SU1522216A1 - Device for checking control computer - Google Patents

Abstract

The invention relates to computing, in particular, to the design of devices for monitoring and protecting against failures in control computers. THE PURPOSE OF THE INVENTION IS THE IMPROVEMENT OF THE CONTROL RELIABILITY. The goal is achieved, a device for monitoring of the control computer, CONTAINING decoders, four FFs, two OR three elements and two elements DELAYS TWO pulse shaper, two registers, Schema Compare, additionally introduced the first and second blocks of non-volatile memory, TRANSMISSION TEAM DEFINTER, SWITCH, FIRST AND SECOND ADDERS, DELAY ELEMENT, TWO ELEMENTS OR, FOUR ELEMENTS AND NO ELEMENT. THE DEVICE ALLOWS TO FIX A DISTORTION AS A RESULT OF MALFUNCTION OF ANY BITS OF INFORMATION INTRODUCED IN THE PROCESSOR OF THE MEMORY COMPUTER FOR THE PROGRAM STORAGE. 5 IL.

Description

The invention relates to computing and can be used in computer-based automatic control systems for monitoring the execution of computer programs and restoring the computational process when a computer fails.

The purpose of the invention is to increase the reliability of the control.

Fig about 1 presents a functional diagram of the device.

The device contains the first block of permanent memory (BPSH) 1, the second block of permanent memory (BPP2) 2, the first element OR 3, the element NOT 4, the first element AND 5, the second element AND 6, the third element OR 7, the first driver pulses 8, fourth

element 9, the second delay element 10, fifth element 11 and 11, the decoder 12 transition commands (DCT), the first trigger I3, the third element And 14, the second element OR 15, the second trigger 16, the decoder 17, the first element 18 delay, the third trigger 19, third delay element 20, fourth OR element 21, sixth element AND 22, second pulse generator 23, first register 24, switch 25, comparison circuit 26, fourth trigger 27, seventh element 28, first adder 29, second adder 30 , second register 31, data bus 32 (ISC), address bus 33 (ША), request input 34, request input 35, input ENTER 36, entrance 37 of feature start command (TC), the input

: l

uh o

38 signals OUTPUT, passive device synchronization input 39 (CIP), AO input of a request for a random access memory (CDR), input 41 of a request for external devices (PCR), input 42 of the preGost signal (PREP), input 43 of the initial setup signal (CU)

Figo 2 shows a timing diagram of the operation of the device in the absence of a malfunction in the equipment of a controlled computer, where the PDD is information on data bus 32; Sha - information on the bus address 33; ZRBPP - request signal B1Sh1 1; ENTER - the input signal information in the processor controlled by the computer on the signal line ENTER 36; T1 is the signal at the inverse output of the first trigger 13; ScBPP2 - a signal to read information from BPP 2; T2 is the signal at the forward output of the second trigger 16; JC - signal of the beginning of the command on the NC 37 line; ZRP - signal recording in WG1 24; SIP - synchronization signal of the passive device on the SIP 39 signal line; WG2 content WG2 31; PREP - interrupt signal on the PREP 42 signal line; РГ1 contains KOP WG1 24 - operation code of the command of the controlled computer | KS control szgmma; ut, is the delay time of the first element of the pilot 18; & t, j, is the delay time of the second delay element 10; bt is the delay time of the third delay element 20o

Fig. (, 3 shows the time diagram of the device operation at the moment of fixation of a failure, where the SM is information on data bus 32, IBA is information on address address 33, ZRBPP is request signal BS1111, ENTER information input signal to the processor on signal line ENTER 36 , TI is the signal at the inverse output of the first trigger 13, SCBSB12 is the read signal NPP2 T2 is the signal at the direct output of the second trigger 16, NC is the command start signal on the signal line NC 37, RFR is the recording signal in WG1 24, CIP is the synchronization signal passive device on the signal line SIP 39, WG2 - content e WG2 31, PREP - interruption signal on the PREP 42 signal line, WG1 - content of WG1 24, CPC operation code of the current command controlled by the computer, delay time of the first delay element 18, bt, - delay time

,

d 0

five

ki of the second delay element 10; utj is the delay time of the third element 20; COP - control amount

Fig. O4 shows the timing diagram when exiting the interrupt and restoring the computational process, where the AHD information is on the data bus 32, the EI is the information on the address bus 33, the RDD is the request signal of external devices of the computer controlled ENTER to the input processor signal INPUT 36, LH - signal at the output of the decoder 17, PREP - interrupt signal on the PREP 42 signal line, WG1 - contents of WG1 24, COP - operation code of the current command of the controlled computer

Fig. 5 shows the location of the information in BS111 and BPP 2, where A is the relative twelve-address address of the BS 1 and BS12 2 cells, the CPC is the opcode.

The device works as follows

The work program of the controlled computer is entered in BPP1 1, and all software constants in PC2 2, Twelve-digit relative addresses of LSI I and BPP2 are the same, but the absolute six-ad address of BSBP 1 and B1Sh2 2 are different. The most significant (13-15) bits of the absolute address are sent to the computer address selector, which returns control signals from BPP1 1 or BSHT2 2. Thus, the computer processor accesses BPP 1 and BSh122 when reading commands and program constants. The computational control of the emissive emulator at the end of each linear section when reading from the runway I of the transition command by comparing the buried in WG2 3 suymy with the control, recoverable ns BPP2 2, Twelve-bit relative addresses of transition cells ( cop), and BSh12 2 cells containing checksums of the corresponding linear sections coincide

(Fig, 5),

I

Consider the execution of the i-th single-word transition command, consisting only of the transition operation code (CCPP), in the absence of failures during the execution of a given linear segment (FIG. 2), the computer processor transmits the address

515

The BNP1 1 cells containing the CPC, after setting this address to the VA 33, the computer address selector generates a signal ZpRBPSH, which via line 34 goes to the first input of the first element OR Zo At the second input of the first element OR 3 at this moment the level O from the output of the element NOT 4 and therefore from the output of the first element OR Z. the blocking input Б1Ш1 1 receives a level signal О, allowing the operation of БПП 1 о After that the computer processor generates signals НК and ENTER, signaling that the processor is ready to receive information from БПЛ1 1 Signal ENTER from line 36 via line The second element 9 is fed to the input of the second delay element 10, from the output of which the computer receives a CIP signal on line 39 delayed by time ut relative to the input signal needed to operate first BPP1 1, then the first 29 and second 30 adders At the same time, the INPUT signal is fed to the input of the BS111 1, from which KOni is read on SM 32 o The first four bits (o –3) of the CPC are fed to the first information input of the switch 25, which is a level 1 signal from the output n element II is included in the transmission of information from The first input to the output, bits 4–15 of the CPC, enters the first information input of the first adder 29 The second information inputs of the first 29 and second 30 adders receive information from the output of the second register (WG2) 31, which is currently located The output of the first 29 and second 30 adders appears KS, KCi, + KOP and on the front 1 (O sip signal), arriving at the entry of record РГ2 31, KS is recorded; in WG2 31, the CS appears at the second information input of the comparison circuit 26 at I

The transition instruction decoder (DCT) 12 is a one-bit permanent programmable storage device with an absolute address field corresponding to the absolute address field of the BNP1 1, and the addresses of the BNP cells 11 that store the codes of the transition operations are entered 1, and in the remaining cells DCT 12 - O. S

66

By the appearance of the address of the BPP1 cell holding KOPP, on G1A 33 from the output of DCT 12, the addresses 1, which are stored in the transfer operation codes, are entered in the addresses of the BSHT1 1 cells that are stored in the rest of the DCT 12 cells, containing KOOP, to SHA 33 from the output of DCT 12 to the information input of the first trigger 13 a level signal is received. On the front. The first trigger signal is set to one. 13 and the level signal O from the inverse of the first trigger 13 is fed to the first input of the third element of the IPI 7. On the front of the input signal, the output level of the first pulse shaper 8 is set, this signal goes to the second input of the third element OR 7, at the output of which the signal СББШ12 appears, of the inputs through the first 5 and second 6 elements AND, respectively, to the input and input blocks of the БШ12 2 о From the БПП2 2 to ШД 32 the checksum of the CS is read; information is supplied to the first data input of comparator circuit 26, which outputs the coincidence of codes in both information input signal is at level O, supplied to the data input of the fourth flip-flop 27

 The signal BFBP2 is fed to the input of the third delay element 20, which delays the front of the signal from BFBP2 for the time At necessary to operate first BPP2 2 and then the comparison circuit 26 The signal from the output of the third delay element 20 goes to the synchronous input of the fourth trigger 27, which remains in zero state since at its information input at this moment the level O from the output of the comparison circuit 26, when the information on the inputs of the comparison circuit 26 coincides, the interrupt signal (PEPP) from the direct output of the fourth trigger 27 does not form

The signal from the output of the third delay element 20 simultaneously enters the input of the first delay element 18, which delays the signal by the time ut, in order for the fourth trigger 27 "to trigger. The level signal O from the output of the first element

delay, which through the third element And 14 is fed to the zero inputs of the first trigger 13 and РГ2 31jC6pacH- the first trigger 13 with РГ2 ЗCO one-time level signal О from the output of the first delay element is fed to the first input of the second element OR 15, the second input of which level signal O from the direct output of the fourth trigger 27, On the front of the signal from the output of the second element OR 15 to the one state the second trigger 16, to the information input of which receives a signal of level 1 from the output of the DCT 12o

After executing the transition command to the linear processor, the computer processor sends the address of the CPC via SM 32; after setting this address, a signal appears on the AA 33, the signal is received, then the processor generates the signals NC and ENTER. The third trigger 19 is set on the edge of the NK signal in a single state, since its information input at this moment contains a level 1 signal from the direct output of the second trigger 16 At the inverse output of the third trigger 19, a WG recording signal is generated, on the front of which A recording is being made with the VA 33 address-. sa KOP ;, at the same time, the STD signal through the sixth element I 22 is fed to the input of the second pulse driver 23, at the output of which a reset pulse of the second 16 and third 19 triggers is formed. On the front i | The YiiQ4 of the CIP signal records information from the outputs of the first and second .30 adders to WG2 31. Thus, the device controls the correctness of the i-ro linear section, and if the latter was completed without errors, the address of the first command of the next j-ro linear is remembered. plot (address

cop.

Claims (1)

Invention Formula A control computer control device containing a decoder, four flip-flops, two OR elements, three AND elements, two delay elements, two pulse shapers, two registers, a comparison circuit, the decoder input connected to the device's address input, the output of the first The delay element is connected to the first inlet of the second element OR, characterized in that, in order to increase the reliability of the control, two fixed memory blocks, a decoder transition coder, a switch, two adders, a third horn, third and four - Qth of the element OR, fourth, fifth,. the sixth and seventh And elements and the NOT element, the information inputs of the transition command decoder and the first register are connected to the device’s address input 5, the first and second blocks of the fixed memory are connected to the device’s address, the outputs of the first and second memory blocks register, the first input 0 of the comparison circuit, the first information input of the compressor, the first information input of the first adder is connected- ". chen to the information entry-exit. device, the output of the second register 5 is connected to the second input of the circuit comparison, the second information input of the first adder and the first information input of the second adder, the outputs of the first and second adders 30 are connected to the information input of the second register, the switch output is connected to the second information a1 input of the second adder, the transfer output of which is connected to the input, transfer the first adder, the first input of the first element OR is connected to the first input of the device request, the output of the first element OR is connected to the blocking input of the first 4Q permanent memory block, the input is read and the first block of the permanent memory and the first input of the second element AND, the input of the first driver and pulses, the synchronous input of the first trigger, the second input d5 of the fourth element OR, and the first input of the fourth element AND are connected to the input of the device, the first input of the first element I is connected to the second input of the device request, the output of the first element And is connected to the input of blocking the second block of the permanent memory, the input of which is connected to the output of the second element AND, the second input of which is connected to the output of the third element OR, watts the input of the first element And the input of the third delay element and the input element is NOT, the output of which is connected to the second input of the first element OR, 50 55 the output of the transition instruction decoder is connected to the information inputs of the first and second triggers, the inverse output of the first trigger is connected to the first input of the third element OR, the second input of which is connected to the output of the first pulse shaper, the decoder is connected to the first input of the seventh element AND and the first input of the fourth element OR, the output of which is connected to the input of the first register register, the input of which is connected to the inverse output of the third trigger and the second input of the sixth element AND, the first inputs of the sixth And the third And elements and the second input of the seventh And element are connected to the initial setup input, the output of the seventh And element is connected to the zero input of the fourth trigger, the direct output of which is connected to the second input. The second OR element and the output of the device interrupt, the output of the first the delay element is connected to the second input of the third element I, the output of which is connected to the inputs of the installation in O of the first trigger and the second register a, the output of the sixth element I is connected to the input of the second pulse shaper, the output of which is connected to nu0 five Q 5 About the left inputs of the second and third triggers, the output of the second element OR is connected to the synchronous input of the second trigger, the direct output of which is connected to the information input of the third trigger, the synchronous input of which is connected to the input of the sign of the device command start, the output of the third delay element is connected to the input of the first delay element and the synchronous input the fourth trigger, the information input of which is connected to the output of the comparison circuit, the second input of the fourth element I is connected to the input of the output of the device, the output of the fourth element And connected to the input of the second delay element, the output of which is connected to the recording input of the second register and the first synchronization output of the passive device, the first and second inputs of the fifth And element are connected respectively to the request inputs of the random access memory and external devices, the output of the fifth And element is connected with the control input of the switch and the blocking input of the first adder, the inputs of the input, output, request for the random access memory and the request for external devices are connected to the second information to the input of the switch. (7 ... / 5 1 RP Address cat - {/ uUZ / ha ha not equal to FIG. 2  X Address Kopp ZprBPL (L  A3pecKonj KOnj Address Compiled by I.Safronova Editor A.Dolynich Tehred L.Serdyukova Order 6964/46 Circulation 668 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. D. 4/5 .five Proofreader M.Maksimishinets Subscription