SU1130865A1 - Firmware control device - Google Patents

Abstract

FIRMWARE DEVICE. CONTROL containing the microinstructions memory block, address register, microinstructions register, start trigger, clock generator, address switch, multiplexer and first AND element, the device start input connected to the single trigger trigger input, the single output of which is connected to the clock pulse input , the first output of the clock generator is connected to the first input of the first element And, the output of the address switch is connected to the information input of the address register, the output of which is connected to the input of the block the memory of microinstructions, the input of the logical conditions of the device is connected to the first information input of the multiplexer, the output of which and the first output of the microcodes memory block are connected to the first information input of the address switch, the second output of the microcodes memory block is connected to the information input of the microinstructions register, the output of which is The information output of the device, which is due to the fact that, in order to explore the device’s field of application, an operand1D1y code register, a control register, a counter, and The address of the first microcommand, the converter of the operation code into the code of the number of commands, the block of AND elements, the second and third AND-NOT elements, the OR-NOT element, the OR element, the AND-NOT element, and the delay element, the input of the operation code of the device connected to the information input the operation code register, the output of which is connected to the inputs (L dami of the address generator of the first microcommand and the operation code converter into the code of the number of commands, the output of the address generator of the first microcommand is connected to the second information input of the address switch, the third output the microinstructions memory block is connected to the second informational input of the multiplexer, the fourth output of the microinstructions memory block is connected to the information inputs re9 U1 of the control unit and the first input of the I element block, the control register outputs are connected to the corresponding inputs of the NAND element, the output of the block elements And is connected to the control input of the multiplexer, the output of the operation code converter in the code of the number of commands is connected to the information input of the counter, the outputs of which are connected to the corresponding inputs. and OR NOT, the output of the element ILINE is connected to the control inputs of the address switch and the second input

Description

The first element And whose output is connected to the synchronization input of the counter and the first input of the second element And, the first control output of the register of micro-commands is connected to the second input of the block of elements And, the third input of the first element And and the first input of the third element And whose output is connected to the counting input the counter and the synchronization input of the control register, the second control output of the micro-register register is connected to the synchronization input of the operation code register, and the third control output of the micro-command register is connected to the first input the house of the OR element, the output of which is connected to the zero input of the trigger trigger, the output of the NAND element is connected to the second input of the second AND element, the output of which is connected to the second input of the OR element and is the device error output, the first output of the clock generator the address register, the second output of the clock pulse generator is connected to the synchronization input of the micro-register register and through the delay element with the second, the input of the third element I.

one .

The invention relates to digital computing and can be used in the design of firmware control devices for computers and computing systems.

A microprogrammed control device with a control is known, which contains a microinstruction memory block, an address register, a buffer register, a comparison circuit, AND, OR 1 elements.

The disadvantage of this device is its low functionality, due to the lack of control over the correct operation of the device during the implementation of microprograms.

A microprocessor with a control with a microinstructions memory block, an microinstructor address register, an address register, a buffer register, comparison circuits, AND, OR 12 elements are known.

The disadvantage of this device is the low speed due to the inefficient use of the working time of the device.

The closest to the proposed invention in its technical essence is a microprogrammed control device containing a microinstructor memory block, address and microinstruction registers, a trigger trigger, a generator of tact pulses, an address switch, a multiplexer -and element, and the start input of the device with a single input trigger trigger, a single output of which is connected to the input of the clock generator, the first output of the clock generator is connected to the first input of the first element I; the output of the address switch is connected to the information input of the address register, the output of which is connected to the input of the microcommand memory block; the input of the logical conditions of the device is connected to the first information input of the multiplexer, the output of which, together with the first output of the memory block of micro-commands of the connections, is connected to the first information input of the address switch; The second output of the memory module of micro commands is connected to the information input of the register of micro-commands, the information output of which is connected to the information output of the device 33.

The disadvantage of this device is the narrow scope, due to the inability to implement composite commands. This is because after a firmware that interprets a processor command of a computer,

To determine the code of the next microgram, it is necessary to refer to the main RAM of the processor. With such an organization of operation of the device, after the implementation of the latest program of the current microprogram to determine the address of the first microcommand of the next microprogram, it is necessary to refer to the main RAM of the processor to determine the operation code. Thus, the processor performance is significantly reduced, in which the device is used due to the fact that it is in standby mode all the time after the firmware is executed until the operation code is received. In the known device, there is also no organization controlling the effectiveness of its functioning. This causes low reliability of its functioning, significantly limits its functionality and scope. Thus, the impossibility of implementing composite commands, the time delays in the operation of the microprogram control device, due to the need to wait for the operation code to enter the device and the lack of control over its correct operation, significantly limit the functionality and limit the scope of the device. The aim of the invention is to expand the field of application of the device by providing the microprogram implementation of the composite commands and organizing control over their implementation. The goal is achieved by the fact that the microprogram control unit containing a crock memory block, an address register, a micro-command register, a trigger trigger, a clock generator, an address switch, a multiplexer and the first AND element, the trigger start input of the device connected to a single trigger trigger input, a single the output of which is connected to the input of the clock pulse generator, the first output of the clock pulse generator is connected to the first input of the first element I, the output of the address switch is connected to the information input address register, the output of which is connected to the input of the microcommand memory block, input of logical conditions of the device is connected to the first information input of the multiplexer, whose output and the first output of the microcommand memory block are connected to the first information input of the address switch, the second output of the microcommand memory block is connected to the microinstructions register information input, the information output of which is the information output of the device, is additionally entered the operation code register, control register, counter, and the address of the address of the first microcommand, the converter of the operation code into the code of the number of commands, the block of elements AND, the second and third elements AND, the element OR NOT, the element OR, the element EINO and the delay element, the input of the operation code of the device connected to the information input of the register of the operation code, the output of which is connected to the inputs of the address generator of the first micro-command and the converter of the operation code into the code of the number of commands, the output of the address generator of the first micro-command is connected to the second information input of the address switch, the third output of the block the memory of micro-instructions is connected to the second information input of the multiplexer, a quarter of the output of the memory-storage module of micro-commands is connected to the information inputs of the control register and the first input of the AND block, the codes of the control register are connected to the corresponding inputs of the NAND element, the output of the AND block of the elements the multiplexer input, the output of the operation code converter into the code of the number of commands is connected to the information input of the counter, the outputs of which are connected to the corresponding inputs of the OR-NOT element, the output of the elements and OR is NOT connected to the control inputs of the address switch and the second input of the first element AND, the output of which is connected to the synchronization input of the counter and the nepBbiM input of the second element AND, the first control output of the micro-register register is connected to the second input of the AND element block, the third input of the first element And the first input of the third element And, the output of which is connected to the counting input of the counter and the synchronization input of the control register, the second control output of the register of micro-commands is connected to the synchronization input of the opera code register and the third control output of the micro-command register is connected to the first input of the OR element, the output of which is connected to the zero input of the trigger trigger, the output of the AND-NOT element is connected to the second input of the second element AND, the output of which is connected to the second input of the OR element. the output of the device error, the first output of the clock generator is connected to the synchronization input of the address register, the second output of the pulse generator is connected to the synchronization input of the microcommand register and through the delay element to the second input the third element And the essence of the invention consists in expanding the field of application of the device by executing “composite” commands based on the firmware implementation of transitions between commands by recording the next operation code in the address field of the last microcommand of the current firmware; organizing the control of composite commands by adding control characters recorded in the free fields of the logical conditions of the last microcommands in the microprograms. In the process of implementation by the firmware of the control of the command commands, the code corresponding to the address of the first micro command of the next microprogram is recorded in the address field of the last microcommand. If a composite command is implemented that contains four firmware, the codes corresponding to the addresses of the first microcommands of the second and fourth microprograms will be recorded in the last microcommands of the first microprogram, respectively. In the logical conditions field of the last microcommand of the first microprogram, the code K will be written in the corresponding field of the last microcommand the second firmware will be recorded code K, in the corresponding field of the last microcommand of the third firmware will be written code K, and in the field logic services Wii Firmware fourth last microinstruction we will be written K. code correctness vsholneni compound command is determined by adding to the modulo two control codes after the end of the last microinstruction vtolneni latest firmware. Consequently, the use of the natural redundancy of micro-command formats allows for the implementation of composite commands to make a transition at the microprogram level of the meshes with their elementary commands and organize the koHTponb to correct the implementation of commands, which increases the speed of the processor in which the device is used and the reliability of its operation and thereby contributes expansion of its application area. The invention is implemented by introducing the following elements and bonds. The introduction of the operation code register and the relations determined by it is necessary to record the operation code and its storage. The introduction of the register of controls and the relations determined by them is necessary for organizing the control of the correctness of the implementation of composite commands by the summation pug modulo control tags. The introduction of the counter and the links due to it is necessary to organize the account of the implemented elementary commands that make up the composite command. The introduction of the shaper of the address of the first micro-command and the links due to it is necessary for the formation of the address of the first micro-command of the implemented microprogram using the on-code. The introduction of the operation code converter into the code of the number of commands and the connections due to them is necessary to form the code of the number of elementary commands implemented by the device according to the corresponding operation code. The introduction of the block of AND elements and the connections caused by it is necessary to control the transfer of the checked conditions to the multiplexer microcommands of conditional jumps. The introduction of the second And element and its agreed connections is necessary to form a device interruption signal in the event of a fault or error. The introduction of the third element AND and the relations conditioned by it is necessary for generating signals in controlling the operation of the control register and the counting pulses of the number of elementary commands implemented. The introduction of the NAND element and the conditional links are necessary for generating an error signal when the code value recorded in the control register is not equal to zero. The introduction of the OR element and the links due to it is necessary to form a signal for the device to stop working when a failure occurs, as well as by. signal of the end of work of the register of microcommands. The introduction of the OR-NOT element and the links due to it are necessary to form an address switch control signal to write the address code of the next microcommand into the address register, as well as a signal allowing the code of the number of elementary commands to be written to the counter. Thus, due to the introduction of new elements and connections, the firmware control unit provides a higher speed and reliability of the processor, which greatly expands its functionality and scope. FIG. 1 shows a functional diagram of the firmware. Controls: FIG. 2 - time diagram of his work. The microprogram control unit (Fig. 1) contains a block of microinstructions memory 1, a counter 2, an operation code register 3, an address register A, microinstructions register 5, a control register 6, an address controller of the first microcommand, preob (the distributor 8 of the operation code in code of the number of commands, multiplexer 9, switch 10 addresses, trigger 11 start, generator 12 clock pulses, first element AND 13, third element AND 14, second, element 15, block 16 elements AND, element AND NOT 1 element OR- NOT 18, element OR 19, delay element 20, input 21 of the operation code of the device, input 22 device conditions, device 23 device 23 output, first control output (command end) 23.1 of the micro-register 5 register, second control output (code entry) of operation 23.2 of the micro-command 5 register, third control output (end of operation) 23.3 of the micro-command register 5, the output 24 of the device start-up the first output (non-modifying bits of the address code) 25 of the micro-instruction memory block 1, the third output (of the address code bits being modified) 26 of the micro-instruction memory block 1, the fourth output (logic code of the 5 8 vii) 27 of the memory block 1 ti microco mand, the second output (micro-operations) of 28 block 1 of microinstructions memory, output 29 errors of the device. The purpose of the main elements of the firmware control device (Fig. 1) is as follows. Block 1 of the microinstructions memory is intended for storing the firmware implemented by the device. Counter 2 is designed to record and count the number of implemented firmware. The firmware number code is written on the falling edge of the synchronization pulse. The subtraction of 1 from the counter content is also carried out on the trailing edge of the counting pulse. Register 3 of the operation code is designed to record and store the operation code. The operation code is recorded on the leading edge of a clock pulse. Register 4 addresses is designed to store the address of the next microcommand. The next address is written to the address register 4 on the trailing edge of the first clock pulse generated by the 12 clock pulse generator. Register 5 of microinstructions is intended for receiving, storing and transmitting microinstructions with the following fields: informational (microoperations); managers; labels for the end of the command, entering the operation code, the end of the device operation. The information field records the codes of micro-operations of microcommands implemented; In the Targets field of the last microcommand command, the microprogram call is recorded 1. For the remaining commands, the value of this bit is O. The label field of the operation code records a single signal of the last microcommand of the last microprogram of a component or elementary command. For the remaining microinstructions, the value of this is different; It is equal to O. In the field labeled End of Device Operation, a single value is recorded in the microcommand, after the implementation of which it is necessary to interrupt (finish) the operation of the device. For the remaining microinstructions, the value of this bit is O. The register 6 of the control is performed on Ttriggers and is intended to organize the control of the correct functioning of the device by summing modulo the control signs coming from the output of the logical conditions 27 of the microcommand memory 1. The summation is performed on the falling edge of the counting pulse of the number of implemented microprograms.

The first microcommand address generator 7 is designed to generate the address code of the first microcommand of the firmware being implemented using the operation code, the operation code converter 8 to the command number code is designed to generate the code of the number of firmware to be implemented in accordance with the operation code.

Consider a specific example of the algorithms for the operation of the driver 7 and converter 8, i.e. algorithms for generating the codes of addresses of the first microinstructions and the codes of the numbers of the implemented microprograms.

Suppose that the entire set of processor commands that must be implemented can be represented as follows

K Kf UKf3UKf UK,

where K is a composite command K, which is implemented by a device in accordance with a specified sequence Kg - a compound command - a composite command Kg Kg; K, is an elementary processor command corresponding to the processor command (the K command may coincide with any of the elementary K -Kg commands).

Let the composite command correspond to the operation code 001; the composite command K is the operation code of the SYu; the composite command K is the operation code 011, and the elementary command corresponds to the operation code 100.

In accordance with the operation code, the driver 7 generates the address code of the first microcommand of the first microprogram in the implemented composite (elementary) command.

Shaper 7 implements a system of Boolean functions consisting of controls, each of which describes a corresponding shaper output and is represented as a disjunctive normal form. The number of equations in the system is determined by the width of the address of the microinstructions. Let the address width be 4 and choose the following coding start address address. Upon receipt of the operation code 001 corresponding to the composite command K, the code 0001 is generated at the output of the matrix; upon receipt of the operation code corresponding to the composite command, code 0101 will be generated; upon receipt of the operation code 011, corresponding to the composite command Kj. code 1000 is generated; upon receipt of the operation code 100, corresponding to the elementary command, the code 1010 is generated.

Then the control system implemented by the shaper 7, will have the form.

WITH,

3 .3

4 .X.1 ...

where Ci. () i is the output variable of the photo sweep 7, corresponding to the i-th digit of the address code; xj () is the j-input of the variables for the corresponding j-th digit of the operation code.

In accordance with this control system, the driver 7 can be implemented on a programmable, logical matrix having three inputs x, X2, Xj, and output circuit C, C, C3. C4.

Converter 8 generates a code for the number of microprograms interpreting the instruction implemented by the processor. Implementing a composite K command requires the execution of four firmware; implementation of a composite K command — three microprograms; implementation of a composite K command — two microprograms; implementation of the elementary team to | will require the execution of only one firmware. When the converter arrives at the input 8 of the operation codes 001, 010, 011, 100, the codes of the number of firmware 100, 011 010, 001 will be generated at its output, respectively.

The control system implemented by the converter 8 is

С х Х2Хз;

, 7 3 7 (And

in accordance with this control system, the converter 8 can be implemented on a programmable logic array having three inputs x ,, X2, Xj, and three outputs C, and Cj,

Multiplexer 9 is designed to modify the address of the micro-command following the branch micro-command. The address modification is carried out by changing the value of the last bit of the address bits being modified. For this purpose, the first information input from the input 21 of the device receives a code of logical condition values. The control input of the multiplexer 9 receives the code of the checked logical conditions. The second information input of the multiplexer 9 receives the values of the most modified modified address bit. When the values of the checked logical conditions equal O, the values of the modified address bits do not change. The address of the next microcommand is determined by the value of the address code at the first 25 output of block 1 of the memory of microcommands; Otherwise, the address is modified by changing from zero to one the value of the modified address bit. The address of the next micro-command is determined by the unmodifiable bits received from the first 25 output of the micro-command memory block 1, and the modified bit from the output of the multiplexer 9. The address switch 10 is used to organize the address of the next micro-command. When implementing the first microcommand of composite and elementary commands, the code of the address is postpassed from the output of shaper 7 to the second information input. The address of all other microinstructions is delivered through the first information input. The trigger 11 is designed to control the operation of the generator 12 clock pulses. A clock pulse generator 12 is designed to generate clock pulses. The sync pulses from the first output synchronize the writing of the code of the numbers of elementary commands to counter 2 and the writing of the code of the address to the register 4 of address. The sync pulses from its second output synchronize

write code microinstructions in register 5 microinstructions.

The first element AND 13 is designed to control the synchronous input of the counter 2. The block 16 elements AND is intended to control the feed to the multiplexer 9 of the code of the checked logical conditions.

The second element 15 is designed to generate a device interruption signal in the event of a fault or an error in the operation process. The third element And 14 is designed to control the supply of pulses to the counting (subtracting) input of counter 2. The AND-NE element 17 is designed to generate a device error signal. The element OR 19 is designed to form a zero reset signal for the trigger 11. Element IPI-NE 18 is designed to control the operation of the address switch 10 when writing information to the address register 4 and generating a permission signal to write information to counter 2. Delay element 20 is designed to delay a clock from the second generator output 12 clock pulses to time tj, and Tj more time switching memory register 5 microinstructions. Device input 21 is an operation code input that determines the address of the first microcommand. The firmware control device operates as follows. In accordance with the operation code received at the device input 21, the address code of the first microcommand is recorded in the 4 address register and the microprogram number code in counter 2. Thus, the receipt, operation code 001 corresponding to the composite command ,,, will be in address register 4 code 0001 is recorded, which corresponds to the address of the first microcommand of the first of four implemented firmware. In counter 2, the code 100 will be written, corresponding to the number of the firmware being implemented. Information is recorded in the address register 4 and the counter 2 is carried out simultaneously on the clock pulses received from the first generator output of 12 clock and pulses. After reading the information from block 1 of micro-instruction memory, it is written to register 5 of micro-instructions to control the operation of the processor. The information is recorded in the register of 5 micro-instructions using sync pulses from the second output of the generator 12 clock pulses. The address of the next mic command from the first 25 output of the micro-instruction memory block 1 through the address switch 10 is written into the address register 4 to further implement the micro-command processing cycle. If it is necessary to go to the address of the next microcommand by the conditional transition in multiplexer 9, the next address bit is modified by the code of the conditions being checked and their value. With a zero value of the checked logical condition, the address of the next microcommand is completely determined by the values of the unmodifiable address bits. In the case of a single value of the condition, the address of the next microcommand changes by one (in the low-order series). After the last micro is recorded, the commands of the first microprogram are registered in the register, the third channel: roo commands decrease the content of counter 2 by one and the control sign K is written to the control register 6. Since the implemented command K is composite, the address of the first microcommand of the next firmware through the address switch 10 is written to the address register 4 from the first output of the microcommand memory 1. After the implementation of the second firmware, the state of the counter .2 also changes and the second control sign K is written to the 6th register. Upon completion of reading the last microcommand of the latest firmware, counter 2 is zeroed and the inverse outputs of register 6 of the control are interrogated. During: normal operation of the device after the last elementary command has been executed, register 6 must be reset and the signal at the output of the NAND 17 signal is O. In case of a failure or failure in the process of the device functioning with the blocking signal, the trigger 11 is reset and the device operates in the operating mode will be banned. In the absence of failures or failures in the operation of the device, the cycle of implementation of the next command with the corresponding operation code will be repeated. In the case of execution of an elementary command K implemented by a single microprogram, the operation of the device will be similar to that described, however after reading the last microcommand of the microprogram, a code consisting of all zeros will be entered into the control register 6. The firmware control device operates as follows. In the initial state, all the storage elements of the device (Fig. 1) are in the zero state. At the output of 23.2 register 5 there is a single signal. The operation code, corresponding to the code of the composite command K and equal to 001, is received from the input 21 of the operation code of the device to the information input register 3 of the operation code. Using the enable signal from the second 23.2 control output of the register of 5 micro-commands, the operation code is written to the register 3. Shaper 7 generates an address code 0001 of the first micro-command of the first microprogram. The address code arrives at the second information input of the address switch 10, the control input of which receives signal 1 from the output of the element OR NOT 18. Transformer 8 generates a code for the number of microprograms that will be implemented during the execution cycle of the Kf command. According to the Start signal from the input 21 of the device, the trigger 11 is set to one state and turns on the generator of 12 clock pulses. The sync pulse from the first generator output of 12 clock pulses is fed to the synchronous input of the 4 address register and, at the back front of the generator, efc records the address code received to its information input from the output of the address switch 10. In addition, the clock pulse from the first generator output 12 clock pulses enters the first input of the first element 13, the second and third inputs of which are opened with single signals from the output of the OR-NO 18 element and the output 23.1 of register 5 micro-instructions, respectively. At the output of the first element And 13, a pulse is formed, which is fed to the synchronous input of counter 2 and its rear edge records information received at its information inputs from the output of converter 8 After the information is recorded, the contents of counter 2 become different from zero and at the output of the element OR -NON 18 appears a zero signal, which blocks the flow of information through the second information input of the address switch 10 and allows it to pass through the first information one; the entrance. In addition, this signal closes the first element of AND 13, thereby prohibiting the formation of a sync pulse at its output and polling the state of register 6 of the control. After writing the address of the first micro-command to the register 4 of the address, the corresponding micro-command is read from block 1 of the micro-instruction memory. The unmodifiable bits of the address of the next microcommand from its first output 25 arrive at the first information input of the switch 10 of the address, which is opened by the control signal from the output of the AND-NOT element 18. The modified address of the address of the next microcommand comes from the third 26 output of the micro memory 1 block commands to the control input of the multiplexer 9. If the microinstruction realizable is not a microcommand of a conditional transition, then the field of logical conditions is free. From the second output 28 of block 1 of the memory of microcommands, the micro-operation code, and the control marks are fed to the information input of the register of 5 micro-instructions. On the falling edge of the sync pulse, which comes from the second output of the generator 12 to the synchronous input of the register 5 micro commands, information is recorded. Codes of micro-operations are received at output 23 of the device The zero signal from the output 23.1 of the register 5 microinstructions is fed to the second input of the element And 13, the control input of the block 16 of the elements And, and to the first input of the element And 14, closing it. The sync pulse from the second generator output 1.2 of the clock pulses through the delay element 20 will arrive at the second input of the element 14 after a time T. There will be no change in the state of the counter 2. By the next pulse from the first output of the generator 12 clock pulses, the code of the ad-1 5-second of the second micro-command will be written into the 4-address register. In the future, the operation of the device will continue as described. . . When writing the last microcommand of the first microprogram, the signal value at the output 23.1 of register 5 microcommands changes to the opposite. A single signal from this output blocks the element AND 16, opens the element AND 14 and arrives at the element 13 blocked by the zero signal from the output of the element OR-NOT 18. The clock pulse from the second generator output 12 clock pulses through the delay element 20 enters the first input of the open element AND 14, at the output of which an impulse is formed, acts on the counting subtractive. ; the input of counter 2 to the synchronous register 6 of the control allows the recording of the control code recorded in the field of the microcommand logic conditions in the register 6. The address code of the first microcommand of the second microprogram is recorded in the address field of the read microcommand. In the future, the operation of the device will be similar to that described until the last microcommand of the latest firmware is read. When reading the last microcommand of the latest firmware from block 1 of the microinstructions memory, the value of the address code is zero. The trailing edge of the sync pulse arriving at the microcommand sync input records information into register 5. A single signal from output 23.1 goes to the first inputs of the And 13, And 14 elements. From the output of the Delay element 20, a pulse goes to the second input of the And 14 element,. The single signal at the output of this element allows the writing of the control code recorded in the field of logical conditions of the read command to the register 6 of the control. In addition, the signal 2 resets the counter 2 and the output of the IDI-NOT 18 element receives a signal 1, which goes to the third input of the And 13 element, keeping it open, as well as controlling the input of the address switch 10, prohibiting transmitting the address on the first information input and allowing transmission on the second information input.

The clock pulse from the first output of the generator 12 clock pulses will go to the first input of the element And 13 and to the synchronization input of the register 4 addresses. The single signal formed at the output of the element And 13 will go to the first input of the element 15 and interrogate the state of the inverse outputs of the register 6 of the control. In the case of an error-free implementation of the firmware, all inverse outputs of register 6 of the control will be single signals, the output of the NAND 17 element is a zero signal that arrives at the second input of the And 15 element. The error signal of the device will not be generated in this case.

In case of incorrect implementation of the composite command, the value of the checksum stored in register 6 of the control is different from zero, and then a single signal is present at the output of the NAND 17 element. As a result, an error signal will be generated at the output of the element 15, which is fed to the second input of the element OR 19, this signal will trigger the trigger 11 and the device will be blocked.

When implementing the elementary command K., the driver 7 will generate the code of the address of the first microcommand equal to 1010. The converter will generate the code 001 on its input. The operation of the device on the implementation of the microprogram will not differ from that described. When executing the last microcommand of the microprogram, except for the zero code of the address of the next microcommand, the field of logical conditions will also be zero.

The use of the invention will expand the field of application of the device due to the implementation of the possibility of implementing the remaining commands. but

Figure 1 23

Fig2

Claims (1)

MICROPROGRAM DEVICE "CONTROLS containing a memory block of microcommands, an address register, a register of microcommands, a trigger trigger, a clock pulse generator, an address switch, a multiplexer and a first AND element, the trigger input of the device being connected to a single input of the trigger trigger, the single output of which is connected to the input of the generator generator clock pulses, the first output of the clock generator is connected to the first input of the first element And, the output of the address switch is connected to the information input of the address register, the output of which is connected to the input of the micro-command memory block, the input of the logical conditions of the device is connected to the first information input of the multiplexer, the output of which and the first output of the micro-command memory block are connected to the first information input of the address switch, the second output of the micro-command memory block is connected to the information input of the micro-command register, the output of which It is an information output of the device, which consists in the fact that, in order to expand the scope of the device, a code of operations code, a control register, and an account are entered into it. chik, driver of the first micro-command address, converter of the operation code into the code of the number of commands, block of AND elements, second and third AND-NOT elements, OR-HE element, OR element, NAND element and delay element, the device operation code input being connected to the information input of the operation code register, the output of which is connected to the inputs of the address generator of the first microcommand and the code converter ^ operations into the code of the number of commands, the output of the address generator of the first microcommand is connected to the second information input of the address switch, third the first output of the micro-command memory block is connected to the second information input of the multiplexer, the fourth output of the micro-command memory block is connected to the information inputs of the control register and to the first input of the block of AND elements, the outputs of the control register are connected to the corresponding inputs of the AND-NOT element, the output of the block of AND elements is connected to the control the multiplexer input, the output of the operation code converter into the code of the number of commands is connected to the information input of the counter, the outputs of which are connected to the corresponding inputs of the OR-HE element, the output q element ORINE is connected to the control inputs of the address switch and the second input SU „1130865 of the first element And, the output of which is connected to the synchronization input of the counter and the first input of the second element And, the first control output of the micro-command register is connected to the second input of the block of elements And, the third input of the first element And and the first input of the third element And, the output of which is connected with the counter counter input and the control register synchronization input, the second control output of the micro-command register is connected to the synchronization input of the operation code register, and the third control output of the micro-command register is connected to the output of the OR element, the output of which is connected to the zero input of the start trigger, the output of the AND gate is connected to the second input of the second AND element, whose output is connected to the second input of the OR element and is the device error output, the first output of the clock generator is connected to the input synchronization of the address register, the second output of the clock generator is connected to the synchronization input of the register of microcommands and through the delay element with the second input of the third element I.