SU1270772A1 - Microprogram device with checking - Google Patents

Abstract

The invention relates to computing and is used to build microprogrammed control devices. The aim of the invention is to increase the reliability of the device. The invention monitors the correctness of the course of the program by controlling the address functions of the previous and subsequent commands. The invention also lays out the initial microcommands when changing commands by setting error labels. 1 il.

Description

"1 The invention relates to automation and computing and can be used in the construction of computer control devices and microprogrammed computer systems. A firmware is known that contains two memories, a pulse generator, triggers, registers, an address counter, a switch, and OR elements. A disadvantage of the known device is a large amount of monitoring equipment, which significantly complicates the device and reduces its reliability. The disadvantage is also the low reliability of operation, which is due to the fact that the device lacks special technical means that control the correctness of functioning in such phases as address information selection, transition to the control channel, control information selection and transition to the address channel. All this ultimately reduces the reliability of the device. In addition, natural structural redundancy inherent in microprogram devices with standard memory blocks is not used to increase confidence. Thus, for example, free zones of the persistent storage device can be filled with special control information for signaling errors. Closest to the proposed technical essence and achievable positive effect. is a microcontroller with control, containing a command counter, the output of which through the command is connected to the inputs of the address switch, the comparison unit and the buffer register, the output of which through the serially connected comparison unit and the first control register is connected to the input of the first OR element, the output of the switch addresses through the serially connected address register and the memory of micro-commands are connected: To the inputs of the address switch, co-switch of logical conditions, the register of micro-commands and the first register a roll, a pulse generator, the lane output of which is connected to the inputs 22 of the microinstruction register and through the first AND element to the input of the buffer register, the second output of the pulse generator is connected to the input of the address register, the second OR element. In the known device, the principle of two-level firmware control is implemented. In one pamlti block, command codes are stored, in the other, microcommands. The operation of the command and microcommand channels is carried out alternately. The drawback of the device is the low reliability of its operation, due to the lack of means for controlling the sequence of command changes (MiiKponporpaMM) if there are branching commands (conditional jump commands) in the program, and no means of controlling the correctness of hitting the initial microprograms of the microprograms when changing commands. The aim of the invention is to increase the reliability of the device. The goal is achieved by connecting a control counter with a command counter, the output of which is connected to the inputs of the address switch, a comparator and a buffer register through an instruction memory, the output of which is connected to the input of the first control through a serially connected comparator through an instruction memory. element OR, the switch output addresses through connected in series address register and microcommand memory is connected to the inputs of the switch ad-. sa, the switch of logical conditions, the register of microinstructions and the first register of control, the pulse generator, the first output of which is connected to the inputs of the register of microinstructions and through the first AND element to the input of the buffer register, the second output of the pulse generator is connected to the input of the address register, the second element OR, the scheme comparisons, two triggers, second control register, two OR elements, four AND elements, the first output of the pulse generator connected to the inputs of the second, third and fourth element AND and the second register , Vpsody memory soed.ineny microinstruction to the inputs of the switch logiches.kih conditions vtoroto jn third element or trete3. 1st, fourth and fifth elements of AND and the first and second control registers, outputs of the micro-register register Connected to the inputs of the fourth OR element and the address switch, the first AND element, the third OR element and the second control register, the output of which is through the first and quarterly connected elements And the first trigger is connected to the input of the pulse generator, the switch output of the logic conditions is connected to the inputs of the address switch and the fifth element AND, the outputs of the second and third elements OR via the corresponding The second and second elements And are connected to the inputs of the second trigger, whose outputs and command memories are connected to the input of the comparison unit through the comparison circuit, the outputs of the third and fourth elements And are connected to the inputs of the command counter, the output of the first And element . The essence of the invention is to increase the reliability of the operation of the microprogram control unit on the basis of increasing the reliability of the control of the sequence of change of commands (microprograms) in the program. Improving the reliability of the operation of the device is carried out by organizing the control of the correctness of the sequence of change of commands when there are conditional transition commands in the program. To control the correctness of the program’s progress on its linear sections, with unconditional as well as conditional transitions, it is proposed to use the principle of controlling the address functions F (a) .. and F (a) t located in the control field of the command word of the command memory block and connecting two consecutive teams. In this case, the address function of the previous command is stored in the buffer register and compared with the address function of the current command, the comparison circuit. The fact of their incomparability testifies to the presence of an error. In the case of a conditional transition, the address function of the current command is modified in accordance with the value of the logical condition being checked. Moreover, the address functions of commands, the transition to which is possible as a result of the verification of the logical resolution of the 724 VII, should differ in one bit. As a result of modifying the modified bit of the address function of the current command, the value of the logical condition of its code becomes equal to the code value of the address function of the previous command. Depending on the size of the address functions, the required level of confidence in the control of the order of commands can be provided. As the address functions increase, the set of instructions is narrowed, and their number is the same, which leads to an increase in the likelihood of a violation of a sequence of command changes. Improving the reliability of the device is achieved by increasing the control of the correctness of the change of commands by organizing the control of access to the initial microcommands of the microprograms when changing commands. For this purpose, a micro-operation (label) of the error is entered into the micro-command word, which is recorded in all the cells of the micro-command memory block, except the cells with the initial micro-commands of all the micro-programs. Thus, if during microprogram change the first micro-command is read, which is not the initial one, then a single signal of the error label will be recorded as an error signal. Increasing the likelihood of forming and issuing an error is achieved by writing two different error labels to the unused cells. Increasing the diagnostics depth is also achieved by increasing the number of errors to be fixed, i.e. increasing the amount of information about the state of the device. The diagram shows the functional diagram of the proposed device. The device contains a memory of 1 commands with command codes (firmware) 1.1, address 1.2, the address function of the previous command 1.3, address function of the current command 1.4, 2 microcommands with the field of the unmodified part of address 2.1, modified address bit 2.2, code checkable logic conditions 2.3, micro-operations 2.4, error marks of reject-1 type 2.5, error labels of reject-2 type, 2.6, counter of 3 commands, buffer register 4, register 5 addresses, register of 6 microcommands with field of end 6.1 command label, field of microoperations 6.2 and the end of program label field 6.3, register 7 and 8 control, triggers 9 and 10, the switch 11, the logical conditions, the comparison unit 12. The comparison circuit 13, the generator of 14 pulses, the address switch 15, the elements SHIII 16-19, the elements AND 20-24. The device works in the following way. In the initial state, the initial address of the firmware sequence is recorded in counter 3, registers 4.5 and 7.8 are set to zero, In register 6 of micro-instructions, one is written in field 6.1, and zero in field 6.2 and 6 . Triggers 9 and 10 are set to zero. The circuits of the initial installation of the device memory elements are conventionally not shown in the diagram. With a single signal from field 6.1 of register 6 micro-commands, switch 15 is opened to pass information from memory 1 to register 5. In accordance with the address of the command set on counter 3, an initial command word is generated at the memory output. In the field 1.1 of the control word, the address code of the initial microcommand of the first microprogram is specified, which via the switch 15 is output to the register of the address 5. The information from floor 1.2 is returned to the address output of the device. In the field 1.3 of the address function of the previous writing command, the address function (a) and in the field 1.4 of the address function of the current command are written zeros. The code of the address function of the current command is compared by block 12 with the code set in register 4. In case of a mismatch, an error signal is generated at the output of comparison block 12. The operation of the device begins with the supply of an enable signal, according to which the trigger 9 is set to one and the generator 14 starts. On the falling edge of the clock pulse of the generator 14, the initial firmware address code is written from field 1.1 of memory 1, through switch 15 to register 5 In accordance with the address set in register 5, the microinstruction code is formed at the output of memory 2 of micro-instructions. If in the formed microprogram initial microcommand — in field 2.6, single error marks of defect-2 type and command ends are recorded, this means that during a microprogram change, a transition was made to a micro-command that was not the initial one in the next microprogram. This signal will be recorded in the second register de register 7 at the falling edge of the signal from the output of element I 20, since it is opened with a single signal from the end of the command from the floor 6.1 of the register 6. In addition, using the same clock pulse, the first bit of the register 8 The signal value of the end command label will be recorded. At the outputs of registers 7 and 8, which are outputs of the device, an error type code will be generated, and at the output of the OR 16 element, an interrupt signal that is fed to the output of the device can be used in the computing system to interrupt its normal operation and diagnose failures. In addition, the signal from the output of the element OR 16, through the element OR 19, the trigger 9 is set to the zero state and the clock pulse is denied by the generator 14. The device stops its operation. At the same time, the control 1B to the center of the formed microcommand from the field 2.4 of memory 2 over the falling edge of the clock pulse of the generator 14 is recorded in register 6. The code of microoperations from the floor 6.2 of the register goes to the output of the device. The code of the checked logical conditions of this microcommand (information field 2.3) is fed to the input of commander 11, which, depending on the values of the logical conditions, modifies the modified bit of the address part of the microcommand. The code of values of the checked logical conditions enters the switch from the input of the device. The modified address bit from the output of switch 11, as well as the unmodified part of the microcommand address, from field 2.1 of memory 2 goes to register 5 through switch 15, which is open with zero signal from field 6.1 of register 6 to pass the value of the unmodified part of the address of microcommand from memory 2 and mod71

from the output of switch 11 to the input of register 5. The same signal prohibits the entry of information into register 5 from memory 1,

If errors in the operation of the device are not detected, then on the falling edge of the next clock pulse of the generator 14, the address of the next microcommand will be recorded in register 5. On the falling edge of the next clock pulse of the generator 14, information will be recorded in register 8 and register 6 in the same way as described.

If during the implementation of the firmware in field 2.5 of the formed micro-command, a single error mark signal of the Brac-1 type is recorded, this means that the sequence of failures within the microprogram, i.e. when changing microinstructions, an unauthorized transition to an unused memory cell 2 was made.

The fact of violation of the sequence of microinstructions changes in the microprogram is recorded in the first discharge of register 8 on the falling edge of the next clock pulse of the generator 14. An error code and an interrupt signal are output at the device output.

The conditional transition in the program is organized using conditional branch instructions.

In the microcommand for checking the logical condition of the corresponding firmware of the conditional branch in field 2.3, the code of the verified logical condition is specified, in field 2.4 of the micro operation, the microoperation of the conditional branch. In accordance with the code of the checked logical conditions, the OR element 17 forms a single signal, which is fed to the input of the element AND 2D. By this, in the presence of a permissive signal of a conditional transition micro-operation element I 24 opens to receive a signal from the output of the switch 11 and to the input of the trigger 10

The process of modifying the values of the modified bit address microcommand switch 11 logical conditions described above. On the falling edge of the clock pulse, coming through the element I 21 from the generator707728

14 to the trigger 10, it will be set to the state corresponding to the value of the signal at the output of the AND 24 element. And 21 is opened with 5 through the OR 18 element with a single signal of the micro operation of the conditional transition from memory 2.

The output signal from trigger 10, which arrives at comparison circuit 13, 10, modifies the value of one bit of the address function of the current command from field 1.4 of memory 1.

Due to the fact that the address functions of microinstructions, which can be transitioned as a result of filling in a conditional branch command, differ from each other by one, as a result of modifying the address function20 of the current command, the output of block 12 will be a zero signal , and in the case when the transition is not carried out due to the absence of the corresponding 25 conditions.

If during the program execution, as a result of comparison of the address functions of the previous and current commands, at the output of block 12 there is a single signal, then this means that the sequence of execution of commands in the program, i.e. sequence of firmware changes.

The fact of violation of sequence 5 of firmware changes will be fixed when changing firmware in the third discharge of register 7 on the falling edge of the control signal from the output of element 20. The code for the address of the next command in the event of a conditional transition at the command level when performing the checked logical condition is performed as follows in a way.

A single micro-operation signal for recording microcommands for checking logical conditions coming from the memory output of 2 micro-commands will allow the next micro-command to pass through the AND 23 element the clock pulse of generator 14 to the synchronization input of counter 3. On the falling edge of the control signal from the output of element 23 to counter 3 5 will be recorded address code from the input device. In accordance with this address, a control word will be formed at the output of the memory 1.

If the condition for executing the transition in the conditional transition command was absent, the address of the next command is generated by the natural advancement of the contents of counter 3, for which a micro-operative is generated: natural addressing at the output of field 2.4 of memory 2,

The generation of the code of the address of the next microcommand during an unconditional transition in the program is organized in the same way as the conditional transition when the transition condition is fulfilled.

With the natural addressing of commands by a single signal of the micro operation of natural addressing from memory output 2, the oscillator-14 clock pulse through the AND 22 element is allowed. On the falling edge of the control signal from the output of the AND 22 element, the code set in counter 3 is increased by one, t . the address of the next command will be generated. When writing a micro-command to register 6, which is the end of the microprogram, with a single tag signal. End of command from field 6.1, switch 15 closes to pass to register 5 of the next microcommand address code from memory output 2 and allows the incoming micro-command of the next microprogram from field 1.1 memory to be received. ty 1.

On the falling edge of the next clock pulse of the generator 14, the code of the start of the initial microcommand of the next microprogram will be recorded in the register 5. At the memory 2 outputs, a microcommand code will be generated. On the falling edge of the next clock pulse of the generator 14, similarly to the previously described one, information will be recorded in the register of register 8, while in its second position a single signal of the end of command will be recorded.

In addition, a single signal from field 6.1 of the end of the command register register b will be allowed to pass through the elements 20 and 21 of the clock pulse generator 14.

On the falling edge of the control signal from the output of the AND 20 element, a code will be written from the output of field 1.3 of the address function of the previous memory command 1 to register 4, as well as the recording of information about detected errors from the output of block 12 and high signals

fields 2.5 and 2.6 of the memory error labels 2 into register 7. On the falling edge of the control signal from the output of the element 21, trigger 10 will be set to the state corresponding to the value of the output signal of the element 24, i.e. to zero state.

The modification of the address function of the current command in the organization of unconditional transition, as well as the natural addressing of commands is not made.

In the microcommand that is the final one in the microprogram, in fields 2.1 and 2.2, the address of the transition to the unused memory location containing error marks such as reject-1 and reject-2 is specified. Therefore, if by a single signal of the end of command command, the address from field 2.1 of memory 2 and the output of com1-1utator 11, rather than the code of the starting address of the next microprogram from field 1.1 of memory 1, will be written into the register of micro-commands, then in fields 2.5 and 2.6 , generated in accordance with this address of the microcommand, error marks of the type defect-1, defect-2 will be recorded. This indicates an incorrect change of firmware (commands). Fact 0 violates the correctness of the formation of firmware codes, i.e. the correct formation of addresses of the initial microinstructions of microprograms is recorded in the first and second bits of the register 7 by the full, control edge of the control signal from the output of the AND 20 element. Simultaneously with the falling edge of the clock pulse of the generator 14 in the first and second bits of the register 8 will be recorded single signals of the error mark of the fault-1 type, and the end of the command, respectively.

At the outputs of the error type as described above, a type code 5 of the error is generated, at the corresponding output of the device an interrupt signal is generated, the device stops working.

When reading the final microcommand, the final microprogram with a single signal of the End of program label from field 6.3 of register 6 will be set to the zero state trigger 9.

By the zero signal from its single output, generator 14 stops the generation of clock pulses.

Thus, the proposed device provides the implementation of micn1

programs written in the memory of 2 micro-commands, in the sequence specified in memory 1 of the commands.

Under the assumption that the device can simultaneously refuse no more than one functional element and the control equipment can absolutely reliably get:

for a known device, the plurality of functional elements suspected of failure may be reduced to a subset of the functional elements of the command level or a subset of the functional elements of the microcommand level; for the proposed device, a plurality of suspected failure of functional elements may be reduced to a group of functional elements of a command or microcommand level. For example, the error type code 11101 can be used to conclude that the microcommand memory block has failed.

Thus, the technical advantages of the proposed device as compared with the known one are in higher reliability of operation, which is provided by the introduction of additional built-in control means.

Claims (1)

Invention Formula - A microprogrammed control unit with a control containing a command counter, the output of which is connected via the command memory to the inputs of the address switch, a comparison unit and a buffer register, the output of which is connected through the serially connected comparison unit and the first control register to the input of the first element through the serially connected address register and the memory of micro-commands connected to the inputs of the switch ad7077212 ca, the switch of logical conditions, the register of microinstructions and the first register of control, a pulse generator, the first output of which is connected 5 with the inputs of the register of microinstructions and through the first AND element with the input of the buffer register, the second output of the pulse generator is connected to the input of the address register, the second element OR, 10 is distinguished by the fact that: in order to increase the reliability of the device, the comparison circuit, two triggers, the second control register, two OR elements, 15 the cell of the AND element, the first output of the pulse generator is connected to the inputs of the second, third and fourth elements of AND and the second control register, the memory outputs of micro 20 commands are connected to the inputs of the switch of logical conditions, the second and third elements of OR, third, fourth and fifth And elements and the first and second control registers, the outputs of the micro-register register are connected to the inputs of the fourth OR element and the address switch, the first AND element, the third OR element and the second control register, the output of which is through the first and the fourth OR elements connected in series and the first trigger is connected to the input of the pulse generator, the output of the logic conditions switch is connected , with the inputs of the address switch and the fifth element AND, the outputs of the second and third elements OR, respectively, the fifth and second elements AND are connected to the inputs of the second trigger Q pa, whose outputs and command memories are connected to the input of the comparator through the comparison circuit, outputs the third and fourth elements And are connected to the inputs of the command counter, j the output of the first element And is connected to the input of the first register control.