SU1304023A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing technology and can be used in microprogram automata and controllers, in particular, in interface devices of computer complexes. The aim of the invention is to reduce the amount of equipment of the device by reducing the amount of used memory of micro-instructions. For this purpose, a device containing block 1 of the microinstructions memory, counter 2, two delay elements 5, 9, element 3 and group 7 ,,, 7 decoders, mode control trigger 12, modulo 13 adder, error trigger are entered 14 and the group of elements I. 1 Il. and S CO 4 About to O5

Description

one

The invention relates to computing technology. And it can be used in microprogram machines and controllers, in particular in interface devices of computer complexes.

The aim of the invention is to reduce the amount of equipment by reducing the amount of used memory of micro-instructions.

The drawing shows a functional diagram of the device.

The firmware control unit contains a block of 1 microinstructor memory, a counter 2, an element 3, and has a synchronization input 4, a first delay element 5, a reset input 6, decoders (, an instruction code input 8, a second delay element 9, a group of 10 operational outputs, group 11J-11 elements And, the trigger 12 of the control mode, the adder 13 modulo two, the trigger 14 error, the output 15 of the signal

. mistakes.

The device works as follows.

The initial state of the counter 2 (zero), the mode control trigger 12 (single), and the error trigger 14 (single) is set when a reset pulse is applied to the input 6 of the device. The information from input 8, which characterizes the device 1 operation mode, goes through a group of 11-11 elements And to the third address input of memory 1, while the second input of block 1 receives information from input 8, which characterizes the transition conditions, and to the third input it enters information about the state of the counter 2. Information about the state of the counter 2 arrives at the information inputs of the decoders 7, -7. In the 1304023

fO

0

the output of the block 1 of the memory of the signal of the passage of the sync pulse and the single state of the trigger 14 the sync pulse from the input 4 of the device enters the output of the element I 3. This sync pulse gates the selected decoder I-, acting through element 9 on the counting input of the counter 2, translates the latter into the next condition. The binary number, (corresponding to this state, is fed to the first address input of block 1, while the state of the latter, depending on the algorithm of the device operation, may remain the same or may change.

In the first case, the counting pulse, delayed by element 5 and arriving at the input of the record of counter 2, writes the previous value of the binary number into it, after which the next microinstruction is formed. In the second case, in the same way, a new binary number is recorded in counter 2. Thus, an unconditional transition to a new micro-tact is performed and the corresponding micro-command is formed.

If there is a signal to prohibit the passage of a clock pulse coming from the output of block 1, the clock pulses do not pass to the counting input of counter 2 and this clock cycle is kept as needed for a long time. When the transition condition code arrives at input 8, the value of the number at output of block 1 changes. This new value of the number is recorded in counter 2 and a new micro-command is formed at the output of the selected decoder 7. Thus, a conditional transition is made to the required microstate, in which Depending on the algorithm of operation, the expectation of a new condition is possible, and then in block 1 it should be sewn 30

35

40

Depending on the mode of operation, the device O, which prohibits dip, selects one or another decoder 7, while at one of the outputs of the decoder, for example, the first output i forms a K-bit of a single-word format command corresponding to the first micro-tact.

In the first microtack (as well as in the subsequent ones), depending on the algorithm of the device operation, the first INPUT of the element I 3 receives information about the prohibition or resolution of the passage of the clock pulse recorded in memory block 1. In the presence of

the clock pulses are sent to the counting input of the counter 2, but if in block 1 the logic 1 is sewn, then the passage of the clock pulses is allowed. With

CQs, when the firmware of the device operates in different modes of common parts (subroutines), are recorded in the allocated memory area once, and are not duplicated during the recording of each

its microprograms.

In the first mikrotaks. (as well as in the subsequent ones), depending on the algorithm of the device functioning, the information input of the trigger 12 enters

1304023

0

the output of the block 1 of the memory of the signal of the passage of the sync pulse and the single state of the trigger 14 the sync pulse from the input 4 of the device enters the output of the element I 3. This sync pulse gates the selected decoder I-, acting through element 9 on the counting input of the counter 2, translates the latter into the next condition. The binary number, (corresponding to this state, is fed to the first address input of block 1, while the state of the latter, depending on the algorithm of the device operation, may remain the same or may change.

In the first case, the counting pulse, delayed by element 5 and arriving at the input of the record of counter 2, writes the previous value of the binary number into it, after which the next microinstruction is formed. In the second case, in the same way, a new binary number is recorded in counter 2. Thus, an unconditional transition to a new micro-tact is performed and the corresponding micro-command is formed.

If there is a signal to prohibit the passage of a clock pulse coming from the output of block 1, the clock pulses do not pass to the counting input of counter 2 and this clock cycle is kept as needed for a long time. When the transition condition code arrives at input 8, the value of the number at output of block 1 changes. This new value of the number is recorded in counter 2 and a new micro-command is formed at the output of the selected decoder 7. Thus, a conditional transition is made to the required microstate in which Depending on the algorithm of operation, the expectation of a new condition is possible, and then in block 1 it should be sewn up

five

0

O, which prohibits the passage of sync pulses to the counting input of counter 2, if in block 1 the logic 1 is sewn up, then the passage of sync pulses is allowed. With

whether the firmware of the device operates in different modes of common parts (subroutines) of the latter are recorded in the allocated memory area once, and are not duplicated during the recording of each

microprogrammes.

In the first mikrotaks. (as well as in the subsequent ones), depending on the algorithm of the device functioning, the information input of the trigger 12 enters

the information recorded in block 1, that this micro-tact is related to the general part of the device’s firmware and is individual for this mode of operation. For individual micro-tacts in block 1, logical 1 must be sewn up, and for general micro-tacts logical O must be sewn. Transition from individual sections of microprograms to common (sub-programs) and the reverse transition is carried out using the described conditional and

When writing firmware to block 1, there may be free areas, access to which is a failure in

unconditional conversions.

In the transition to a common site mik-) 5 operation of the device. Readable routines (subroutines) for information from block 1 are fed to the input input of trigger 12, and adder 13 is received, where the group from (n-1)

ABOUT

value of logical and which

in the last microtape indie sewn up

output codes of block 1 are added modulo two with the code on its n

of the microprogram section. P20 out.

the sync pulse arriving from element 5, trigger 12 goes to the zero state, and counter 2 records the new value corresponding to the first microcommand of the subroutine.25 stupid from the output of element 5, recording the zero value of the signal from the output to trigger 14. Single

Thus, with the correct operation of the device, a logic level 1 is formed at the output of the adder 13, which, according to the sync pulse,

trigger 12 goes to the first inputs of the group (And elements, from the outputs of which the zero value of the address goes to the third address input of block 1, i.e. the transition to the split (zero) area of block 1 is made, where

sewn subroutines.

When returning from the subroutine to the informational input of trigger 12, the value of logical 1 arrives, which is wired in the last microtogram of the subroutine. On the sync pulse from element 5, the trigger 12 goes into one state and the counter 2 records the value corresponding to the first microcommand of the individual microprogram section following the common area. Single value of output signal

trigger 12 opens group 11 -il

1 elements And through which information

from input 8 goes to the third address input of block 1. Thus, when returning from the subroutine, one goes to the cells of block 1 with the same code value on the first address with the input, i.e. all individual microprogram sections following the common section must begin with this cell. Then, using conditional or unconditional jump operations, you can switch to

individual or common areas of the device firmware.

To determine the failures in the operation of the device, there is a control circuit consisting of an OF element, an adder 13 and a trigger 14. Each microinstruction that is embedded in block 1 is supplied with a control bit, which is an addition to the oddness of the modulo two sum (n-1 ) microcommand bits.

When writing firmware to block 1, there may be free areas, access to which is a failure in

output codes of block 1 are added modulo two with the code on its n

stupid from the output of element 5, is written to the trigger 14. The single

Thus, with the correct operation of the device, a logic level 1 is formed at the output of the adder 13, which, according to the sync pulse,

0

five

0

.

d.

The trigger 14 allows the passage of clock pulses from input 4 of the device. With the appearance of a fault in the ra-. At the output of the adder 13, a logic level O is formed at the output of the device. When the next clock pulse is applied, it will be written to the trigger 14. The zero state of the trigger 14 will prohibit the passage of clock pulses from the input 4 of the device and the output 15 will show an error signal. The failure state of the device will persist until a reset signal appears from input 6. Thus, by analyzing the state of counter 2 and the value of the operating mode taken from the outputs of group 11.11 of elements AND, it is possible to localize the malfunctioning chip of memory 1.

This control scheme allows you to check not only microcommands read from memory 1, but also cases of accessing the unused area of memory 1 of microcommands, since in the unused area of memory 1, the memory remains wired by O across all output bits.

The operation of the firmware is performed until the counter 2 returns to its initial (zero) state or until a reset signal comes from input 6 and the mode selection signal is removed from input 8 or a failure is detected devices. When a new mode value is received at input 8, another decoder 7 is sampled and the operation of the device continues according to the algorithm established for this mode according to the described principle.

In comparison with the known, the proposed device requires less equipment for its realization.

fO dam group decoders, which is tacted by the fact that, in order to reduce the amount of equipment, it contains a mode control trigger, a modulo two adder, an error trigger. In addition, in the device under consideration, the reliability of the function is increased due to the introduction of element- 5 and group of elements And, the first and

Claims (1)

the second inputs and outputs of which are connected respectively to the output of the trigger control mode, the input of the device command code and the third address — Microprogramming device to the 20 input of the microinstructions memory block, the microinformation input containing the memory block, And 3, adder 13 and trigger 14. The formula of the invention commands, a counter, two delay elements, an element And and a group of decoders, the outputs of which form a group of operational outputs of the device, an information input, a recording input, a counting input, a reset input, the output of the counter are connected by the corresponding operational output of the microcommand memory block, the output of the first element the delay, the output of the second delay element, the output of the device reset and the information inputs of the group decoders; in addition, the output of the counter is connected to the first address input of the microinstructions memory block, the second address input d is connected to an input to the code Editor M, Pandora Order 1312/49 Compiled by G. Vitaliev Tehred M. Khodanich Proofreader N. King Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 4023 the device mandates and the first gates of the decoders of the group, the first and second inputs of the AND element are connected respectively to the output of the 5th synchronization clock of the microinstructions block and the synchronization input of the device, and the output of the And element is connected to the inputs of the first and second delay elements and the second gatefo dam group decoders, which is based on the fact that, in order to reduce the amount of equipment, it contains a mode control trigger, a modulo two adder, an error trigger 5 and and a group of elements I, the first and The reset and trigger reset input of the mode control trigger are connected respectively to the output of the microcommand memory block mode feature, the output of the first delay element and the device reset input, the modulo dya's input and output are connected respectively to all the micro memory block outputs commands and information input of the error trigger, the synchronization input and the reset input of which are connected respectively to the output of the first delay element and the device reset input, and the error trigger output is connected to the third output of the AND element and the device error signal output. Subscription