SU1297063A1 - Device for controlling,checking and diagnostic testing - Google Patents

Abstract

The invention relates to automation and computing and can be used in the development of microprogram devices for controlling, monitoring and diagnosing computers and computing systems, systems for production control and for controlling technological processes. The purpose of the invention is to simplify and enhance the diagnosis of a device by organizing a partial overlap of the implementation of control and diagnostic algorithms. The device contains a micro-command memory unit 1, an address register 2, a micro-operation register 3, a return register 4, an address switch 5, a modifiable address switch 6, a clock signal switch 7, a control signal switch 8, a logic conditions multiplexer 9, a comparison block 10 , failure trigger 11, trigger 12 trigger, generator 13 clock pulses, decoder 14, block of elements AND, third, first, fourth and second 16-19 elements of AND, element OR 20. 4 Il. (L to with -vl O) with

Description

The invention relates to automation and computing technology and can be used in the development of microprogramming devices for controlling, monitoring and diagnosing computers of computing systems, systems for production control and controlling technological processes.

The aim of the invention is to simplify and increase the efficiency of device diagnostics.

FIG. 1 shows a functional diagram of the device; in fig. 2 - belt device operation diagram; in fig. 3 and 4 show the layout of information in the memory blocks of the proposed device and the prototype, respectively.

The device (Fig. 1) contains a micro-command memory block 1, an address register 2, a micro-operation register 3, a return register 4, an address switch 5, an address-changing switch 6, a clock signal switch 7, a control signal switch 8, a multiplexer 9 logical conditions, block 10 comparison, failure trigger 11, trigger 12 trigger, clock generator 13, decoder 14 (failure), block of elements AND, third 16, first 17, fourth 18 and second 19 elements AND, element OR 20, inputs: Opcode 21, Start 22, Logical conditions 23, outputs: m micro-operation 24, failure number 25, outputs of micro-operation memory unit 1: micro-operations 26, marks 27, logic conditions 28, addresses 29, register outputs 3 micro-commands third (command end) 30, second (end of work) 31, group of first outputs (micro-operations ) 32, the first 33 and second 34 outputs of the generator 13 clock pulses.

Block 1 of the memory of micro-instructions is intended for storing micro-commands implemented by the device. It is a static type memory device, the information on the output of which appears after the address has been supplied to its input and remains on the output until the input signal is removed. At the output 26 of the micro-command memory unit 1, micro-operations signals are read out, at the output 27 - a tag signal, at the output 28 - a code of a tested logical condition (or a reference value

five

0

five

0

five

0

five

0

55

output response of the control object), and output 29 reads the address of the next microcommand.

Address address register 2 is designed to receive storage and issue of the next microcommand address when the control microprogram (MPU) branch and execute the diagnostic microprogram (MTD) by the device and generate addresses of the next microcommand linear sections of the MPU by increasing the previous address by one. The address entered at the D-inputs of register 2 is recorded on the trailing edge of the first clock pulse, which arrives at its synchronization input via the clock switch 7 from the output 33 of the generator 13 clock pulses. An increase in the content of register 2 per unit is carried out on the trailing edge of the first clock pulse, which arrives at its counting input through an AND 16 element from the output 33 of the generator 13 clock pulses.

Register 3 of the micro-ops is used to receive, store and output micro-ops signals. The operation of the microcommand is written to register 3 from the group of outputs 26 of the microoperation of memory block G on the falling edge of the second clock pulse, which arrives at its synchronization input from the output 34 of the generator 13 clock pulses. The micro-operation signals are read from output 32 of register 3. From output 30 (one bit), a command end signal is received, which takes a single value at the end of the implemented control and diagnostics microprogram (MPU and MTD) in case of failure to detect or the detection of an automatically recoverable failure. From output 31 (one bit), the end of work signal is read, it takes a single value when the device finishes its work and at the end of the diagnostic firmware (MTD) in case of detection of an unrecoverable failure.

The return register 4 is intended for receiving, storing and retrieving the address of the micro-command that caused the failure of the control object. The return address is written to register 4 on the trailing edge of the sync pulse from the output 33 of the generator 13 clocks, which

provided that a zero signal is present at the output of the SHSh 20 element (i.e., the microcommand being executed is not a branch microcommand and the control object has not yet failed), go through element 19 to its synchronization input.

The address switch 5 is designed to switch to the input of the register 2 addresses of the next microcommand. It transfers to the input of register 2 one of the three addresses that arrive at its information inputs: the initial address of the microprogram, which enters input 21 of the device, the current address of the next control micro-command during a branch of the microprogram control (MPU) or the next diagnostic micro-command (MTD), which arrives from the group of outputs 29 of the address of memory block 1, and the return address received from the output of register 4 of return. The control of the switch 5 is carried out by signals coming from the output 30 of the end of the micro-register command 3 and the output of the element OR 20.

Switch 6 of the modifiable address bit is designed to modify the lower bit of the address of the next microcommand when executing the diagnostics firmware (trigger 11 for a single state failure). The modification is carried out by the output of the comparator unit 10. If the output value of the comparison unit 10 is one, then the value of the address bit being modified is transmitted to the output of the switch 6 unchanged, if the output value of the comparison unit 10 is zero, then the least significant bit of the address is forced to zero. When the control firmware is executed (the failure trigger l in the zero state), the output of the logical conditions multiplexer 9 is transmitted to the output of the switch 6.

The switch 7 of the synchronizing signal is designed to control the recording in the register 2 of the address of the next microcommand. The first clock pulse from the output 33 of the generator 13 clock pulses passes to its output when it is necessary to record the starting address of the next microprogram in register 2 addresses - the operation code (a single signal at the output 30 of the command end

to

15

20

25

and d g970634

register micro-operations 3) and when the device executes a control firmware micro-command or diagnostic firmware (single signal at the output of the OR 20 element).

The switchboard 8 of the control signal is designed to control the decoder 14 (failure), output micro-operations signals to the output 24 of the device and control resetting the failure trigger 11. A single signal at its output, enabling the decoder 14 (failure) to work, passing pulses from the output 33 of the generator 13 through an AND 18 element and prohibiting the output of signals to the output 24 of the device’s microoperations, only appears when at one of the outputs 30 end of the command ( in the case of a recoverable failure or if it is not detected) or 31 end of operation (in the case of an unrecoverable failure) of register 3 of micro-operations, there is a single signal, a failure trigger 11 in a single state and a single signal (unit The output signal 27 of the label of the memory 1 in the last microcommand of the diagnostic firmware cannot be detected. Therefore, a single signal at the output of the OR element 20 is determined only by the single state of the failure trigger F, i.e., when the device has completed testing the diagnostic firmware) .

The multiplexer 9 logical conditions is intended to modify the low-order bit of the address of the next microcommand of the control firmware. For this purpose, the logical conditions signals from the input 23 of the device are supplied to its information input, and the code of the checked logical conditions from the output 28 of memory block 1 is fed to the control input. The output of multiplexer 9 is determined by the function

thirty

35

40

50

, Y, + X, Y, + ...,

five

where is x

: Y. Y y

J 1 7

, X - values of logical conditions;

, Y - codes of checked logical conditions

if Y, l;

Y Y X {

four

if 0.

Y is the i-ro value of the logical conditions code.

If the next microinstruction is a microinstruction of the program and the values of the bits of the code of logical conditions are such that Y 1 (j-0, jti), then, i.e. at the output of the multiplexer 9 logical conditions, the value of the logical condition is obtained, which is used as a low-order bit of the address of the following microcommand.

If the next micro-command is not a branch micro-command, then the output signal of the multiplexer 9 is not used in the operation of the device, since the address of the next micro-command is generated by the address 2 register by increasing the previous address by one,

Comparison unit 10 is intended

The decoder 14 (a failure serves to decode the code of the failure arriving at its information input from the output 32 of micro-operation register 3. The signal at the output of the decoder 14 (comparing the code arriving from

input 23 of the device, with a reference code of 20 kaz) is obtained only in the case of a different result coming from the output at its control input of a unit 28 of the logical conditions of the block of the return signal coming from the 1 memory. The signal at the output of the stroke unit 10 of the switch 8 of the control signal comparison is generated in accordance with the logic function

Z (XY, + Xy,) (), ..., {X ,, where X is the value of the i-ro bit and compare 25

Nala, i.e. at the end of the diagnostic firmware.

The block of elements And controls the transfer of the code of micro-operations from the output of 32 micro-operations of register 3 of the micro-operations to the output 24 of the device. If a single signal appears at the output of the switch 8 of the control signal, which corresponds to the end of the diagnostics firmware, then it goes to the second (inniated code;

Y is the i-ro value of the reference code.

If the codes received at comparison unit 10 do not differ from each other, a single signal will be generated, if the codes differ from each other, then at the output of comparison unit 10, 35) the input elements And 15 -15 will form a zero signal. and prohibits the receipt of a failure code, the failure trigger 14 is intended for

recorded in the field of microcommand operations, the last microcommand on output 24 of the device. Element AND 16 serves to control the formation of the address of the next microcommand on the linear sections of the control firmware. The first clock pulse from the output 33 of the generator 13 clock pulses pass through it to the counting input of the register 2 addresses only when the outputs 30 at the end of the register command 3 microoperations and the OR element 20 present zero signals, i.e. the micro-command executed by the device is not a branch micro-command or micro-command of the diagnostics microprogram or the initial micro-command of the control micro-program.

remembering the signal of failure. It is transferred to the single state by a single signal (its leading edge), received at its S input from the output of the AND 17 element. Zeroing of the failure trigger 11 has occurred. walks on the falling edge of the first such pulse, which came through the element 18 18 (under the condition of a single signal at the output of the switch 8 of the forward signal) simultaneously at the K input and C input of the trigger 11.

Trigger trigger 12 is designed to control the 13 clock pulse generator. It is turned on by the Start signal, which is fed to the device input 22, and off, by the End of operation signal from the output 30 of the register 3 micro-operations.

The generator 13 clock pulses is designed to synchronize the operation of the device. At its outputs 33 and 34, the first and second clock pulses are formed, respectively, which are phase-shifted relative to each other, the pulses are generated only when a single signal arrives at the input of the generator 13. The duration of the first clock pulse generated at the output 33 of the generator 13 must be longer circuit switching times from an AND 17 connected in series, a failure trigger 1I, an OR 20 element, and an address switch 5.

Decoder 14 (failures is used to decipher the failure code arriving at its information input from output 32 of micro-operation register 3. The signal at output of decoder 14 (failures) is detected only if a single signal arriving at its control input the switch output 8 of the control signal

KAZOV) only in the case of the appearance at its control input of a single signal coming from the output of the switch 8 of the control signal

Nala, i.e. at the end of the firmware

we are diagnosing.

The block of elements And controls the transfer of the code of micro-operations from the output of 32 micro-operations of register 3 of the micro-operations to the output 24 of the device. If a single signal appears at the output of the switch 8 of the control signal, which corresponds to the end of the diagnostics firmware, it goes to the second (inverse) input of the AND 15-15 elements and prohibits the receipt of a failure code,

recorded in the field of microcommand operations, the last microcommand on the output of 24 devices. Element AND 16 is slaughtered to control the formation of the address of the next microcommand on the linear sections of the control microprogram. The first clock pulse from the output 33 of the generator 13 clock pulses pass through it to the counting input of the register 2 addresses only when the outputs 30 at the end of the register command 3 microoperations and the OR element 20 present zero signals, i.e. the micro-command executed by the device is not a branch micro-command or micro-command of the diagnostics microprogram or the initial micro-command of the control micro-program.

Element AND 17 serves to set the failure trigger 11 to a single state. For this purpose, its inputs are supplied with a signal from the output of the comparator unit 10, a signal from the output 27 of the label, block 1 of the memory and clock pulses from the output 33 of the generator 13 clock pulses. If the first two signals take zero values, the next clock pulse from the output 33 of the generator 13 will pass to the output of the element 17 and the failure trigger 11 will go to one state.

Element I8 serves to control zeroing of failure trigger 11. For this, a signal from the output of the switch 8 of the control signal and a clock pulse from the output 33 of the generator 13 clock pulses are supplied to its inputs. If the signal at the output of switch 8 takes a single value (what happens at the end of the microfusion signal) The end of work at the output 31 of register 3 of the micro-operations is performed only at the end of the device operation or if an automatically unrecoverable failure of the control object is detected in the last micro-command of the diagnostic command.

If the read micro-command is not a branch micro-command, then the value of the mark at output 27 of microcommand memory 1 will be zero, and at the output 28 of the logic signals there will be signals of the reference value of the output response - control object for this microcommand. The reference value of the output reaction is compared with its actual value, which is fed to the input 23 of the device of block 10 compared to 10

15

diagnostics programs), then queues. If during the execution of a micron clock pulse from the output 33 of the generator 13 clock pulses go through the element 18 and the K input and the C input of the failure trigger I1 and on the trailing edge of this pulse, the trigger 11 clears.

Element AND 19 serves to control the writing of information to the return register 4. The return register 4 records the addresses of the micro-commands of the linear sections of the control microprogram, during which the output reactions of the control object coincided with their reference values, i.e. During the execution of these microinstructions, the control object did not fail. If the execution of the microcommand failed at the control object, then the second (inverse) input of the AND 19 element will receive a single signal from the output of the OR 20 element and prevent the passage of clock pulses from the output 33 of the generator 13 clock pulses to the second input of the And 19 element, On sync register 4 return. Thus, in the reset register 4, for the duration of the diagnostics firmware execution, the address of the last microcommand of the control microprogram will be stored, the validation check of which yielded a positive result (the output response of the control object coincided with the reference value).

The OR 20 element performs a disjunction operation on signals coming from the output 27 of the labels of the memory block 1 and from the direct output of the failure trigger 1 1.

970638

Single signal The end of the work at the output 31 of the register 3 micro-operations on the Vits only at the end of the device operation or in the case of detection of an automatically unrecoverable failure of the control object in the last diagnostics micro-command.

If the read micro-command is not a branch micro-command, then the value of the mark at output 27 of microcommand memory 1 will be zero, and at the output 28 of the logic signals there will be signals of the reference value of the output response - control object for this microcommand. The reference value of the output reaction is compared with its actual value, which is fed to the input 23 of the device of block 10 compared to 10

15

the command on the control object did not fail, then its output response coincides with the reference value and the output of the comparison unit 10 yields a single signal, the element output will remain zero, the failure trigger 1I will remain in the zero state and the output element OR 20 will be zero signal. As a result, the next clock pulse from the output 33 of the generator 13 will not pass through the switch 7 of the synchronizing signal, but will go through the AND 16 element to the counting input of the 2 address register, and also through the open AND I9 element will go to the synchronization input of the return register 4. On its trailing edge, the address register 2 will generate the address of the next microcommand by increasing the previous address by one, the address of the previous microcommand from register 2 will be rewritten in the return register 4, and then the whole cycle of the device operation will be repeated.

If the read micro-command is a branch micro-command, then the value of the label at output 27 of memory block 1 will be one, at output 28 there will be a code of the checked logical condition, and at output 29 - the address of the conditional transition.

In accordance with the logical condition code at the output of the multiplexer 9, the value of the checked logical condition that passes at the output of the switch 6 of the modified address bit (because

The rep il of the failure in the zero state is the least significant bit of the next micro instruction. Thus, the address of the next microcommand will be modified by the value of the checked logical condition.

Since the value of the label at output 27 of memory 1 is equal to one, AND 17 is closed and the failure trigger 11 cannot be transferred to one, the output of the OR 20 element is a single signal, according to which through the switch 5 the addresses on the information input of the register 2 address will receive the modified address of the next micro-command, which will be written into it on the falling edge of the next clock pulse from the output 33 of the generator 13 received at its synchronization input through the switch 7. Elements 16 and 19 will be closed you signal output from the OR gate 20, so the counter input register 2 and the address register 4 WMOs synchronization return clock is not received. Further operation of the device will be determined by whether the microcommand that is read is a branch microcommand or not.

In the event of a failure of the control object when the next microcommand of the linear portion of the control firmware is executed, i.e. microcommand is not a microcommand branch, the output response of the control object does not coincide with its reference value and the output of the comparator unit 10 shows a zero signal. At the output 27 of the memory unit 1 tag, there is also a zero signal and therefore the next clock pulse from the output 33 of the generator 13 will pass through the element 17 to the S input of the failure trigger 11 and at its next front the trigger 11 will go to one state. At the output of the element OR 20, a single signal is shown. As a result, through the address switch 5, the diagnostics firmware address will be sent to the information input of the address register 2 from the output 29 of memory 1, which will be written to register 2 on the falling edge of the same clock pulse from the output 33 of the generator 13 received through the output decoder of the decoder 14; on Wits single signal corresponding to the code post

0

five

who drank at his entrance from the output 32 of the register of 3 micro-operations and uniquely indicating the failed block of the controlled object. At the same time a single signal at the output of the switch 8 will close the block of elements And 15 -15 and

about/ -

the zero code will be present at the output of the / 4 device, and will open element 18 on the falling edge of the next clock pulse.

The device works as follows.

In the initial state, all the memory elements of the device (Fig. 1) are in the zero state, with the exception of the register register 3 micro-operations, corresponding to the output 30 of the end of the register register (the circuit of the initial state of the device is not shown), the latter allows transmission through the switch 5 addresses the operation code from the input 21 of the device and its entry in the register 2 addresses.

According to the Start signal from the device input 22, the trigger 12 is set to one state and turns on r; generator 13. On the falling edge of the first clock pulse from the output 33 of the generator 13 clock pulses fed through the switch 7 of the synchronizing signal to the synchronous input address register 2, register 2 from the device input 21, through the address switch 5, the code of the microprogram being implemented, which determines the address of its first microcommand, is written. The address recorded in register 2 is fed to the input of block 1.pam ti microcommands. As a result, microcooperation signals are output at its output 26 in terms of hardware; at output 27, the value of the label at output 28 of the logical condition being checked, at output

29- address of the following microcommand.

On the falling edge of the second clock pulse from the output 34 of the generator 13, the micro-operation part of the micro-command is recorded in register 3 of the micro-operations. As a result, at his exit

At the end of the operation, a single signal will disappear, and at output 32 of the TC of micro-operations signals, which are outputted at the output 24 of the device block 15 -15 to the device output 24, the output 33 of the generator 13 to the address register 2 via the switch 5 will write the address stored in register 4 return, i.e. the address of the last correctly executed microinstruction, and the trigger 11 fails

0

five

0

for reset. Thus, the device will resume execution of the control firmware.

If, however, when the diagnostic firmware was executed, the reasons for the failure were not detected, the recovery firmware does not execute the device, and in the last microcommand of the diagnostic microprogram, the outputs of the micro-operations register 3 do not contain signals similar to the previous case, only the output code 32 the cause of the failure, the output of the decoder 14 (failure) will not (corresponds to no failure, ie, the failure signal was formulated as a result of failure). Further, the device functions as in the previous case.

If a fault was detected, the automatic elimination of which is not possible. it is possible, then the firmware is not executed, and in the last microcommand of the diagnostics firmware at the output 31 of the work end, a single signal is made, and at the output 32 of the register 3 of the micro-operations, the failure reason code is displayed. As a result, the output of the switch 8 of the control signal is at Vit 1 and the output of the decoder 1 of failures according to the indication, and a single signal from the output 31 of the end of the micro-operation register 3 turns off the start trigger 12, a zero signal from the output of which enters the generator 13 and clock generation is stopped — device operation ends.

Claims (1)

Invention Formula A dp control, monitoring and diagnostics device containing a microinstructions memory block, microoperation register, address register, return register, clock switch, control switch, logic conditions multiplexer, comparison block, trigger trigger, failure trigger, clock generator , a decoder, a block of AND elements, four AND elements, an OR element, and an address switch connected by the first and second group of information inputs to the device operation code and to the outputs of the register, respectively return country and exit 5 o 15 20 35 25 40 45 50 55 to the information input of the address register connected by the outputs to the group of information inputs of the return register and to the group of inputs of the memory block connected by the label output to the first input of the first element AND, the group of outputs of logical conditions to the group of the first inputs of the comparison unit and to the group of control inputs of the multiplexer logical conditions associated with a group of information inputs with an input Logical conditions of the device and with a group of second inputs of the comparison unit, connected by the output to the first switching input a mouth of a modified bit of the address connected by the first information input to the output of the modified bit of the address outputs of a memory unit connected by the input of the modified bit to the output of the switch of the modified address bit, a group of address outputs to the group of third information inputs of the address switch, and a group of micro-operations outputs - to the group of information inputs of the register of microinstructions associated with the group of first outputs with the group of first inputs of the block of elements I and with the group of information inputs into the decoder, and the synchronization input - with the first output of the clock pulse generator connected to the forward output of the start trigger connected by the S input to the Start input of the device, and the R input to the second output of the micro-command register connected to the third output of the first information input the control signal switch and to the first control input of the switch of the clock signal associated with the information inputs with the second output of the clock generator and the first input of the second element And the synchronous input the return register is connected to the output of the second element AND, the S input of the failure trigger is connected to the output of the first element AND, and the outputs of the decoder and the block of elements AND respectively to the outputs of the Failure number and the Micro-operation of the device, characterized in that, p. the purpose of simplifying and increasing the diagnostics efficiency of the device, the first control inputs of the address switch are connected to the third output register of microinstructions and to the first input of the third element: And, connected by the output with the counting input of the address register, the second input - with the second control input of the Sikh switch, with the second input of the second element And, with the second control input of the address switch, with the output the W and the control inputs of the control signal switch connected by the second information input to the second output of the microinstructions register, and the output to the control input of the decoder, to the second input of the AND block fourth entrance Execution of microcommands Branching And connected with the output to the C and K inputs of the failure trigger and the second input to the first input of the second And element and to the second input of the first And element connected by the third input to the first control input of the switch of the modified address bit connected by the second the control inputs with the direct output of the failure trigger and the first input of the SHS element connected by the second input to the first input of the first AND element, the output of the switch of the clock signal is associated with the synchronous input of the address register. Horses J aaom6i Transition CNPD End MTD t t Fy Compiled by N. Gorbunova Editor T. Parfenova Tehred L. Serdyukova Proofreader T. Kolb . "." -.- "" ---- ----- - .- Order 783/53 Circulation 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 t /, {/ / Tag Fig.Z t „y ioqzUnp ncn Tag