SU1242946A1 - Microprogram device for test diagnostic checking and control - Google Patents

Abstract

This invention relates to automatics and computing. and can be used in control devices and in the diagnosis of discrete objects. The aim of the invention is to increase the reliability of the device by reducing the equipment of the memory blocks. Device. contains a microinstructions memory block, microinstructions address counter, microoperation register, conditional and transition addresses block, co-switching unit, pulse distributor, multiplexer, switchboard switch, logical conditions register, decoder, trigger start, clock generator, electer block - And mects, three elements And, two elements OR, and a generator of units, 5 Il. about to Y to).-.- jijsa (S-ci 1che ff .-

Description

one

The invention relates to the information technology and computing technology i can be used in control and diagnostics devices of the sample -1X O7LM TOV.

Melieu izobrstenn Yalisletts. increasing the reliability of the device by reducing the memory block hardware. I

Figure 1 shows the functional diagram of the firmware for test diagnostics and control; Figures 2 and 3 show fragments of implemented private firmware; in Fig. A, a functional diagram of a block of conditions and addresses of a transition and a switching unit for a particular example; Fig. 5 is a block diagram of a device operation algorithm.

The MpiKponporpaMMHoe device for testing diagnostics and control (Fig.P contains block 1 of microinstructions memory with code of I.1 micro-operations code, output 1.2 of address and output 1.3 of labels, counter 2 addresses of microinstructions, register of 3 micro-operations, block 4 of conditions memory and addresses of the transition, block 5 KoViMyramm, distributor 6 pulses, multiplexer 7, commutator 8 addresses, register 9 logical conditions, decoder 10 (10.1-10k - group of output terminals), trigger 11, start, generator 12 clock pulses, first 13 , second 14 and third 15 elements And, block 16 elements And, per 1st and second 18 elements OR, generator 19 units, inputs 20-22, respectively, start, operation code and logic conditions of the device and device output 23. In addition, the outputs 23.1 and 23.2 of the command end and the end of the micro-operation register cooTBeTCTBet Ho, first 24 The second 25 and third 26 generator outputs 12 clock pulses correspond respectively to the first one - p-27.1-27. The outputs of the distributor are 6 pulses, the Hu (X) codes of the tested lagging conditions (that; “logical logic condition), the format F microcommands, read from the memory block of conditions and addresses of ode signal KR - at the output end of the register 3 microoperations signal CK - the outlet concentration micro instruction register 3, pgg - unconditional jump and

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. Memory unit 1 (.NI) of micro-instructions is intended for storage of micro-instructions and has three outputs. Signal output is read from output 1.1: micropsraction

5 and arrive at the corresponding information inputs of pei-ister 3 microoperations. From output 1.2, the address of the special microcommand, in which the analysis of transition conditions is provided, is read. At the address contained in this microcommand, the information input of the switching unit 5 is selected for the information input; the information containing the codes of the conditions checked in this microcommand is selected. From output 1.3, a single label is read when executing unconditional jump micro-commands (but by address). In this case, the contents of floor 1.2 are internationally recognized as an unconditional transition.

- The counter 2 addresses of micro-instructions is intended for receiving, storing and issuing codes of addresses of micro-instructions on the power supply unit 1 of the micro-instructions. With ort lnization

 unconditional transfer in microprograms to write the address code of the next microinstruction into the counter 2 addresses of microcommands produced from the output of the switch 8 address when the SRI arrives at its first control input of the label from the output of the PSU 1. When performing microcommands that do not analyze the transition conditions, the contents of the counter 2 addresses microinstructions

35 is incremented by one and the next microcommand is selected and read from the memory block.

Register 3 microoperations prednaz-. Started to receive, store, and issue micro-operation codes at device output 23. The recording of information in a micro-op 3 micro-operation is carried out in the presence of a synchronous input signal j generated at the second output 25

40

45 reiicparopa

gpTo pulses

Unit 4 of the memory of conditions and transition addresses is intended for storing and retrieving codes of the checked logical conditions and high order bits of the transition address. Switching unit 5

designed for issuing codes of checked logrg conditions.

The pulse distributor 6 is a serial connection of a counter and a decoder. The synchronizing and installation of the distributor of sh-puls are counted 1 g. - 1 m and the installation inputs of the cooler cooTncTCTHtmno. The outcome of the condition of a single potential is present in the input 27.1. Distributor 6 ifMny.TbcoB is intended for djopMHponaHifH sequences of pulses, the number of which depends and is determined by the number of levels of the test of the logical conditions. IIjiH receipt of the first successive pulse unit value is present. on route 27.2 and so on until exit 27. and, where and are the number of levels in the logical conditions being checked. Single sp1-cash on one of and. outputs - indicates the number of the level to be tested.

Multiplexer 7 is designed to verify the values of logical conditions. , 1Step up 1 with the input of 22 logical conditions of the device.

The address switch 8 transmits to. the information input of the counter of 2 micro-commands addresses or the operation code received from the input 21 of the device, or the transition address to the next micro-command on the third I) form. At the single input or zero signal value. The end of the command at the output 23.1 of the register of 3 micro-operations, respectively, and also transfer of the address of unconditional jump with the enable signal of the tag from output 1.3 BP.1.

Logical condition register 9 is designed to sequentially record, store, and issue the lower-order codes of the transition address. Recording and formations in register 9 are performed on the falling edge of the clock from the output of the Third Element And 15. The register is equal to .g

The decoder 10 is logical: -: the conditions are intended for issuing in the cogmutation unit 5 the number of the checked logical condition in the test case. The number of outputs of the decoder is equal to. Trigger trigger 11 controls the generator of 12 clock pulses. It is set to one unit when a single signal arrives at the input 20 of the device, which is connected by its h input. A single signal at the output of the trigger 1I start-up allows the generator to operate 12 clock pulses.

A29464

The 12-clock pulse generator is designed for formropl (P1 after the pulse, for the first pulses. At outputs 2A and 25, nocjie5 is added to the output, shifted one relative to the other, the time of writing to the counter 2 addresses of the regular command NOiKpOKOf.saiwLi, and the sample and the sampling pattern and the sampling pattern and the sampling pattern and the sampling pattern and the sampling pattern and the sampling pattern are used. . On exit 26

10, a sequence of pulses is generated controlling the logical conditions.

The first element I I3 is designed to control P1 by writing the address of the very rare microcommand to counter 2 addresses at command1 {the front of a clock pulse from the first output 24 of the generator 12 clock pulses. The second element, And 14, is designed to control the operation of counter 2 (by changing the unit of the address of the next microcombus when executing the linear microprogram section). The third element And 15 is designed to control the work

25 pulse distributor.

Block 16 of the unit I is designed to control the operation of block 4 of the memory of conditions and addresses of the transition when reading from the firmware BP1,

 which provides an analysis of the conditions of transitions.

The first element OR 17 is designed to control and operate the third element I 15, the second element ISH-1 18 to control the first 13 and second 14 elements I.

Input 20 is for starting the device, input 21 is the input for the operation code of the device, which is 35

determines the beginning of the firmware to be executed, input 22 is the input to the logic conditions of the device.

Exit 23 is intended for issuing microoperating devices.

Microprocessor device for testing diagnostics and control works as follows.

In the initial state, all the elements of the circuit are in the zero state of the scientific research institute, and in the discharge register 3 of the micro-operations corresponding to the micro-operation. The end of the command (output 23.) is recorded I and on the first output 27.1 of the distributor 6

single signal. Also the single signal is present at the output 10.1 of the decoder 10 (the circuit bringing the circuit to the initial state of the condition

not showing 1P-d). On curtiajiy start, received through the input 20 of the device on -nxo / i, trigger I 1, the last ycTaitanjinBacTc.H in the same condition. At the same time, in the outputs of the heater-12, the following sequence of drivers are excited: r tact 1) x -;

First tacto; 1.; th pulse from the first output 24 of reitnpnropa 12 is fed to the synchronous input of the counter 2 when resolving (I use the Kovnj control, a command from the output of the register 3. At the same time, the operation code, owner of the first micro-command executed by the microprogram, through the switch 8 enters the information input of the counter 2. address.

According to the address recorded in the counter 2 in the power supply unit 1, the corresponding values are selected. The command is a microinstruction and enters its inputs. In the presence of a signal at the register 3 synchronous input, the operation-part of the microcommand from the output I.I enters the information-entry input and records it in the register 3 M1R of the operation. The signals of the micro operations from register 3 arrive at the code 23 of the device.

When forming the address of the next BOSNIOKI & I micro-command, the following modes of operation of the device: implementation. Linear firmware plots, without checking logical conditions; implementation of unconditional jumps in microprograms; implementation and branching with different configurations of checked logical conditions

In the first mode, at the next clock cycle: - at the impulse output from the output 2A of the generator 12, the coder;: l 5oe of the counter 2 is increased by one unit. From the BP1, the following microinstruction is selected, and so r, alee. not yet; - the microcommand of unconditional transition (at address) or microcom a, which provides for the analysis of conditions of transitions, is taken.

When organizing an unconditional transition (second mode) from BP 1, a micro-command is read, in the format of which there is a transition address code and a label that allows passage of the transition address code to the second information input of address switch 8. On the next sync pulse from the output 24 of the generator 12, the address code is recorded in the information input through the information input. From the BP 1, the unconditional transition microinstruction is retrieved. According to the sync pulse from the output 23 5 of the generator 12, the signals of the microoperations arrive at the output of the device.

The third mode. For definiteness and lag, the operation of a firmware is considered

0 devices for testing diagnostics and control when implementing firmware fragments shown in Leagues. 2 and 3. With | un ststsionalnaya circuit 4 memory unit us.-search of the transition and switching unit 5 for this case is presented in figure 4.

For the next th pulse, the pulse from the output of counter 2 is read.

Q address of the next microinstruction. From PDU 1, a micro-op is selected ;, l, the operational part of KOTopoii is fed to the information input of register 3, and the address i iacTb is sent to block 4. By

To this address from block 4 of the memory of conditions and addresses of transition to 11nform; the input 1 of the block Z. commutapia is selected; the information contained in the Lopch

0 conditions. Older bits of the address of the microcommands arrive at the i; xyodes of the higher addresses of the third I} 1form: the personal input of the switch 8 address. According to the clock 1-Mpul1) Su i .j from the output 25 of the generator 12, the signals of micro-operations from the register 3 arrive at the output 23 of the device.

five

The code of the first verification of the south of the logical condition X is fed to the mult-7-7, plexor / as in the code /7.

the distributor 6 and on the 10.1 de decoding code of the coder 10 there is a single signal) and the value of the tested log-h-zsky with gop - l is fed to

information input of the register 9. On the falling edge of the first clock pulse from the output of the third element And 13, the value of the first condition checked is set into the register 9. On

exit 27.. distributor 6 and

output 10.2 (l) of the decoder 10 with a single (zero) value of X is set (saved) a single signal. At the next clock

sh-ful fj in register 9 is entered the code of the second checked logugic condition X. (X °). The signals from the outputs of the decoder 10 are thus

7

indicate which branch is being made.

The junction address, corresponding to the testable logical condition, is determined on the margin.

rvep wh ), Л „,,, where А з (ac1 high-order bits of the address of the next microcommand from the memory block of conditions and transition adresors;

A (RG) - the value of the lower bit to 9

regular microinstructions with

the output of the register of logical conditions; . mr value of the signal at the output of the multiplexer logical conditions (the value of the last verified condition).

For a three-level fragment, microprograms (with a total number of microinstructions equal to 256), the bit A of the transition is 8 bits, including, A - 5, L G) - 2,

  „

If the tree is checked by logical conditions of the NCC and Eritric, then condition codes X 1, i.e. The method is supplemented to conditionally by dcml-1.

When the X code is received, multiplexer 7 receives a single, 1st signal from generator 19 at the input, and the device operates in the same way as described.

According to the last (the third sync impulse, the C signal from output 27 .p. (27.3) goes to the switching unit, multiplexer 7 generates a signal of the last logical condition value. On the sequential i, the distributor 6 and r / li li register - 9 logical conditions The next pulse C from the output 24 of the generator 12 is added to the counter 2 of the address.

Claims (1)

Invention Formula A microprogramming device for test diagnostics and control, containing a microinstructions memory block, microinstructions address counter, microoperations register, conditional and transition addresses block, switching unit, pulse distributor. s 0 15 20 25 thirty . . 35 40 45 55 429468 multiplexer, descrambler, AND block of elements, OR first element, and the output of the micro-operation code of the micro-command memory microcontroller is connected to the information P: 1m input of the micro-operation register, which is connected to the micro-address address counter's counter. c, info (; rmats1 onn, 1m input of the micropock memory block, outputs of conditions codes of the conditions memory block and transfer addresses are connected to information inputs of the comaciation module, the output of which logical conditions code and logical conditions input of the device are connected to equal to the input and with the inputs of the higher bits of the information input of the multiplexer, the OUTPUT group of the pulse distributor is connected to the first group of control inputs of the switching unit, characterized in that it contains an address switch, a register of logical conditions, a trigger trigger, a clock generator pulses, generator 1tor units, the first, second and third And, the second element H. nii, and the device start input is connected to the S-input trigger trigger, the output of which is connected to the input of the clock pulse generator The first output of the clock pulse generator is connected to the first inputs of the first and second elements I, the outputs of the first and second elements AND are connected respectively to the synchronization input and the counting input of the microinstruction address counter, the second output of the clock generator is connected to the synchronization input of the distributor pulses and the register of logical conditions, and the third output is connected to the first input of the third element And, the output of which is connected to the synchronization inputs of the distribution tel pulses and registers the logical conditions, the device opcode input coupled to a first data input switch address, the output of which is connected to the information input of the address counter of microscopic commands, the output of the address of the microcommand memory block is connected to the first group of inputs of the block of elements And and the second information input of the address switch, group of outputs of the block 9 of elements And is connected to the group of informative inputs of the naiMHTH block of the conditional and transitional points and from the group headlab of the first element Ш1Н, the output of the label of the memory block is small. with an inverted input of a block of elements And, the first control input of an address switch and with the first input of a second element 11101, the output of which connects to the second input of the first element And and the inverted input of the second element And, the outputs of the higher bits of the memory address of the memory block and the address the transition is connected to the inputs of the higher bits up to the address of the third information input of the address switch, the output of the multiplexer is connected to the information input of the register of logical conditions and to the input of the bit value 242946 ten The last 1 condition of the third information input of the address switch, the output of the register of the local conditions is connected to the first input of the address switch, the group of outputs of the decoder is connected to the second rpyrinoii of the control inputs. switching unit, code first element lUIli is connected to the second inputs of the second element HJIIi and the third element I, the end of the command of the register register register M is connected to the third-f input of the second element IL11 and with the second control to the gateway input of the address switch, the output of the end of the micro-operations register is connected to the H input of the start trigger. F1 Fig.Z  7} A L Y v