SU1208556A1 - Microprogram device with check - Google Patents

Description

one

The micro-operation register is connected to the first and second error control inputs of the error switch and to the first error switch information input, respectively, the label output of the monitored microinstructions memory controlled condition is connected to the first modulo-two input, the output of which is connected to the second error switch information input , the output of the check mark of the control logic of the microcommand memory block is connected to the inverse input of the second element and the third control input of the switch

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ki, the information output of which and the second output of the clock generator are connected respectively to the informational and synchronous input of the error trigger, the information output of the multiplexer is connected to the second input of the modulo two and the first input of the second element I, o -; OR, the output of the modifiable part of the address of the microcommand memory block is connected to the second input of the second OR element, the output of which is connected to the third information input of the address switch.

The invention relates to the field of automation and computer technology and can be used in computers and computer systems with microprogrammed control.

The aim of the invention is to increase the reliability of the control.

The essence of the invention consists in expanding the field of application of the device and increasing the reliability of control by organizing system testing of a firmware control device — the object of control using information on the distribution of operator shifts (PCR).

The presence of a PCR is one of the sources of natural information redundancy that can be used to control the interaction of a device and a control object.

The essence of the RNO is as follows. If the logical condition does not change its value after the execution of the operator (microcommand) A; then it is not included in the distribution of the shifts of the operator A-, i.e. belongs to the subset B; . If x- enters the RSO A ;, then the following situations are possible: -XJ after issuing A; always set to O, i.e. is included in the RJ subset; ; x; after issuing A; always set to 1, i.e. enters into the subset x: after the step A-, always changes its value to the opposite, i.e.

is included in the subset B, g; Xj after issuing A; can change its value with a probability of 1 p 0.

Knowing about RSO, you can in

During the execution of the firmware, check whether the actual values of the logical conditions are THEIR and the required values. To do this, it is enough to set the logical number

condition and its required value after issuing the appropriate operator. In this case, the control of the correct functioning of the control object, as well as

an indirect check of the firmware device itself, since an incorrect value of the logical condition at the corresponding point of the firmware may be due to

Sequence Violations

microinstructions.

The drawing shows the functional diagram of the device.

The device contains a block of 1 micro-command memory with bits of unmodifiable 1.1 and 1.2 parts of the address being modified, microoperations 1.3, first 1.4 and second 1.5 labels of the controlled logical condition and verification of the control logic condition respectively of the logical conditions code 1.6, address registers 2 and microoperations 3, multiplexer 4, generator 5 clock pulses, trigger 6 triggers and errors 7, switches 8 addresses 9 errors

the first 10 and second 11 elements are And, the first 12 and second 13 elements are OR, the adder 14 is modulo two, inputs 15 of the operation code, 16 logical conditions and 17 start-ups of the device and outputs 18 micro-operations (including the end of operation 18.1 and the end of command 18, 2) and 19 device errors.

The microcommand memory unit 1 is designed to store microcode codes on the trailing edge.

mand and has six outs. The output 1.1 of the address of the next microcommand is connected to the corresponding bits of the second information input of the switch 8. At this output, all the bits of the address are read, with the exception of the low-modifiable bit of the address (field 1.2).

Output 1.6 of the logic condition code is connected to the inputs of multiplexer 4, which, if necessary, analyzes the value of the corresponding logic condition,

In fields 1.4 and 1.5 of block 1, control marks M are written, and 25 are relative to each other clock pulse than M, 1 (o), if the value of the contours that provide the synchronized logical condition must be equal to 1 (o ), M 1 (0), if

Operation of all elements of the device. The formation of a sequence of pulses at the outputs of the generator 5

check is performed

Operation of all elements of the device. The formation of a sequence of pulses at the outputs of the generator 5

(working) logical conditions, CRO. clock pulses are produced only by a combination of M, - Mj o is marked by the initial microcommand of each microprogram.

Output 1.3 micro-operations connected to the information input of the register 3 micro-operations. In addition to the external micro-operations issued at the output 18 of the device, the output of the 1.3 block I reads the internal micro-operations End of command and End of work. Each last microprogram of a microprogram contains a microoperation of the End of a command, and the last microcomomand of the latest microprogram contains, in addition, a microoperation of Co35

40

ko in the presence of a single signal at its control input.

Trigger trigger 6 controls the generator of 5 clock pulses. It is set to one when a single signal is received. to the input 17 start the device. A single signal at the output of the trigger 6 allows the operation of the generator 5 clock pulses. Trigger trigger 6 is set to zero from the station when a micro-operation signal arrives at its R input through an OR 13 element. End of operation, which is formed at output 18.1 of register 3

Nets work. These micro-operations, such as micro-operations, or an error signal, come to the information input which is formed at the output of the error trigger 7.

Trigger Error 7 is intended

micro-register register 3 Block 1 is a static type of storage device whose information on the outputs of which is present during the entire time the address is present; microinstructions at its entrance. The address register 2 is designed to store the address of the next microcommand that is received and its information input from the output of the switch 6, the next address is written to the address register 2 by 50

dp fixing the error in the operation of the device and is set to one in the presence of 1 at the switch output to the falling edge of the pulse from the second output of the generator 5,

55 Switch 8 is designed to transmit to the input of the register 2 the address of the operation code, which enters the input 13 of the device, or the queue address 208556

c on the falling edge of the pulse arriving at the synchronous input of the register 2 address from the first generator output 5 clocks, 5 Micro-register 3 is intended for storing micro-operations signals to its information input from block 1.3. 1. Record micro-operations in the register 3

clock pulse arriving at the synchronous input of register 3 from the second output of the generator 5 clock pulse fc oB.

} 5 - Multiplexer 4 selects the value of the logical condition from the incoming to its information input, the number of which is specified in the code of logical conditions, 2Q stepping on its control input from the output 1.6 of block 1,

The generator 5 clock pulses I forms on the first and second outputs of a sequence of shifted each

relative to the other clock pulses that provide synchronous

Operation of all elements of the device. The formation of a sequence of pulses at the outputs of the generator 5

five

0

ko in the presence of a single signal at its control input.

Trigger trigger 6 controls the generator of 5 clock pulses. It is set to one when a single signal is received. to the input 17 start the device. A single signal at the output of the trigger 6 allows the operation of the generator 5 clock pulses. Trigger trigger 6 is set to zero from the station when a micro-operation signal arrives at its R input through an OR 13 element. End of operation, which is formed at output 18.1 of register 3

microoperations, or an error signal, which is generated at the output of the error trigger 7.

50

dp fixing the error in the operation of the device and is set to one in the presence of 1 at the switch output to the falling edge of the pulse from the second output of the generator 5,

55 Switch 8 is designed to transmit to the input of the register 2 the address of the operation code, which enters the input 13 of the device, or the queue address

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the microcommand coming from address 1.1 of the output of block I and the output of the element ISH1 13 (modified address bit), the operation code is switched to the input of register 2 of the address with a single signal to the control input of switch 8,

The switch 9 error generates a single signal in accordance with the following logical function

00 (M, © xj Mj + K M M + + K, M, H2, (O

where x, the actual value of the counter

leg logical condition; K | - signal the end of the command.

Thus, the error signal is generated when the value of the label M | (the required value of the control logic condition and x if M 1; in the absence of a command end signal in register 3 after accessing a microcommand marked with a combination of M 1, Mg 0; in the absence of a microcommand following the last microcommand of the microprogram with a K 1 signal, combinations of labels M (M 1.

Element And 10 is designed for odds. Mirani conjunction labels M, M.

Element And 11 controls the transmission of the logical condition value to modify the lower address bit on the element OR 13 With Mj 1, the address modification circuit. is blocked. Since in all microcommands of the branching, the address is recorded with a Jamglaim a and O, then

its modification is to replace the value of that logical

conditions, which is verified by the implementation of the branch. Modulo 14 admits the comparison of the values of the signals M. And x ...

1 1h

The proposed device works as follows

In the initial state, all the memory elements are set to zero. In the single state there is only one

„

trigger register J, which corresponds to the output 18.2 microoperations of the end of the command (the installation circuit of the source is conventionally not shown).

The operation of the device begins after a signal arrives at the input 17. A start by which the trigger 6 is set in the single state. On the first clock pulse from the first output

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generator 5 to register 2 is entered into the code from input 15, this code is written to register 2 through switch 8, to the control input of which a single signal is output from output 18.2 of register 3.

. Then, the clock pulse from the second output of the generator 5 to the register 3 is entered into the part of the code of the first micro-command, consisting of the code of micro-coordinates. On the trailing edge of this pulse, a single signal at the output 18.2 of register 3 disappears, and in error trigger 7, a single I.PI zero signal is recorded. A single signal is written to this trigger if expression (1) is turned to one. In this situation, this will happen if a combination different from combination 10 is recorded in the first microcommand in fields x 1 „4 and 1.5, which indicates a distortion of the operation code or a failure (malfunction) of the device’s address circuits,

 the trigger 7 remains in the zero state, the trigger 6 does not change its single state, and the address of the next microcommand is written to register 2 on the second pulse from the output of the generator 5. This address enters register 2 from run 1 of block 1 (unmodifiable part) through switch 8, to the control input of which zero potential is supplied from output 18 and 2 of register 3. If this microcommand is not a branch microcommand, the least modifiable addressable bit passes to the input of the element OR 13 and further to the register 2 of the address without change.

On the second clock pulse from the output of the generator 7, the micro-operations codes are entered into the register 3, and then the device continues to operate as described.

In the branch micro-commands, the code of logical conditions comes from the Iv6 field to multiplexer 4, the output of which passes the value of the condition being checked. This signal through the open element AND 1 arrives at the element OR 13 and modifies the low-order address bit. The algorithm of the working device after reading the last micro-command and moving to the next firmware in bint-le r PC)

 one

similar to the algorithm of the initial phase of operation.

After reading the register of micro-operation of the end of operation with a signal from output 18.1 through the element OR 12, trigger 6 is zeroed and the device stops working until the next start signal is applied,

In the process of device operation due to failures (malfunctions), an erroneous transition to the initial microprogram of the microprogram is possible. In this case, a single signal appears at the output of the AND 10 element. Since the signal at the output 18.1 is equal to zero, the conjunction K reverses, the incoming voltage is 1, and the trigger 7 detects an error.

to

0 if (x ,, (M) 0, x, e6i, (, x, eB ;,)

1, ecli (x.ev; 2lv yк (, e6; ,, (- ll - 0, 6; j.,

where X (t-1) is the logical value

conditions in the previous

about the malfunctioning of the control object, or about the cycle or the subsequent distortion of the firmware, the branching.

If values ,. and not due to his failure.

match up

then it says

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To control the correctness of the interaction of the proposed device with the control object and to increase the reliability of operation in

The 5 linear microinstructions in the field 1.6 are given the code (number) of the control logic conditions. In this case, the field 1.5 records the label M 1, which blocks with

10 of the element 11 is an address modification circuit (in order not to disrupt the normal course of the firmware), and in the 1.6 field the required value of the logical condition Xj is written. which is calculated at the microprogramming stage taking into account the existing distribution of shifts according to the following rule

Compiled by A, Sirotska Editor L, Veselovska Tehred T.TulikKorrektor S.Shekmar

Order 289/58 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5

Branch PPP Patent, Uzhgorod, Proektna St., 4

Claims (1)

A FIRMWARE DEVICE WITH CONTROL, containing a micro-memory memory block, an address register and a micro-operation register, a multiplexer, a clock generator, a start trigger, an error trigger, an address switch and a first OR element, wherein the device start input is connected to a single input of the start trigger, the zero input of which is connected with the output of the first OR gate, the output start trigger is connected to the clock pulse generator trigger input, nep- _t vy and second outputs are connected to inputs of the synchronization register address and register m operation, respectively, the outputs of the address register are connected to the corresponding address inputs of the micro-memory block, the outputs of the micro-operation register are information outputs of the device, respectively, the output of the error trigger is connected to the first input of the first OR element and is the output of the device error, the outputs of the signs are End of operation and End of the instruction of the operation register connected respectively to the second input of the first OR element and the control input of the address switch, the information output of which is connected with the information input of the address register, the inputs of the device operation code are connected to the first group of information inputs of the address switch, the inputs of the logical conditions of the device are connected to the group of information inputs of the multiplexer, the output of the non-modifiable part of the address of the micro memory instruction block is connected to the second information input of the address switch, microoperation outputs the memory block microcommands are connected to the information inputs of the register of microoperations, respectively, the output code of the logical conditions of the memory block microcom ND are connected with the corresponding control inputs of the multiplexer, characterized in that, in order to increase the reliability of control, it additionally contains an error switch, an adder modulo two, two AND elements, a second OR element, and labels of the controlled logical condition and labels of the control of the logical control condition micro memory blocks are connected respectively with the first inverse _t input and the second inverse input of the first AND element, the output of which and the output of the sign End of command LZ of the microoperation register is connected to the first and second control inputs of the error switch and to the first information input of the error switch, respectively, the output of the label of the controlled logical condition of the micro-memory block is connected to the first input ^ of the adder modulo two, the output of which is connected to the second information input of the error switch, the output check marks of the control logical condition of the micro memory command block is connected to the inverse input of the second element and the third control input of the switch errors whose rotational output and the second output of the clock generator are connected respectively to the information and sync input of the error trigger, the information output of the multiplexer is connected to the second input of the adder modulo two and the first input of the second AND element, the output of which is connected to the first input of the second OR element, the output of the address part being modified The micro-command memory block is connected to the second input of the second OR element, the output of which is connected to the third information input of the address switch.