SU1376084A1 - Microprogram control device - Google Patents

Abstract

The invention relates to digital automation and computer technology and can be used for the design of microprogrammed computer controllers and controllers for automated process control systems. The purpose of the invention is to expand the scope of application by providing processing of various types of interrupts. The microprogram control unit contains a memory block of 1 microinstructions, a counter of 2 addresses, a register of 3 microoperations, a counter of 4 return, multiplexers 5 and 6, blocks 7 and 8 of interrupts, encoders 9, 10, blrk 11 decoders, triggers 12, 13., clock generator pulses 14, elements OR 15 and 16 elements AND 17-22 19. 3 Il., 1 tab. with $ (L od “00 Pui.i 26

Description

The invention relates to automation and computing and can be used in computer and microprogrammed computer systems, as well as in process control systems.

The purpose of the invention is to expand the scope by providing processing of various types of interrupts.

FIG. 1 is a functional diagram of the proposed firmware control device; FIG. 2 is a functional block diagram of an interrupt upon permitted (or invalid) request; FIG. 3 - time diagram of the device.

The proposed device (Fig. 1) contains a block of 1 microinstructions memory (ROM) with the fields 1.1 labels of a linear microcommand (MK), 1.2 addresses, 1.3 codes of logical conditions, 1.4 codes of microoperations, 1.5 ends of the interprogram (MP), 1.6 ends of the command , counter 2 addresses, register 3 micro-operations, counter 4 returns ,. multiplexer 5 logical conditions, multiplexer 6 addresses, blocks 7 and 8 interrupts, respectively, by allowed and invalid requests, the first 9 and second 10 encoders, block 11 decoders, trigger 12. errors, trigger 13 start, generator 14 clocks with outputs 14.1 and 14.2 the first element OR 15, the second element OR 16, the first 17, the second 18 and three. 19 And elements, cTisa device start input 20, device operation code input 21 (it is also the second information input of the address multiplexer 6), device interrupt input 22, device logic conditions input 23, output 24 micro-operations of the device operation output 25 , error output 26 — devices controlling 27, first 28 and second 29 informational inputs of interrupt block 7 by permitted request, first 30 and second 31 informational inputs of block 8, five, 32, third 33, fourth 34, first 35 informational and fourth 36, fifth 37, first - the third 38-40 control inputs of the multiplexer 6, the control input 41 of the interrupt unit 8 upon an invalid request, the outputs 42 and 43, respectively, of the interruption unit 7 upon the permitted request and 8 interruption upon an invalid request.

0

0

five

0

five

0

five

0

five

Interrupt block 7 (8) by the allowed (invalid) request (FIG. 2) contains the first (second) block 44 of the elements AND, the third (fourth) element OR 45, the quarter (five) element AND 46.

The time diagram (Fig. 3) uses the notation entered in Figs. 1 and 2.

The functional purpose of the elements and connections of the firmware-control device is as follows (Fig. 1).

Block 1 of the microinstructions memory (ROM) is intended for storing the MCs implemented by the MP device, a static type ROM, information at the output of each appears after the address is given at its input and remains at the output until the input signal is removed. At the output of p. 1 .1 block a 1, a linear microcommand tag signal is read (one only in the case of linear MK). If zero is written in field 1.1 (i.e., branching MC), then the output of the next MC is read at the output of field 1.2 of block 1, and the code of the checked logical condition is stored in field 1.3. If in the cell of block 1 linear MK is written, i.e. In the 1.1 field, the unit is written, then the codes of allowed and invalid interrupt requests are read from the outputs of the fields 1 .2 and 1.3. From the output of the floor 1 .. 4 the code of the next micro-operation is read. From the output of field 1.5 of block 1, the signal of the end of the interrupt MT is read, which is single only in the last MC of the interrupt MC.

From the output of field 1.6, the command end signal is read, single only in the last MC of the working MP. Counter 2 addresses is designed to form and retrieve the address of the next MC. Controls the operation of counter 2, the signal from the output of element a OR 15. With a single value of this signal, counter 2 records the address code from its information input. It is determined by the address of the next MC. At a zero value of the control signal from the output of the element OR 15, the counter 2 increases its content by one (the formation of the address MK following the linear MK). A new address code is generated by a counter 2 on the falling edge of each clock pulse from the output 14.1 of the generator 14 arriving at the synchronous input of the counter 2.

Register 3 of micro-operations is designed to receive, store and output to the block 11 decoders the next micro-operation code from the output of field 1.4 of the code of micro-operations of ROM 1. Register the code of the next micro-operation in register 3 only on the falling edge of the clock pulse from output 14.2 of the generator 14 entering on register sync 3.

The return counter 4 is designed to form, store, and return to the input 32 of multiplexer 6 a return address to the interrupted working MP. On the falling edge of the pulse from the output of the AND 19 element, which arrives at the synchronization input of counter 4, the address of the linear MC read at this time is written to the latter, which is fed to the information input of counter 4 from the output of counter 2. This pulse is formed by the AND 19 element as a result of the conjunction the interrupt signal and the clock pulse coming respectively from the output of the OR 16 element and the output 14.2 of the generator 14. After the address of the readable linear MK (not the last in the working MP) is written to the counter 4, the device performs an MP interrupt. From the floor 1.5 of the last MK of this MP, the signal of the end of the MP of the interrupt is read. The unit signal of the conjunction of this signal and the clock pulse from the output 14.2 of the generator 14, formed by the element 18, enters the counting input of the counter 4 and increases its content by one with the falling edge. Thus, counter 4 forms the MK address following the linear MK, after which the interrupt MT was performed.

The logical conditions multiplexer 5 transmits to its output the values of that logical condition from the input 23 of the device, the code of which is recorded in the field 1.3 of block 1 and arrives at the address input of the multiplexer 5, the multiplexer 5 only works if its control inverse there is no single linear MK tag signal from the output of field 1.1 of block 1.

The address multiplexer 6 is designed to supply the information input of the counter 2 with an address code from one of its information inputs 21, 32, 33, 34, 35 in accordance with the control code on the control inputs.

36, 37, 38, 39, 40. The operation algorithm of the address multiplexer 6 is described by the following expression

,

A ,, v40

AzgUz.Uz7 +

.

ten

15

2Q 25 30

W

50

five

A - Blocks

where a. - the address code at the i-th information input of multiplexer 6;

a single signal at the jth control input of the multiplexer 6;

address code at the output of the multiplexer 6.

7 allowed and 8 invalid requests (Fig. 2) are designed to generate interrupt signals of the working MP, respectively, by permitted or invalid request.

A request signal appears on one of the inputs 22 of the device and then the first input of the corresponding element AND of the AND block 44 enters; The input 29 (31) of block 7 (8) receives the code of allowed (invalid) requests from the corresponding outputs of fields 1.2 and 1.3 of block 1. If the second input of the And element of the block 44 has one, then the corresponding request at the first input of the same element And will be allowed (invalid). In this case, the pulse from the output of the corresponding element J5 AND block 44, passed through the element OR 45, goes to the second input of the element I 46. At its first input, i.e. at the input 27 (41) of block 7 (8) there is a linear MK tag signal from the output of the field 1.1 of block 1. If this signal is single, then the output of the element 46, i.e. at the output 42 (43) of block 7 (8), an interrupt signal appears upon the permitted (non-45 permissible) request.

The encoders 9 and 10 are designed to convert the unitary code of interrupt requests that come to their inputs from the device input 22 into the address code of the first MC of the corresponding MT. The encoder 9, in this case, sends the code of the first MC of an interrupt to the information input 33 of multiplexer 6 of an address according to an allowed request, and the encoder 10 sends the code of the first MC of an interrupt of an invalid request to information of 34 of multiplexer 6.

513

The decoder unit 11 is designed to convert the micro-operation code stored in the field 1.4 of unit 1 and read from the output of micro-operation register 3 to the input of unit 11 into unitary codes (codes of incompatible micro-operations) received from the outputs of the decoder unit 11 to the output 25 of the device’s micro-operations. The output 24 of the micro-operation of the end of the work output of one of the decoders of the block 11, in addition, is connected with the zero input of the trigger trigger 13. Use blo

11 descramblers allow the hardware to be implemented. B tab-

20

thirty

to reduce the field depth of 1.4 block 1 and the register of 3 micro-operations. The number of decoders of block 11 is determined by the number of fields of incompatible micro-operations.

Error trigger 12 is designed to store the error signal that is output to the device output 26 during the execution of an interrupt MF upon an invalid interrupt request. Trigger 12 is set to one state by an interrupt signal upon an unacceptable request received by a single trigger input from the output of block 8. To the zero state, trigger 12 is set by a signal from an output of an element 17, which performs the conjunction of the end of the interrupt signal MP from the field 1.5 output. unit 1 and the time pulse from output 14.1 of generator 14.

A start trigger 13 controls the operation of the clock pulse generator 14. It is set to the one state by the start signal from the input 20 of the device. After the device executes the program, at its output 24 a micro-operation signal appears at the end of the operation, which, arriving at the zero input of the trigger 13, thus prohibits the operation of the generator 14 clock pulses and thereby stops the device.

The generator 14 clock pulses is designed to form at its outputs 14.1 and 14.2 sequences shifted relative to each other 50 by the phase of the clock pulses synchronizing the operation of the device,

The element OR 15 is designed to form the control signal of the counter and their symbols and the differences in the content of the corresponding cells of block 1 are shown.

In the initial state, all the memory elements are in the zero state (the initial circuit for the installation is simply not shown conventionally).

Only field 1.6 of the end of the zero-cell command (with zero address- 25 res) of unit 1 is recorded as one. The signal from the output of this field is present in the initial state at the control input 39 of the multiplexer 6 of the address, which passes to the information input of the counter 2 the code of the first working MP s, the input 21 of the operation code of the device. The same signal from the output of field 1.6 through the OR 15 element is fed to the control input of counter 2, thus allowing the address code from the output of multiplexer 6 to be written to it.

Consider the operation of the device in the first mode.

Upon receipt at the input 24 of the launch device of the pulse (Fig. 3) trigger

13 is set to one and permits the operation of the generator

14-stroke pulses. On the falling edge of the first clock pulse. from the output 14.1 of the generator 14 to the counter 2 is entered from the information input the address of the first MC of the first working MP. Let it be MK of type A. Then the signal from the output of the field 1.1 of the block 1 will prohibit the operation of the multiplexer 5 logical conditions. Information from the outputs of fields 1.2 and 1.3 of block 1 will be fed to inputs 28 and 30, respectively, of blocks 7 allowed and 8 invalid interrupt requests. When working in

40

45

14-stroke pulses. On the falling edge of the first clock pulse. from the output 14.1 of the generator 14 to the counter 2 is entered from the information input the address of the first MC of the first working MP. Let it be MK of type A. Then the signal from the output of the field 1.1 of the block 1 will prohibit the operation of the multiplexer 5 logical conditions. Information from the outputs of fields 1.2 and 1.3 of block 1 will be fed to inputs 28 and 30, respectively, of blocks 7 allowed and 8 invalid interrupt requests. When working in

Chick 2 addresses. The signal is formed on the first 55 mode of the allowed or under output of the element OR 15, if at least acceptable interrupt requests are in

at one of its four inputs, the device is not received and signals

there is no single interrupt signal in units of 7 ff 8 not forming. The OR element 16 generates a control signal for the counter 2 addresses and the return counter 4 when the device switches to the interrupt mode according to the signals of allowed or unacceptable requests 7 received respectively at the first and second inputs of the OR 16 element.

The device (Fig. 1) can operate in the following modes: the implementation of the working MP; implementations of interrupt MP on allowed request; implementations of interrupt MPs by invalid request.

Let's select 4 main types MK, which

0

0 face shows their symbols and the differences in the contents of the corresponding cells of block 1.

In the initial state, all the memory elements are in the zero state (the initial circuit for the sake of simplicity is conventionally not shown).

Only field 1.6 of the end of the zero-cell command (with zero ad- 5res) of block 1 is written down to one. The signal from the output of this field in the initial state is present at the control input 39 of the multiplexer 6 of the address, which passes to the information input of the counter 2 the code of the first working MP s, the input 21 of the operation code of the device. The same signal from the output of field 1.6 through the OR 15 element is fed to the control input of counter 2, thus allowing the entry into it of the address code from the output of multiplexer 6.

Consider the operation of the device in the first mode.

Upon receipt at the input 24 of the launch device of the pulse (Fig. 3) trigger

13 is set to one and permits the operation of the generator

14-stroke pulses. On the falling edge of the first clock pulse. from the output 14.1 of the generator 14 to the counter 2 is entered from the information input the address of the first MC of the first working MP. Let it be MK of type A. Then the signal from the output of the field 1.1 of the block 1 will prohibit the operation of the multiplexer 5 logical conditions. Information from the outputs of fields 1.2 and 1.3 of block 1 will be fed to inputs 28 and 30, respectively, of blocks 7 allowed and 8 invalid interrupt requests. When working in

0

five

5 The first mode is allowed or not available. On the falling edge of the second clock pulse from the output 14.2 of the generator 14 into the register 3, the code of the micro-operation is entered from the output of the field 1.4 ROM 1. Further, this micro-code is decrypted-. It is interleaved by a block of 11 decoders and is fed to the output of 25 micro-operations of the device. On the falling edge of the next clock pulse from the output of 14.1 Q, the crap 6 (i.e., from the output of field 1.2 of the block

generator 14, the counter 2 addresses, on: whose control input there is no single signal from the output of the element OR 15, increases its content by one and thus forms the address of the next cell of block 1. Let the type B MC be recorded in it. Then field 1.2 of block 1 recorded the code of the checked logical condition that goes to the address A input 20 of the multiplexer 5. At the inverse control input of the last signal, the linear MK tag is missing and the multiplexer 5 passes the output sign 1) or increases the content by units nitsu (i.e., the next address is formed as an IC for reading and MC type A). In the last MK of the working MP (MK Ipa C), the signal of the command end from the output of the 1.6 block floor is fed through the OR 15 element to the control input of counter 2, allowing entry from the input 41 of the multiplexer 6 to it. The signal of the command end also goes to the output 25 of the device’s micro-operations and to the control input 39 of the address multiplexer 6. Since the device works in the first mode and signals

the torus to register 3 is recorded by the micro-operandion code MK of type B. On the falling edge of the next pulse from output 14.1 of generator 14, when a single or zero value of the checked logical condition in counter 2, respectively, either the address code is written from the output of the multiplex1), or the content is increased by unit (i.e., the address of the following MC is formed as in the case of reading type A MC). In the last MK of the working MP (MK Ipa C), the signal of the command end from the output of the 1.6 block floor is fed through the OR 15 element to the control input of counter 2, allowing entry from the input 41 of the multiplexer 6 to it. The signal of the command end also goes to the output 25 of the device’s micro-operations and to the control input 39 of the address multiplexer 6. Since the device works in the first mode and signals

There is no interruption of the checked logical level, then multiplexer 6

VIA. If it is single, then this signal through the element OR 15 is fed to the control input of counter 2, allowing it to be recorded from the output of multiplexer 6 address. The same single signal from the output of multiplexer 5 is fed to the control input 38 of multiplexer 6, informational input 35 of which contains an address code from the output of field 1.2 of block 1. Information from the outputs of fields 1.2 and 1.3 also goes to inputs 29 and 31 of blocks 7 and 8. However, at their outputs 26 and 41, if there is any request at the input 22 of the device interrupts, a false interrupt signal does not occur due to the lack of a single signal of the linear MK mark in the type MC

The device can go to the second and third modes of operation only after reading the linear MK, which should not be the last in the working MP. In fields x 1.2 and 1.3 of the linear MK of working MPs, codes of allowed and unacceptable cancellations are recorded. In the latest MC working MP and all MC MP interrupt is zero codes. They are fed to inputs 29 and 31 of blocks of 7 authorized and 8 invalid requests, respectively. Requests for interrupts are received at input 22 of the device, and then inputs 28 and 30 of blocks 7 and 8

B on inputs 27 and 42 of blocks 7 and B. Thus, only on one control - only after being formed by the generator

     14 clock pulse -on-14.1

(The interrupt request flow must be ordinary. The exception is invalid requests for any MP. One of such requests may appear together with an unresolved or allowed request. The address multiplexer 6 in the latter case will miss the operation code corresponding to this invalid input input on its output 38, a single signal is present at multiplexer 6. Therefore, address multiplexer 6 transmits the address code from its input 35 to the information input of counter 2, that is, from the output of field 1.2 of the block.

At a zero value of the checked logical condition, a single signal at the output of the element OR 15 does not appear and, therefore, is absent at the control input of the counter 2 of the address.

On the falling edge of the next time pulse from the output 14.2 of the

50

55

su). In order for the incoming request to be allowed (i.e., to interrupt the working MP), it is necessary that the input 22 of the device on which

0

h

five

passes to the information input of counter 2 the code of the new MP (the address of its first MC) from the input 21 of the operation code of the device. Further work in the first mode is similar.

The device can go to the second and third modes of operation only after reading the linear MK, which should not be the last in the working MP. In fields x 1.2 and 1.3 of the linear MK of working MPs, codes of allowed and unacceptable cancellations are recorded. In the latest MC working MP and all MC MP interrupt is zero codes. They are fed to inputs 29 and 31 of blocks of 7 authorized and 8 invalid requests, respectively. Requests for interrupts are received at input 22 of the device, and then inputs 28 and 30 of blocks 7 and 8

only after forming by generator

50

(The interrupt request flow must be ordinary. The exception is invalid requests for any MP. One of such requests may occur together with an unresolved or allowed request. The address multiplexer 6 in the latter case will miss the operation code corresponding to the invalid request for its output

su). In order for the incoming request to be allowed (i.e., to interrupt the working MP), it is necessary that the input 22 of the device on which

on the wils a single request signal, was connected to the first input of that element And from the block 44 elements And, on the second input of which there is a single signal with the corresponding bit field 1.2, 1.3 linear MK. The signal from the output of the corresponding element And, having passed through the element OR 45, is fed to the second input of the generator 14, which enters the second

25

thirty

element I 46, at the first input of which is a single signal of a linear MK tag from the output of the field 1.1. block 1. Thus, the block of 7 allowed requests generates an interrupt signal, by which the device switches to the second mode of operation. In order for the request received at input 22 to be invalid, it is necessary to fulfill the same conditions as for the allowed request, only already for elements AND of block 8. The invalid request block 8 generates a signal for interrogation and device transition to the third mode of operation in the same way as block 1.

When the device enters the second mode of operation, the interrupt signal generated by block 7 is fed to the control input 36 of multiplexer 6 and through the OR elements 16 and 15 to the control input of counter 2, allowing recording from the output of the multiplexer 6. The last one by its single signal Input 36 transmits to the information input of counter 2 an interrupt operation code generated by the encoder 9 upon an incoming request. The interrupt signal also passes through the OR element 16 to the second input of the AND 19 element.

On the next clock pulse from the output 14.2 of the generator 14, the micro-operation code MK of the working MP is recorded in the register 3. The same pulse arrives at the first input of the element And 19 and further to the synchronous input of the counter 4 return. On this pulse, the address of the already readable linear MK is entered into it from the output of counter 2. On the trailing edge of the next clock pulse from the output 14.1 of the generator 14 to the counter 2 from the output of the multiplexer 6, the interrupt operation code (address of the first MK) is entered and then the device operates in the same way as in the first mode. The only difference is that in linear MK codes of allowed and invalid interrupts are zero (MK

the input element And 18, the output of which is connected to the counting input of the counter 4 return, the latter increases its content by one. therefore

15 is the back edge of the register 3 zano-i. the latest micro-operation interrupt MP code is set. The signal of the end of the interrupt MT from the output of floor 1.5 of block 1,. also arrives at exit 25

20 micro-operations of the device, control input 39 of multiplexer 6 and through the OR 15 element to the control input of counter 2 addresses. Thus, the information input of counter 2 contains the address code from input 32 of multiplexer 6. This code from return counter 4 is the address of the next MC of the interrupted working MP and is entered into counter 2 on the falling edge of the next clock pulse from output 14.1 of the generator 14. Next, the device works in the first mode again.

In the third mode, i.e. according to the invalid interrupt signal generated by block 8, the device operates similarly to the second mode. The only difference is that the signal of an unacceptable interruption sets the error trigger 12 to one state and a single signal appears at the device output 26. The signal of the end of the interrupt signal MP read from the 1.5 field of the last MC of the interrupt MP arrives at the first input of the element I 17. At the next clock pulse from the output 14.1 of the generator 14, the counter code 2 records the address code from the output of the return counter 4, and a single signal from the output element And 17 zeroed trigger 12. The error signal at the output 26 of the device disappears.

The device finishes its work after writing to the register 3 of the micro-operation code of the last MC of the last MP program. In this case, at the output 24 of the output of the block 11 of the decoders, a signal of the end of the work arises, which arrives at the zero input of the trigger

35

40

45

five

Type D) and therefore the interrupt signals in the second mode cannot appear. In the 1.5 field of the end of the MT of the interrupt of the last MC When reading this MC from ROM 1, the signal of the end of the interrupt MF is fed to the first input of the element And 18. On the falling edge of the pulse from output 14.2

five

0

the input element And 18, the output of which is connected to the counting input of the counter 4 return, the latter increases its content by one. therefore

same falling edge in register 3 zano-i. the latest micro-operation interrupt MP code is set. The signal of the end of the interrupt MT from the output of floor 1.5 of block 1,. also arrives at exit 25

0 device micro-operations, control input 39 of multiplexer 6 and through the OR 15 element to the control input of counter 2 addresses. Thus, the information input of counter 2 contains the address code from input 32 of multiplexer 6. This code from return counter 4 is the address of the next MC of the interrupted working MP and is entered into counter 2 on the falling edge of the next clock pulse from output 14.1 of the generator 14. Next, the device works in the first mode again.

In the third mode, i.e. according to the invalid interrupt signal generated by block 8, the device operates similarly to the second mode. The only difference is that the signal of an unacceptable interruption sets the error trigger 12 to one state and a single signal appears at the device output 26. The signal of the end of the interrupt signal MP read from the 1.5 field of the last MC of the interrupt MP arrives at the first input of the element I 17. At the next clock pulse from the output 14.1 of the generator 14, the counter code 2 records the address code from the output of the return counter 4, and a single signal from the output element And 17 zeroed trigger 12. The error signal at the output 26 of the device disappears.

The device finishes its work after writing to the register 3 of the micro-operation code of the last MC of the last MP program. In this case, at the output 24 of the output of the block 11 of the decoders, a signal of the end of the work arises, which arrives at the zero input of the trigger

five

0

five

five

13 start and zero it, prohibiting thus the operation of the generator 14 clock pulses.

Thus, the proposed device allows an analysis of the admissibility of incoming interrupt requests, i.e. work in the control and diagnostics mode. In addition, the servicing of interrupt requests is accelerated by providing for each MC, at which an interrupt is possible, the right to interrupt as many different requests as possible.

Claims (1)

Invention Formula A microprogram control device containing a microcommand memory block, an address counter, an address multiplexer, a logic conditions multiplexer, a micro-operation register, a trigger, an error trigger, a clock generator, and the information output of the address counter is connected to the address of the memory block microinstructions, the output of the address field of which is connected to the first information input of the address multiplexer, the output of which is connected to the information input of the address counter, the output of the microoperations floor of the microcool memory unit Mand is connected to the micro-operation register information input, the device start input is connected to the installation input of 1 start trigger, the forward output of which is connected to the clock generator start input, the first and second outputs of which are connected to the address counter clock input and microoperations, the output label of the linear microcommand of the microcommand memory block is connected to the gate input of the logical conditions plexor, the output of which is connected to the first control input of address multiplexer, the output of the logic conditions of the microcommand memory block is connected to the multiplexer address input of the logic conditions, the logical conditions input of the device is connected to the information input of the multiplexer logic conditions, the forward error trigger output is connected to the output of the device error, the outputs of the signs Interrupt microprogram end and End of the microinstructions memory block command from Q 15 20 25 5 0 5 0 five Dineny respectively with the second and third control inputs of the address multiplexer and connected to the device outputs of the same name, the input of the operation code of the device is connected to the second information input of the address multiplexer, characterized in that: in order to expand the scope by providing processing of various types of interrupts, it additionally contains a decoder block, first and second encoders, a return counter, first to fourth elements OR, first to fifth elements And, first and second blocks of elements And, The output of the label of the linear microcommand of the microcommand memory block is connected to the first inputs of the fourth and fifth elements And, the interrupt input of the device is connected to the inputs of the first and second encoders and to the first inputs of the first and second blocks of elements And, the output address field of the microcommand memory block is connected to the second input of the first block of elements AND, the output of which is connected to the inputs of the third element OR, the output of which is connected to the second input of the fourth element AND, the output of which is connected to the first input of the second element OR and the fourth control input of the address multiplexer, the output of the logical conditions of the microcommand memory block is connected to the second input of the second block of AND elements, the output of which is connected to the inputs of the fourth OR element, the output of which is connected to the second input of the fifth AND element, the output of which is connected to the installation input in 1 error trigger, with the fifth control input of the address multiplexer and with the second input of the second OR element, the output of the logic conditions multiplexer is connected to the first input of the first OR element, the first output is generated the clock pulse is connected to the first input of the first element AND, the second output of the clock generator is connected to the first inputs of the second and third elements AND, the labels outputs the end of the microprogram of interrupts and the end of the command of the microcommand memory block are connected respectively to the second and third inputs of the first element OR, the output which is connected to the input of the counting record of the address counter, the output of the second element OR is connected to the fourth input of the first element OR and to the second input of the third element AND, the output of which is connected, to the synchronization input of the return counter, the output of the microinstructions memory interrupt microprogram Label is connected to the second inputs of the first element AND and the second element AND, you- JQ the course of the first element And is connected to the installation input in O of the error trigger, the output of the second element I is connected to the summing counting input Return counter, first and second outputs 15 Contents field 1.1 label linear MK Contents floor 1.2 addresses of the next MK The contents of field 1.3 of the code being verified are logical conditions Contents floor 1.4 microscope code Contents floor 1.5 end of interrupt command Contents floor 1.6 end of working team Note Types of commands: A is a linear MC of working MPs (the address of the next MC is generated by a counter-2 by increasing its content by one); B - MK branching (the address of the following MK is recorded in field 1.2, if the value of the logical condition, the code of which is recorded in field 1.3 of block 1, is one (otherwise the address of the next MC is formed as in the case of linear MC); C - the last MK in the working MP; it is always linear, but zero and 1.2 codes are written in its field 1.2 and 1.3, which prohibit interrupting this MC by any request; D is a linear MK in the MP of interruptions; in its fields x 1.2 and 1.3, zero codes are written, which makes it possible to exclude interruptions of the MP interrupts; the unit in field 1.5 is recorded only in the last (always linear) microcommand MP interrupt. the encoders are connected respectively to the third and fourth information inputs of the address multiplexer, the information OUTPUT of the address counter is connected to the information input of the counter. A return, the information output of which is connected to the Fifth information input of the address multiplexer, the output of the micro-operation register is connected to the input of the decoder unit, the output of which is connected to the output of the device microoperations, and the first output of the decoder unit is connected to the start triggering switch. Code allowed Address code and non-admissible code of the logical termination of catching Codes of micro-operations 0 (1)