SU1285471A1 - Control device for checking - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in the construction of monitoring and control systems, in particular those that control distributed hierarchically related control objects:. The purpose of the invention is to expand the scope by implementing control control in hierarchical systems. The control and monitoring device contains a firmware control block, an arithmetic unit, first and second counters, a selection block, a register, a comparison circuit, and decoders. The introduction of new elements: a block of choice, a register, a comparison scheme and a decoder, provides control over the control of multi-level groups of control objects, carried out the selection of a group of objects, determining the number of objects. low levels to be surveyed, the sequential inclusion and polling of the state of objects in this group of the system. 2 hp f-ly, 5 ill. with in (L

Description

The invention relates to computing technology and can be dismantled when building control systems and control systems, in particular, controlling the distributed j hierarchically related ontrol objects.

The purpose of the invention is to expand the range of application of the device by implementing control management in H hierarchical systems.

Figure 1 shows the functional diagram of the proposed device; FIGS. 2 to 4 are functional diagrams j5 of the firmware control unit, the arithmetic unit and the selection unit, respectively;; FIG. 5 is a diagram of the operation algorithm of the device. 20

The device (Fig. 1) contains a microprogram control block 1, an arithmetic block 2, a selection block 3, first 4 and second 5 decoders, register 6, first 7 and second 8 counters, comparison circuit 9, manual installation input 10 sanpoccJB for service, input 11 service requests, synchronization input 12 for manual installation of service requests, 30 start-stop input 13, control object response input 1h, control object output 15, control action output 16, initial installation input 17, outputs j 18 sign of failure of the control object.

The microprogram control unit (FIG. 2) contains a multiplexer 19, an address register 20, a microprogram memory block 21, a micro-command register 22, 40 a pulse generator 23, a first pulse generator output 23.1, a second output of a pulse generator 23y 23, element And 25, the second element And 26, the third element 45 And 27, - the first input 28 of the condition, the second input 29 of the condition, the third input 30 of the condition, the fourth input 31 of the condition, the input 32 of the start-stop, the input 33 of the initial installation, the eighth output 34, 50 second output 35, output 35.1 of the control element And the arithmetic unit, output 35.2 control switchboard arithmetic unit, output 35.3 control adder arithmetic unit, output 35.4 counting counter arithmetic unit, output 35.5 write to the counter arithmetic unit, fifth output 36.1, sixth output

36.2, first output 37, third output 38, seventh output 39, fourth output 40, output 41 of the address of the memory module of the microprogramme, output 42 of the operation field of the memory of the microprogramme, output 43 of the code field of the logical conditions of the memory microprogramme, output 44 fields of modifiable bits of the firmware memory block address.

The arithmetic unit (FIG. 3) contains a register 45, a counter 46, a sum of tbr 47, a comparison circuit 48, a switch 49, an AND 50 element, an AND-NOT 51 element, an input 52 of the operation code, an input 52, an element control AND, an input 52.2 of control the switch, the input 52.3 controls the adder, the counting input 52.4 of the counter, the input 52.5 records the account;

The selection block (FIG. 4) contains the register 53, the encoder 54, the input 55 of the one bit setting to zero, the output 56

The device works as follows

In the initial state, all the elements of the device memory are set to the zero state (external initial setting circuits are not shown),

In addition, the installation in the zero state can be carried out by a signal from the input 17 of the device. In this case, the signal from the input 17 enters the same input 33 of block 1 (Figures 1 and 2), where the setting to the zero state of the registers 20- occurs. and 22. In addition, the same signal through the OR element 24 of block 1 (FIG. 2) arrives at the output 40 of block 1 and sets the counters 7 and 8 (fig. 1) to the zero state at the inputs R and R, respectively.

After resetting, the device is ready for operation,

The output signal, 13 (FIG. 1), turns on the generator 23 of clock pulses of the control unit 1 (FIG. 2) of the device. At the same time, the input 11 of the device begins to receive the signals of requests for execution of the check from the control objects. At the same time, the corresponding signal from the group of inputs 11 sets after the synchronization pulse from the input 39 of the block 1 of the same name of the register 53 (FIG. 4) to one, and the priority encoder 54 outputs the code of the control object number to the group of outputs 56 of block 3 old imero priority.

After switching on the generator 23 (FIG. 2), the first clock pulse from the output 23.1 of the generator 23 into the register 20 records information from the outputs 41 of the field of the unmodified address bits of the next command A4 of the microinstruction memory 21 and from the outputs of the multiplexer 19. Since the register 20 is tentative is set to the zero state, then, information is selected from the zero cell of the microprogram memory unit 21; this cell contains the address of the first microcommand of the device operation microprogram. In this case, the code from the output 43 of the microprogram memory unit 21 specifies the transmission of the code of the modified address bits of the next microcommand without modification through the multiplexer 19 of block 1 (Fig. 2).

Thus, on the first clock pulse, the register 20 records the address of the first microcommand of the device operation.

The second clock pulse from the output 23.2 of the generator 23 records the micro-command code in the register 22, and the signals from the outputs 40, 42 and 44 of the microprogram memory block 21 form the address of the next micro-command in the same way as described above.

The signal from output 35.2 of register 22 through a group of outputs 35 of block 1; (FIG. 2) is fed to input 52.2 of block 2, thereby configuring switch 49 to connect the output 56 of block 3 to the D inputs of register 45.

In addition, a signal is output from the corresponding bit 36.2 of the group of outputs 36 of the register 22 of the block 1 (FIG. Reset of the object failure sign.

Next, the next first clock pulse from the output 23.1 of the generator 23 (FIG. 2) and the signal from the output of the corresponding bit of the register 22 are triggered by an element 25, the output signal of which goes to the output 37 of block 2 (fig.Z) and allows the code number to be written the control object of the upper level simultaneously in the register 45 of block 2 and the register 6 (Fig. 1) of the device.

This first clock pulse from the output 23.1 of the generator 23 (FIG. 2) records the code of the address of the next microcommand in the re

H5471 4

hist 20. On the second clock pulse from the output 23.2 of the generator 23, the next microcontrol command for controlling the operation of the device is written into the register 22, the outputs of the register 22 are excited in this microcommand to synchronize the arithmetic unit and control the counter. Therefore, on the first one

fO a clock pulse from the output 23.1 of the generator 23 of the block 1 (FIG. 2) triggers the element And 26, the signal from the output 38 of which produces an increase in the contents of the counters 7 and 8

 5 device (fig.O per unit.

In addition, in the considered microcommand, the signals from the output group 43 of the microprogram memory unit 21 (FIG. 2) are used to check the values of the output logic conditions of the comparison circuit 9 (FIG. 0) at the inputs 30 and 31 of the control unit 1.

In this case, if the output signal 30

0

0

equal to zero, and present at the output 31, which indicates the inequality of the contents of counter 7 and register 6 (Fig. 0), then the modification of bits 44 of the address field of the next microcommand is not made by multiplexer 19 of block 1 (figure 2). Therefore, next to the first clock pulse from the output 23.1 of the generator 23 of block 1, the address of the previous microcommand is recorded.For 5 this microcommand, similarly to that considered, is produced by the signals from the output 38, the contents of the counters 7 and 8 are increased and then the described above cyclically repeat action for a given microcommand.

Moreover, each time when the code in the counter 8 reaches the specified value of the size of the group of control objects, the decoder 4 is triggered (Fig. 0) and the counter 8 is set to the zero state.

Exit from the described cycle funk-. Unitization occurs when the contents of register 6 and counter 7 are equal. In this case, the signals at the outputs of the comparison circuit 9 are reversed.

Therefore, the multiplexer 19 modifiable bits of the address field of the next microcommand, coming from the outputs 44 of the microprogram memory unit 21 (Fig. 2), are converted to

five

0

the way that block 1 (diHr.l) proceeds to the implementation of the next microcommand control,) following the described cycle.

According to this microcommand, the device proceeds to the implementation of the next stage of work, consisting in the sequential polling of a given group of Control objects. To do this, in this microcommand, a microoperation signal is generated from output 35.5 of the register 22 of block 1 (Fig. 1). This signal through the group 35 of the outputs of block 1 (figure 1) is fed to the input 52.5 of the counter 46 of block 2 (fig.Z) and allows the recording of the contents of the counter 8, which determines the number of objects in the group to be checked, in the register 45 (fig. H).

The polling of control objects in a group begins with the lowest-level object having the lowest number in the group. For this, the smallest object number in the group is calculated by the next micro-command, in which the micro-operation signal is pushed from the output of the 35.5-register 22 (FIG. 2) of block 1. This signal is received through the corresponding bit of the group of inputs 35 of block 2 (FIG. 3) on Equal input 52.3 of adder 47 of block 2 (FIG. 3), in this case subtraction of counter code 46 in code 45 is performed. The resulting code from output 15 of adder 47 is displayed as an identifier signal and a poll for command signal trunk to which all objects of the control are connected . This signal is perceived only by the control object whose number matches the code on the outputs 15 of block 2 (Fig. 1).

This code is used to survey the state of a given object. The indication of the operating state of a given object is considered to be the issuance by this object of a response code equal to its own code (address) in the group. The response code of the control object arrives at a group of inputs 14 of block 2 (figure 1). In the case of equality of codes at the inputs A and B of the comparison circuit 48 (FIG. 3), a signal is output at its output, which is interrogated by the micro-operation signal from the output 35.1 of the register 22 (FIG. 2) in the next microcommand of the operation of block 1,

five

0

This signal from output 35.1 of block 1 is input to input 52.1 of block 2 and then to the input of element I 50 (FIG. 3), to the other input of which the output signal of circuit 48 is received.

The output signal of AND 50 (FIG. 3) is used at input 28 of multiplexer 19 (FIG. 2) as a logical branch condition in the control firmware.

If the signal at the output 28 of block 2 (fig.Z) is present, which indicates a repair and a specified volume. from the outputs 15, the device proceeds to the next microcommand of the control microprogram, in which the micro-signal from the output 35.4 of the register 22 of the block 1 (figure 2), which enters the input 52.4 of the block 2 (fig.Z), decreases the content the counter 46 per unit and further along the next micro-command, similarly to the described type, subtraction is carried out on the adder 47

 counter 46 of Register Contents 45. Thus, the code of the object of the next higher level is formed, and then the above-described operations for polling its state are carried out.

0

If the signal at the output 28 of the element And 50 of block 2 (fig.Z) is absent, which indicates a failure in a given control object, then

. The logical condition (zero in this case) signal, which enters the input 28 of the multiplexer 19 of block 1 (FIG. 2), is transferred to the next control micro-command, which has the following actions.

From the output 36.1 of the microprogram 1 of the multi-control unit, the output 18 of the device receives a signal of the sign 5 for the control object. Next, the device proceeds to the execution of the next microcommand control, which is implemented in the same way as described above,

Thus, the device is after

0 polls a group of objects of control before they are exhausted; As soon as the next microcommand for controlling the device is executed, the contents of the counter 46 (Fig. 3) are set to zero, the AND-HE element 51 is triggered, the output signal 29 of which is logically: - a condition for ending the monitoring of a given group of objects. This logical condition is fed to the input 29 of multiplexer 19 of block 1 (FIG. 2), which modifies the address of the next micro-control command such that the device proceeds to the micro-command to complete the interrogation cycle of a given group of objects

In this micro-command, a micro-operation signal is produced at the output 34 of the register 22 of block 1 (FIG. 2), according to which the decoder 5 is activated.

The D-inputs of this decoder from the outputs of register 6 receive the code of the highest level entity that issued the verification request. The unitary code from the decoder 5 (Figs, 1 and 4) sets to the zero state the bit RR of the register 53 corresponding to the served request.

After that, the device proceeds to the next micro-command of control, according to which the preparation of the memory elements of the device to the op. dew of the next group of objects

In this case, the micro-operation signal from the output of the corresponding register bit 22 through the OR 24 element (FIG. 2) resets the counters 7 and I (FIG.), And the micro-operation signal from the register 22 output of the block 1 (FIG. 2) in the presence of a clock pulse. from the output 23.2 of the generator 23 from the output 39 of the unit 1, a request synchronization signal is output to the register 53 of the unit 3 (FIG. 4).

Next, the device proceeds to the selection and processing of the request of the highest priority in the same way as described above,

The setting of the object code in block 3 (FIG. 4) can be carried out not only from the device outputs 11 (FIG. 1), but also from the input 10 of manually setting the request by the write synchronization signal 12 of the manual setting of the request. In this case, the input signal 12 is fed to the synchronization input of the register 53, into which information from the inputs 10 of the device is entered.

If it is necessary to stop working the device, its input 13 Figures, 1) receives a stop signal. As a result, the generator 23 of block 1 (FIG. 2) is turned off, thereby stopping the operation of the device.

Claims (3)

: Invention Formula 1, A control control unit containing a microprogram control unit, an arithmetic unit, first and second counters, the first and second outputs of the signs of the result of the arithmetic unit being connected respectively to the first and o second inputs of the micro conditions of the block. software control, the input of the response of the control object of the device is connected to the primary information input of the arithmetic unit, the first 5 and the second information outputs are arith-. The control unit is, respectively, the output of the object number of the control unit and the output of the control device, the first 0 output of the firmware control block is connected to the synchronization input of the arithmetic unit, the second output of the firmware control block is connected to the operation code input of the arithmetic block, the third output of the block firmware control is connected to the counting inputs of the first and second counters; the fourth output of the firmware control block is connected to the installation input to zero of the first counter and with the first input of the installation to zero of the second counter, the input of the initial installation of the device is connected to the input of the initial set. 5 of the firmware control block, the start-up input of the device is connected to the start-stop input of the microprogram control block, the information output of the second one. The counter 0 is connected to the second information input of the arithmetic unit, the fifth and sixth outputs of the microprogram control block are combined and are the output of the signs of the 5 rejection of the control object of the device, characterized in that to expand the scope of control by implementing control control in hierarchical systems The arrangement additionally contains a comparison circuit, the first and second decoders, a register, a selection block containing a register and an encoder, the inputs of the service requests of the device 5 being connected to the input terminal. By setting the unit of bits of the register of the selection unit, the seventh output of the firmware control unit is connected to the first synchronization input of the selection register. 91 input manual installation of service requests of the device connected to the information input of the register of the selection block; synchronization input manual installation of service requests of the device connected to the second synchronization input of the register of the selection block whose output is connected to the input of the encoder of the selector whose output is connected to the third information input of the arithmetic and with the information input of the register, the information output of the second counter is connected to the input of the first decoder, the first output of which is connected to the second the input of the second zero meter, the information output of the register is connected to the first input of the comparison circuit and the information input of the second decoder, the outputs of which are connected to the inputs of the zero digit register of the selection unit, the information output of the first counter , the outputs of equality and inequalities of which are connected respectively to the third and fourth inputs of the conditions of the microprogram control unit, the eighth output of which is connected to the gate input of the second eshifratora, .First mikroprogrammno- output of the control unit is connected to the synchronization input of the register. 2. The device according to claim 1, as follows: if the firmware control block contains a multiplexer, an address register, a microprogram memory block, a micro-command register, a pulse generator, the OR element, the first through the third AND elements, and the first the fourth information inputs of the multiplexer are connected respectively to the first ho fourth inputs of the block conditions, the output of the address register is connected to the address input of the microprogram memory block, the output of which address field is connected to the second information input of the address register, output the field of modifiable bits of the block address. firmware firmware is connected to the fifth information input of the multiplexer, the output of which is connected to the first information input of the address register, the output field of the code of logical conditions of the firmware memory block is connected to the control o 0 five 5A7 five 35 0   ten , the multiplexer input, the output of the microprocessor memory module oiiepauHH is connected to the micro-domain register information input, the first local control field output of which is connected to the eighth block output, the pulse generator start input is connected to the block start-stop input, the first output of the pulse generator is connected with the synchronization input of the address register and with the first inputs of the first and second elements AND, the outputs of which are connected respectively. The first output of the pulse generator is connected to the first input of the third element I and to the sync input of the micro-command register, the second output of the local control field of which is connected to the second output of the block, the outputs of setting the micro-command register and address register to zero, and the first input of the OR element are combined and connected to the input of the initial installation of the block, the first and second outputs of the symptoms of the object of control of the register of micro-commands are connected to the fifth and sixth outputs of the block The third output of the local control field of the micro-command register is connected to the second input of the OR element, the output of which is connected to the fourth output of the block, the fourth, fifth and sixth output of the local control field of the micro-command register are connected to the second inputs of the first, second and third elements, respectively. , the output of the third element And is connected to the seventh output of the block. 3. The device according to claim 1, about tl and - chchaechets. We have, that ari || the meth- odic block contains a counter, register, switch, adder, circuit 45, the AND element, the AND – NE element, and 0 0 0 the first input of the element I, the control input of the switch, the gate input of the adder, the counter input and the input of the counter record are combined and connected to the input of the operation code of the block, the format output of the counter is connected to the input of the first addendum ad unit the output of which is connected to the second output 5 of the indication of the result of the block, the information input of the counter is connected to the second information input of the block, the information input of the register is connected to the third information input of the block .11 .ka, the register synchronization input is connected to the block synchronization input, the first input of the comparison circuit is connected to the first information input of the block, the information output of the register is connected to the input of the second term of the adder and the first information input of the adder whose output is connected to the second input of the 547112 circuit we compare with the second inLorma tion output of the block, the equality output of the comparison circuit is connected to the second input of the element I, the output of which is connected to the first output of the result of the block, the output of the adder co. 1 is connected to the second information input of the switch and the first information output block. FIG. 7 Fmg.5 3 35 36 37 2 56 FIG. FIG. five