SU1310816A1 - Microprogram control device - Google Patents

Abstract

The invention relates to computing and can be used in computers and other digital systems with firmware. The aim of the invention is to improve the speed of the device. The device contains a memory block, microinstructions, address register, residue register, microinstruction register, output register, switches, decoders, adders, multiplexer, triggers, pulse generator, AND blocks, OR block, OR elements. New in the device are the register output, the switch, the decoder, the adder, the trigger, the blocks AND the elements, the element S. In the device, several microinstructions are placed in one line of the memory block. In order to match the single microcommands, one or maximum two lines of the memory block must be counted, the placement of all the microcommand blocks in the memory block is independent of the type of microcommand from top to bottom, and the placement in each block of microinstructions - from left to right and from top to bottom. 4 il. i SL 00 O)

Description

The invention relates to digital computing and can be used in the construction of microprogrammed control devices for computers and digital systems.

The purpose of the invention is to increase the speed of the device,

Figure 1 and 2 shows the functional diagram of the device; FIG. 3 shows an example of the placement of micro-instructions in a memory block; Fig. 4 shows examples of the placement of complete and incomplete micro-instructions in blocks and the order in which they are numbered;

The device (phi g, 1 and 2) contains a block of 1 memory of micro-instructions, a register of 2 addresses, a register of 3 remnants of micro-instructions, a register of 4 micro-instructions, a register of 5 outputs, a switch 6 of addresses, a com-. a control mutator 7, a command switch 8, a switch 9 residues, a decoder 10 commands, a decoder M residuals, a first adder 12 addresses, a second adder 13 addresses, g-1 multiplexer 14, first trigger 15, second trigger 16, clock generator 17, the first block 18 And elements, the second block 19 elements And And, the seventh block 20 elements And, the sixth block 21 elements And, the fifth block 22 elements And, the third block 23 elements And, the fourth block 24 elements And, the block 25 elements OR , second element OR 26, first element OR

Dov 48 switchgear. residues, the second group of outputs 49 switch residues, output 50 switch commands,

The device works as follows:

In the initial state, all the triggers are in the zero state. The installation inputs to the initial state are not

IQ are shown), the Start signal is sent to the input 29, the trigger 15 unlocks the generator 17 and the first clock pulse from the output 43.1 of the generator 17 allows the recording of the starting address from the input JJ 28 through the switch 6 to the register 2, On the first clock pulse from the output 43.2 of the generator 17, register 3 is written the first line of the microinstructions block, in which there is

20 readable microcommand. By the same impulse that passed through the OR element 26, the trigger 16 is converted into a unit of 20 elements AND, unmasking 25 the second part of the address. In the adder 13, the first and second parts of the address are added, resulting in the address of the required string of there is a readable microcommand or part of it.

At the first clock pulse from output 43.3, this line is written to register 4. At the same time, one of the decoder outputs 42, 10 27, input 28 of the operation code of the device,, the unit potential is set, device start input 29, input 30 Output number corresponds to the number

device shutdown, input 31 of logical conditions of the device, group of outputs 32 micro-operations of the device, where output 32.1 is the output of the sign End of operation, output 32.2 - output of the sign End of the command, output 33 of the address register address field, output 34 address increment fields of the address register, output 35 of the microcommand number of the address register, output 36 of the branch mark, output 37 of the register of residuals output 38 of the microcommand register, output 39 of the address field of the microcommand of the output register, output 40 of the logic code of the output register, output 41 of the decoder remnants, output 42 of the command decoder, output group 43.1-43.4 of the pulse generator, output 44 of the sixth block of elements And, output 45 of the block of elements And, output 46 of the third block of elements And, output 47 of the fourth block of elements And, first group outputs 48 switchgear. residues, the second group of outputs 49 switch residues, output 50 switch commands,

The device operates as follows.

In the initial state, all the triggers are in the zero state. The installation inputs to the initial state are not

are shown), the Start signal is sent to input 29, trigger 15 unlocks generator 17 and the first clock pulse from output 43.1 of generator 17 allows writing the starting address from input 28 through switch 6 to register 2, On the first clock pulse from output 43.2 of generator 17 register 3 is written the first line of the microinstructions block in which there is

readable microcommand. By the same impulse that passed through the OR 26 element, the trigger 16 is translated into uniform microcommands in a string written in binary code in register 2, to the decoder 10. This code is fed from turn 35 of register 2 through blocks of elements AND 19 and OR 25, t, e, a third part of the address is provided. If the microinstruction (branching or linear) is the last in the line, then. unit jj ky potential from the corresponding output 42, having passed through the switch 7, enters the gate input of the decoder I, unblocking it. On one of the flywalks 41 decoder II

rQ appears unit potential. The number of this output corresponds to the line number of the readable block of microinstructions (the counting of lines of the block of microcommands begins with O), thus unambiguously determining the necessary remainder (the line number of the block of microcommands corresponds to the residue number in the first row, to the counting of residues from the first) .

31310816

In the interval between the first pulses from the outputs 43.3-43.4 in the switches 8 and 9, all transients associated with the formation of a readable micro-command end. 5 As a result, a microcommand is formed at the output 50 of the switch 9 of commands. On the first pulse from the output 43.4 of the generator 17, it is recorded in the register 5. By the same name, the pulse passing through the OR 26 element, the trigger 16 is whipped, masking the second part of the address, since the AND 20 block of elements is closed.

On the second clock pulse from 5 output 43.1 of the generator 17, the address of the next microcommand is written to register 2. In this case, the input 28 is blocked, since if this is not the last

Such a state of the switch 7 will be until such time a microinstruction is written to register 5, in which at output 32.2 it is not equivalent to zero. If, during operation of the device at output 32.1, a unit is wits, then, having passed through the OR element 27, it flushes the trigger 15, thereby blocking the generator 17. The device switches off. Starting is possible only when units are fed to device 29 input. The device can be stopped externally; to do this, it is sufficiently fed to the input 30 units.

F o rumula of an image of a shadow Firmware manager of a microprogram command, output 20 containing a micro30 memory block

32.2 will be Oh, the device works similarly.

I

If the branch firmware was read from the output of the device, then the 25 output of the multiplexer 14 could be achieved by one (if a linear command is read, then there will always be zero at the output of the multiplexer). If zero is present at the output of multiplexer 14, the AND block 18 of elements is closed, and the block of 19 elements of AND opens, a third part of the address passes through the block of 25 elements OR to the input of the decoder 10 unchanged. If a unit is present at the output of the multiplexer 14, then the I-element block 18 is opened, and the I element block 19 is closed, the third part of the address, passed through the adder 12, is changed by one. The modified address, passed through a block of 25 elements OR, is fed to the input of the decoder 10.

The fourth part of the address, recorded in register 2, plays the role of a control signal depending on what type of microcommand is read: zero corresponds to the branching microcommand, the unit is linear.

35

40

45

commands, register of residues, register of micro-commands, address switch, ksm-muta; control torus, command switch, address register, decoder for comans, first OR element, first trigger, pulse generator, first to fourth blocks of AND elements, element block OR, first adder address, multiplexer, and the input operation code of the device is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the input of the logical conditions of the device connected to information inputs multi The iplexer, the output of which is connected to the first input of the first block of elements And and with the inverse input of the second block of elements And, the output field of the microcommand number of the address register is connected to the remaining inputs of the first and second blocks of elements And, the first to the third outputs of the pulse generator are connected to the synchronization inputs respectively, the address register, the residual register, and the microinstructor register; the output of the branch register's address register is connected to the control input of the switch; the label opens or closes the switches; m input of the third bypassable blocks of elements And 21, 22, of the block of elements And, with the first entrance

23 and 24, and also controls the inputs of the switch 7.

If when reading the next microcommand at the output 32.2 of the device, a unit appeared, then the first pulse from the output 43.1 of the generator 17 will register in the register 2 a new code of the actions from the input 28 of the device.

the fourth block of the And elements and the first control input of the command instruction coil, the outputs of the third and fourth JJ5 units of the And elements are connected respectively to the second and third control inputs of the Komats com1F1, the output of the first block of And elements is connected to the input of the first operand

Such a state of the switch 7 will be until such time a microinstruction is written to register 5 in which zero does not appear at output 32.2. If, during operation of the device at output 32.1, a unit is wits, then, after passing through the OR element 27, it flushes the trigger 15, thereby blocking the generator 17. The device switches off. Starting is possible only when the unit is fed to the input device 29. The device can be stopped from the outside, for this purpose it is sufficiently supplied to the input 30 units.

F o rumula image of the shadow of a microprogram control device containing a micro0 memory block

five

five

0

five

commands, register of residues, register of micro-commands, address switch, ksm-muta; control torus, command switch, address register, decoder for comans, first OR element, first trigger, pulse generator, first to fourth blocks of AND elements, element block OR, first adder address, multiplexer, and the input operation code of the device is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, the input of the logical conditions of the device connected to information inputs multi The iplexer, the output of which is connected to the first input of the first block of elements And and with the inverse input of the second block of elements And, the output field of the microcommand number of the address register is connected to the remaining inputs of the first and second blocks of elements And, the first to the third outputs of the pulse generator are connected to the synchronization inputs respectively, the address register, the residual register and the microinstructions register, the output of the address register branching tag is connected to the control input of the switch of the fourth fourth block of elements And with the first control input one command coder, the outputs of the third and fourth JJ5 units of elements I are connected respectively to the second and third control inputs of the commatics cofactor, the output of the first block of elements I are connected to the input of the first operand

the first adder address, the output of which is connected to the first input of the block of elements OR, the output of which is connected to the input of the command decoder whose outputs are combined and connected to the remaining inputs of the third and fourth blocks of the elements And to the information inputs of the control switch, the second operand of the adder address is connected to the bus of the logical unit of the device, the output of the second block of elements AND is connected to the second input of the bdoc of elements OR, the output of the memory block of microcommands is connected to the information inputs of the register for the microinstructions register, the output of the microinstructions register is connected to the first information input of the command switch, the device launch input is connected to the installation input of the first trigger, the device stop input is connected to the first input of the first OR element, the output of which is connected to the installation input of the first trigger O The output of which is connected to the trigger input of the pulse generator, characterized in that, in order to increase speed, a residual decoder, a second address adder, a second trigger, a second el ment OR, from the fifth to the seventh blocks of elements AND, the output register, and the second output of the pulse generator is connected to the first input of the second element OR, the output of which is connected to the counting input of the second trigger, the output of which is connected to the first input of the seventh block of elements AND, the output field the address of the first row of the register of the address is connected to the input of the first operand of the second adder of the address, the output of which is connected to the address input of the microcircuit memory unit

Mand, the output of the address register's address increment field is connected to the input of the residual deshifter and to the second input of the seventh And block, the output of which is connected to the input of the second operand of the second address adder, the output of the address register branch branch marker is connected to the first input of the fifth And block block of the And and inverse

input of the sixth block of elements And, output, the switch stroke is connected to the gate input of the residual decoder, the outputs of which are combined and connected to the remaining inputs of the fifth and

of the sixth block of elements And, the output of the n block of elements And connected to the first control; the input of the residual switch, the output of the sixth block of elements And connected to the second control

Shdm input of the residual switch, the first output of which is connected to the second information input of the command switch, the output of the residual register is connected to the information input of the residual switch, the second output of which is connected to the third informatdione input of the command switch, the output of which is connected to the information inputs of the output register, output field whose address is connected to the second information input of the address switch, the fourth output of the pulsed-oscillator is connected to the second input of the second element I and to the synchronous input3 5 zation of the output register, output of the pole

the conditions of which are connected to the control input of the multiplexer, the output field of the microoperations of the output register is the output of the device, the output of 40 characters. The end of the operation of the output register is connected to the second input of the first OR element, the output of the sign. The end command of the output register is connected to the control input of the switch ad.res .

figure 1

37

f

2c

ten .

39

32

eight

32.1 -M

32.2

-WITH

23

46

24

47

 CPUB.J

Subdlock of “full micro-commands

Subblock, incomplete microinstructions

Compiled by A.Soshkin Editor M.Dshin TeHred L.Olninyk Proofreader L.

Order 1892/45 Circulation 673 Subscription VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

fig4

Claims (1)

Claim A microprogram control device containing a micro-command memory block, a remainder register, a micro-command register, an address switch, a control switch, a command switch, an address register, a command decoder, a first OR element, a first trigger, a pulse generator, from the first to the fourth block of AND elements, a block of elements OR, the first adder of the address, the multiplexer, and the input of the device operation code is connected to the first information input of the address switch, the output of which is connected to the information input of the address register, log input The device’s conditions are connected to the information input of the multiplex output of which is connected to the first input of the first block of AND elements and to the inverse input of the second block of AND elements, the output of the address register microcommand number field is connected to the remaining inputs of the first and second blocks of AND elements, from the first to third outputs of the pulse generator connected to the synchronization inputs, respectively, of the address register, register of residues and the register of microcommands, the output of the branch mark of the address register is connected to the control input of the switch control, with the inverse input of the third block of elements And, with the first input of the fourth block of elements And and with the first control input of the command switch, the outputs of the third and fourth blocks of elements And are connected respectively to the second and third control inputs of the command switch, the output of the first block of elements And is connected to input of the first operand 5 · the first adder of the address, the output of which is connected to the first input of the block of OR elements, the output of which is connected to the input of the command decoder, the outputs of which are combined and connected to the other inputs of the third and fourth blocks of AND elements and to the information inputs of the control switch, the input of the second operand of the Adder the address is connected to the bus of the logical unit of the device, the output of the second block of elements AND is connected to the second input of the side of the elements OR, the output of the memory block 'microcommands is connected to the information inputs of the remainder register For example, the microcommand register, the microcommand register output is connected to the first information input of the command switch, the device start input is connected to the first input of the first trigger, the device stop input is connected to the first input of the first OR element, the output of which is connected to the first input of the first trigger the output of which is connected to the start input of the pulse generator, characterized in that, in order to increase speed, a residual decryptor, a second address adder, a second trigger, and a second element are introduced into the device OR, the fifth through seventh blocks of AND elements, the output register, the second output of the pulse generator, connected to the first input of the second OR element, the output of which is connected to the counting input of the second trigger, the output of which is connected to the first input of the seventh block of AND elements, the output of the address field the first line of the address register is connected to the input of the first operand of the second adder of the address, the output of which is connected to the address input of the micro memory command block, the output of the increment field of the address register address is connected to the input of the remainder decoder and the second input of the seventh block of elements And, the output of which is connected to the input of the second operand of the second adder address, the output of the branch mark of the address register is connected to the first input of the fifth block of elements And and with the inverse 1θ input of the sixth block of elements And, you-. the switch is connected to the gate input of the residual decoder, the outputs of which are combined and connected. . yen with the remaining inputs of the fifth and 15th sixth blocks of elements And, the output of the fifth block of elements And is connected to the first control input of the remainder switch, the output of the sixth block of elements And is connected to the second control20 input of the remainder switch, the first output of which is connected to the second information input of the command switch, the output of the residual register is connected to the information input of the residual switch 25, the second output of which is connected to the third information input of the command switch, the output of which is connected to the information one. output register input, field output 50 of the address of which is connected to the second information input of the address switch, the fourth output of the pulse generator is connected to the second input of the second element And and to the synchronization input 35 of the output register, the output of the condition field of which is connected to the control input of the multiplexer, the output of the microoperation field of the output register is the device output, the output at 40 characters. The end of operation of the output register • is connected to the second input of the first OR element, the output of the flag The end of the output register command is connected to the control input of the address switch. Fig 2 131 081 6 Subunit of “full’ 'microcommands 4't Wa 112 '(h) 116 '(4) 1 2 3 4 1 6 (2} 7 (3) ^ H31 \ Ijiii / 4 (2) 75 (3) Subblock ,, incomplete microcommands 6b) No.IWIJmsi t sh 1 2 3 4 5 6 7 (1) J (2) ~~~ 1 (3) - 10 (4) 71 (5) ΊΪ Spare parts 1 & gg 33 (h) 34 (4) 35 (5) Ik srig4