SU1179338A1 - Microprogram control device - Google Patents

Abstract

MICROPROGRAMME CONTROL DEVICE, containing a microcommand constant memory block, address register and microcommand register, multiplexer, first address switch, start trigger, clock generator, the device start input connected to a single trigger trigger input, the output of which is connected to the clock generator input , the output of the register of the address is connected to the address input of the microcommand memory block, the first information output of which is connected to the first information input of the register of the microcoma The output of microoperations of the register of micro-commands is connected to the output of microoperations of the device, and the output of the micro-operation “End of work is connected to the zero input of the start trigger, the output of the logical conditions of the register of micro-commands is connected to the control input of the multiplexer, the information input of which is connected to the input of the logical conditions of the device, the output of the first switch The address is connected to the information input of the address register, characterized in that, in order to reduce the amount of equipment, a second address switch is inserted into the device, buffer register, AND block, first, second and third AND elements, OR element, the input of the operation code of the device is connected to the first information input of the first address switch, the first output of the clock generator is connected to the synchronization input of the address register, the second output of the clock generator is connected with the micro-command register synchronization input and the first input of the first element I, the output of which is connected to the synchronization input of the buffer register, the first and second outputs of the buffer register are connected with the first groups of inputs, respectively, of the first and second information inputs of the second address switch, the output of which is connected to the first group of inputs of the second information input of the first address switch, i the second information output of the microcommand constant memory block is connected to the input (Lation input of the buffer register, direct the input of the block of elements AND and the inputs of the element OR, the output of the block of elements AND is connected to the second information input of the register of microinstructions, the output of the element OR is connected to the inverse input of the second The And element and the direct input of the third And element, the outputs of which are connected respectively to the output error of the device and the first control input of the second; from the address switch, the output of the logic conditions of the microcommand constant memory block is connected to the inverse inputs of the element block 00 And with the direct inputs of the first and second element And, and with the inverse input of the third element And, the output of the multiplexer is connected to the second control input of the second address switch, the outputs of the unmodifiable and modified parts of the address register micro-commands are connected respectively to the second group of inputs of the second information input of the first address switch and the third information input of the second address switch; the output of the microoperation The end of the micro-command register command is connected to the direct and inverse control inputs of the first communi

Description

The address, first, and second groups of outputs of the modifiable part of the microcommand register address are connected to the second groups of inputs of the first and second information inputs of the second address switch, respectively.

one

The invention relates to automation and computing and can be used in the construction of central and peripheral control devices of computers and computer systems.

The aim of the invention is to reduce the amount of equipment used.

FIG. 1 shows a functional diagram of a firmware control device; in fig. 2 - a fragment of the implemented firmware; in fig. 3 - placement of information in the fields of micro-instructions preceding branching (F1) and branching micro-commands (F1).

The microprogram control unit (Fig. 1) with a control unit contains a block of 1 permanent memory of micro-commands, an address register 2 and a micro-command register 3, a buffer register 4, the first 5 and second 6 address switches, a multiplexer 7, an 8-clock trigger generator 9 , the first element And 10, the element OR 11, the block 12 elements And, the second 13 and the third 14 elements And, the inputs of the operation code 15, the logical conditions 16 and the launch 17 of the device, the outputs of micro-operations 18 (including the outputs of micro-operations “End of command 18.1 and “End of work 18.2) and device error 19, first 20 and in Ora 21 exits the generator 8, the first 22 and second 23 data outputs and output 24 of logic unit 1 conditions constant memory microinstructions nemodifitsiruemey outlets 25 and 26 parts modifiable address register 3, the first 27 and second 28 outputs register 4.

FIG. 2 and 3, the following notation is used: R; - microinstruction i; X, - is a logical condition j; F1 is the micro-command format preceding the branch micro-command; F2 is a branch microcommand format.

The purpose of the main elements of the firmware control device (Fig. I) is as follows.

The block 1 of the permanent memory of micro-commands is intended for storing the address and operating parts of the micro-commands, the logical conditions codes of the label M, intended for controlling the operation of the device.

The address register 2 is intended to store the address of the next microcommand. The next address is written to the address register 2 on the trailing edge of the first clock pulse generated by the generator 8 clock pulses.

Register 3 of microinstructions is intended for receiving, storing and issuing microcommands, each of which contains a field of unmodifiable address bits, a field of modifiable address bits, a field of microoperation, a label field and logical condition codes. The recording of the next microinstruction in the register 9 microinstructions is carried out on the falling edge of the second pulse. The buffer register 4 is designed for receiving, storing and issuing modifiable address bits of the microcommand for branches read from the field of logic codes

5 conditions of block 1 on the trailing edge of the second clock pulse at the enabling signal of the mark.

The first address switch 5 is designed to switch the address of the next microQ command. In the absence of a micro-operation signal “The end of the command at the output 18.1 of the register of 3 micro-commands, the address formed from the modified and unmodifiable parts — the composite address — arrives at the information input of the register 2 address.

5 Otherwise, the code of the operation being executed from the input 15 of the device, which determines the address of the first microcommand of the corresponding microprogram, is transferred to register 2.

The second address switch 6 is designed to form the modifiable part of the address of the next microcommand from the address address bits being modified, arriving at its information inputs from outputs 26 of register 3 microcommands and outputs 27 and 28 of buffer register 4 in accordance with the control signals from multiplexer 7 and the third element And 14. In the absence of a signal from the output of the third element And 14 all non-modifiable bits of the output address 25

0 directly, and from the output 26 of the register of 3 micro-commands through the switch 6, arrive at the second information input of the first switch 5 of the address. However, there is no information at the output of the buffer register 4. After the appearance of the signal at the output of the element 14, the address of the next microcommand is formed taking into account the value of the checked logical condition on the multiplexer 7. At a single signal value from the output of the multiplexer 7, the input of the first switch 5 receives a part of the address generated from the modified address bits received the input of the switch 6 from the output 26 of the register of 3 micro-instructions and 27 of the buffer register 4, corresponding to a single value of the logical condition being checked. When the signal from the output of multiplexer 7 is zero, the address generated by the modified address bits, which are input to the switch 6 of the address from the output 26 of the micro-command register 3 and the output 28 of the buffer register 4, correspond to the zero value of the checked logical condition .

Multiplexer 7 is designed to extract the value of the logical condition being tested. For this purpose, the logic inputs of the information inputs are fed to the input 16 of the device, and the control inputs are the codes of the checked logic conditions from the register output of 3 microcommands.

The generator 8 clock pulses is designed to synchronize the operation of the device. At its outputs 20 and 21, the first and second clock pulses are formed, respectively.

The trigger 9 is designed to control the start of the generator 8 clock pulses. It is turned on by the “Start” signal, which is fed to the device input 17, and shutdown, by the “End of operation from the output 18.2 register of 3 microcommands. The first element 10 controls the transfer of a clock pulse from the output 21 of the generator 8 clock pulses in accordance with the value of the control label to the clock input of the buffer register 4.

The element OR 1 1 is intended to give a signal about the presence of information in the field of logical conditions of a microcommand.

Block 12 of the AND elements controls the arrival of the bit positions of the logic conditions to the second information input D2 of the micro-command register 3 in accordance with the value of the control label.

The second element And 13 forms at the output of the device 19 a signal “Error. A signal is generated under the condition that the label appears in the absence of information in the field of the logical conditions of the microcommand.

The third element And 14 is designed to generate a signal that controls the address switch 6.

Consider the operation of a firmware control device.

In the initial state, all the memory elements of the device (Fig. 1) are in the zero state with the exception of a single state of the register register 3 microcommands corresponding to the output 18.1 of the register 3 microcommands. Circuit bringing in the initial state on the diagram conventionally not shown. The latter permits the transfer through the switch 5 of the operation code from the input 15 of the device for subsequent writing to the address register 2.

According to the "Start" signal from the device input 17, the trigger 9 is set to one state and the generator of 8 clock pulses is turned off. The first clock pulse from the output 20 of the generator 8 into the address register 2 from the input 15 of the operation code of the device through the first address switch 5 records the code of the implemented operation, which determines the address of the first micro command corresponding to the firmware. Consider the implementation of the linear portion of the firmware.

In this case, there is no information in the logic field of micro-instructions and

0 label value is zero.

On the second clock pulse from the output 21 of the generator 8, the address of the next micro-command and the micro-command code are recorded in the register of 3 micro-commands. The micro-command code is issued from the outputs of the register 3

 microinstructions on the output 18 micro-operations of the device. The unmodifiable address bits come from the output 25 of the register of 3 microcommands to the second information inputs of the address switch 5; And the modified bits of the address from the output 26 of the register of 3 micro-commands through the second switch 6 of the address are transmitted to the second information input of the switch 5 by the resolution signal from the output 18.2 of the register 3. Thus, the address of the micro-command is the sum of the non-modified high-order address bits (Fig. 3 ), modified address bits corresponding to the zero value of the checked logical conditions, modified address bits corresponding to the single value of the checked logical

0 conditions.

At the next clock pulse from the output 20 of the generator 8 clock pulses into the address register 2 from the second and third information inputs of the second address switch 6, the generated microcommand address is read and the device operates as described. If necessary, the implementation of the conditional transition device operates as follows.

0 In the format of the logical conditions (Fig. 3) microcommands preceding the branch microcommand, the modified parts of the address are specified: the address bits being modified, corresponding to the zero value of the logical condition being checked

5 and modifiable address bits corresponding to a single value of the checked logical condition and a control label M. As a result of this

the label blocks the passage of information to the second information input of the register of 3 micro-instructions and provides the recording of the second clock pulse from the output 21 of the generator 8 through the first element AND 10 of the modified address bits to the buffer register 4.

On the first clock pulse from the output 20 of the generator 8, the generated address is recorded into the address register 2, at which the branch micro-command is read.

In the format of this microcommand, the label M is absent; therefore, reading of information into the buffer register 4 is blocked, and the second microcommand code and the microoperations codes are recorded in microcommand register 3 by the second clock pulse from the output 21 of the clock oscillator 8 clock pulses. In this case, the output signal of the element And 14 allows you to generate two addresses. The choice of the necessary one is made in accordance with the signal from the output of the multiplexer 7. At a zero value of the logical condition, the address of the following microcommand is represented as the AO, and for a single one, as

The generated address is again recorded on the first clock pulse through the switch 5 into the address register 2.

If the next micro-command is also a micro-command of a conditional branch, then the device functions in the same way.

If it is necessary to move to a new linear section of the microprogram in the format of the first microcommand of this section, a label M is set, which provides for the second clock pulse of zeroing the bits of the buffer register 4 and the bits of the logic conditions of the register 3 microcommands. The signal from the output of the element And 14 on the first clock pulse provides for reading in the register 2 addresses of the next microcommand.

The operation of the device is carried out further according to the algorithm described for the linear portion of the microprogram.

At the end of the work from the output 18.2 of the register of 3 micro-instructions, the zero input of the trigger 9 receives the signal “End of operation.

On this signal, the trigger is set to the zero position and stops the generator 8.

The proposed firmware control device provides a system for monitoring the implementation of the firmware. For this purpose, an output 19 of the device is provided, which is the output of the error signal. A “Error” error is generated if there is a label and no information is present in the field of logical conditions in the microcommand format.

(rig. 3

23 2

Claims (1)

A MICROPROGRAM CONTROL DEVICE, comprising a micro-read-only memory block, an address register and a micro-register, a multiplexer, a first address switch, a start trigger, a clock generator, the device start input being connected to a single start trigger input, the output of which is connected to the input of the clock generator, output the address register is connected to the address input of the micro-instruction read-only memory block, the first information output of which is connected to the first information input of the micro-instruction register d microoperations of the micro-command register is connected to the output of the micro-operations of the device, and the output of the micro-operation “End of work” is connected to the zero input of the start trigger, the output of the logical conditions of the micro-command register is connected to the control input of the multiplexer, the information input of which is connected to the input of the logical conditions of the device, the output of the first address switch is connected with the information input of the address register, characterized in that, in order to reduce the amount of equipment, a second address switch, a buffer reg istr, block of AND elements, first, second, and third elements AND, OR element, wherein the input of the device operation code is connected to the first information input of the first address switch, the first output of the clock generator is connected to the synchronization input of the address register, the second output of the clock generator connected to the synchronization input of the register of microcommands and the first input of the first element And, the output of which is connected to the synchronization input of the buffer register, the first and second outputs of the buffer register are connected to the first groups inputs of the first and second information inputs of the second switch addresses, whose output is connected with the first group of inputs of the second information input of the first switch address _from the second memory data output yannoy posto- 5S block of microinstructions connected to a data input of the buffer register, the direct input of the AND gates and the inputs of the OR element, the output of the block of AND elements is connected to the second information input of the micro command register, the output of the OR element is connected to the inverse input of the second And element and direct to the third element AND, the outputs of which are connected respectively to the device error output and the first control input of the second address switch, the logical conditions output of the micro-instruction read-only memory block is connected to the inverse inputs of the AND element block, to the direct inputs of the first and second AND elements and to the inverse input of the third element And, the multiplexer output is connected to the second control input of the second address switch, the outputs of the non-modifiable and modifiable parts of the micro-register register address are connected respectively with the second group of inputs of the second information input of the first address switch and the third information input of the second address switch, the microoperation output “End of command” of the micro-command register is connected to the direct and inverse control inputs of the first commutator of the address, the first and second groups of outputs of the modified part of the address of the micro-command register are connected to the second groups of inputs of the first and second information inputs of the second address switch, respectively.