SU1580360A1 - Multiprogram control device - Google Patents

Abstract

The invention relates to computing and can be used in control devices for discrete objects with a strong variation in the duration of individual microoperations. The purpose of the invention is to expand the field of application of the device. For this, the device contains a block of 1 memory of micro-instructions, a register of 2 addresses, a register of 3 micro-operations, a register of 4 masks, a trigger 5, a start, an adder7, a one-shot 8, blocks 9, 10, AND elements, OR elements 11, 12, delay elements 13,14 and element 15. The issue of the micro-operation code to the register 3 of the next microcommand from the microcommand memory block 1 is carried out upon receipt of 20 events at the input of at least one of the expected events. The control signal for issuing micro-operations of the next microcommand is formed using the one-shot 8, the block 10 of the AND elements and the OR 11 element in accordance with the mask from the mask register 4. The address of the next microcommand is formed using the block 9 of the elements AND and the adder 7 by analyzing the codes of the logical conditions from the input 19 of the device. The microcommand address is stored in address register 2, where it is loaded via address switch 6. Trigger trigger 5, the element And 15, the element OR 12 and the delay elements 13 and 14 provide control over the operation of the individual components of the device. 3 il.

Description

The invention relates to computing and can be used in control devices for discrete objects.

The purpose of the invention is to expand the field of application of the device by realizing the possibility of programmatically selecting an arbitrary set of micro-operation completion events and by realizing the possibility of arbitrarily selecting the initial micro-, manda from an external source.

Figure 1 shows the functional diagram of the device; figure 2 - format microcommand; FIG. 3 is an example of a timing diagram illustrating the operation of the device.

The microprogram control unit contains a block of 1 microinstructor memory with a 1-by-1 micro-opcode output, a 1.2 condition conditions output, an 1.3-output address and an 1/4-output event event mask, 2 address registers, a micro-ops register 3, a masking register 4, start trigger 5, 6 address switches , adder 7, one-shot 8, first 9 and second 10 blocks of AND elements, 11 and second 12 elements OR, first 13 and second 14 delay elements, AND 15 element, start input 16, forced stop input 17, operation code input 18, input 19 logic conditions, input 20 termination events and microoperation, yield 21 (micro code) "

Micro-operation field 22 (Figv2) includes a group of bits, which corresponds to output 1.1 of the code of micro-operations of memory block 1 to a micro-instruction

The micro-command field 23 includes the group of bits to which the output of the condition mask 3.2 corresponds. If the i-th discharge field is set to O (set to 1), condition X. does not participate (participates) in the formation of the address of the next micro-command

The micro-command field 24 includes a group of bits, which corresponds to the output 1.3 of the address and is intended to form the address of the next micro-command,

The field 25 micro-instructions includes a group of bits, which corresponds to the output 1.4 of the event mask. If the j-th bit of the field is set to O (set to 1), the occurrence signal S of the event does not cause (causes

five

0

0

five

0

five

0

five

issuing a micro-command code for microcommands on the device output.

In FIG. 3, the following designations are accepted: signal 26 at the input 16 of the start of the device signal 27 at the synchronous input of the address 2 register; signal 28 at the synchronous input of the register 4 of the mask signal 29 at the reset input of the register 4 of the mask} signal 30 at the input 20 of the device; signal 31 at the output of the element OR 11; the signal 32 at the output of the one-shot 8; signal 33 at the register microchip 3 synchronous input; the signal 34 at the output 21, the delay value Al of the first delaying element 13, the magnitude / delay of the second delaying element 14, t., t are the instants of the onset of events that are not masked by the micro-command field 25, the events that are masked by the micro-command field 25.

The micro-command memory block 1 is intended for storing micro-commands and has four outputs. Micro-operation signals are output from output 1.1, which are sent to information input of micro-register register 3. From output 1.2, a condition mask is read, in which 1 marked are checked, i.e. generating the address of the next microcommand condition, output 1.3 reads the code involved in generating the address of the next microcommand, output 1.4 reads the event mask, in which 1 marks the analyzed events, t, e those events, on arrival from the least one of which is considered microinstruction micro code is outputted to the output device 21

The address register 2 is designed to receive and store the addresses of micro-instructions from block 1 of the memory of micro-instructions. Information is received into the register when there is a signal at its sync input generated at the output of the OR 32 element. Register 3 of the micro ops is designed to receive, store and issue micro ops codes at the device output 21. Information is received into a register when a sync signal is present on its output generated by an element of AND 15 Mask Register 4 is used to store the code from 1.4 of the event mask of microcommand memory 1.

Trigger trigger 5 is designed to set the device operation mode — Operation mode and Forced stop mode.

The address switch 6 is designed to transmit to the information input of the register 2 the address of the incoming code either from the output of the adder 7 or from the input 18 of the operation code.

The adder 7 and the first block 9 of the elements And are designed to form the address of the next microcommand. The address of the next microcommand is formed as

BUT

SL

 A + H & M,

where a

X Mch

code coming from output 1.3 addresses;

condition code, coming from the input 19 of the logical conditions of the device;

code coming from the output

1.3 masks provided;

- bitwise operation - conjunction of codes.

If the conditions mask is all masked, i.e. X Od, 00, obviously, Tse, unconditional jump to the address coming from the output of 1.3 microcommand memory blocks is performed. Branching with an arbitrary topology is achieved by setting 23 microcommands in 1 bit field that meet the verifiable logical conditions .

The single-pulse single-pulse 8, the second block 10 of the AND elements and the first element OR 11 are designed to generate a control signal5 determining the moment of issuing the micro-operation code, to the output 21 of the device and receive the address of the next micro-command in the address register 2.

A control signal is issued at the output of the one-shot 8 at the time of arrival, at least one of the events marked 1 in the code coming from the output of register 4 of the mask. It is understood that the time of arrival of the event S. indicated by the signal in the jth resolution of input 20,

The element OR 12 is designed to combine the signals coming from the input 16 of the start of the device, or from the output element And 15,

five

0

five

0

five

0

five

0

five

The delay element 13 is designed for the delay of the control signal at the time of switching the address switch 6 and eliminating the states at the inputs of the address register 2. The delay element 14 is designed to delay the control signal at the time of receiving the address in the register 2 of the address and reading the microcommand from the microinstructor memory block 1, thereby eliminating the states on the inputs of the register 4 mask 0 The element 15 is designed to prohibit the passage of the control signal from the one-shot output 8 when forced to stop the device.

The device works as follows.

The device is intended for issuing control signals (micro-operations), and issuing the code of micro-operations of the next micro-command occurs when at least one of the events specified in the micro-command occurs.

In the initial state, the trigger 5 trigger, the micro-operation register 3, the mask register 4 are in the zero state. The circuit for resetting the circuit to the initial state is not shown conventionally.

When a signal is applied to the start-up input 16, the address switch 6 switches to the transmission of the code from the operation code input 18 to the information input of the address register 2. At the same time, the start-up triggers set the hour in a single state. The signal from the start input 16, the passage through the first delay element 13 and the second element OR 12 are fed to the synchronous input of the register 2 address and in the register 2 the address of the first microcommand is entered.

When the contents of the address register are changed, the reading process is started from the micro-instruction memory block 1 and the corresponding micro-command fields appear at its outputs 1.1-1-4. At the same time, the signal from the output of the element OR 12, the passage through the delay element 14, arrives at the synchronous input of the mask register 4, and register 25 registers the microcommand. 25 Signals from the register 4 output go to the corresponding inputs of the AND elements of the 10 AND block. element OR i can pass only signals from those input bits

20s which are marked 1 in the event mask field 25. At the same time, the field 22 of microoperations arrives at the information input of the register 3 microoperations, and poi 23 and 24, respectively, on the block 9 elements And and the adder 7, The block 9 elements And logically connects to the input of the adder only those bits of the input 19 logical conditions that are marked 1 in field 23 of the micro-command conditions mask. The device goes into standby mode when at least one of the events specified in the event mask field 25 occurs.

It is assumed that at some time point t, at least one of the expected events comes in. The signal from the corresponding bit of input 20, the passage through the corresponding AND element of the AND block 10 (another input of this element comes from the register 4 of the event mask is one) and through the first element OR 11 is fed to the input of the one-shot 8, which produces a pulse at its output, the pulse from the output of the one-shot 8 is fed to the reset input of the register 4 of the mask, setting it to zero. Thus, the block 10 of the AND elements logically disconnects the input 20 from the inputs of the OR I element, eliminating possible signal states during the transients of the block 1 of the memory of microcommands. At the same time, the pulse from the output of the one-shot 8 through the element I 15 is fed to the synchro clock of the register 3 micro-operations and the field 22 enters the field 22 micro-operations of the microcommand from the output 1.1 of the memory block. The same impulse through the element OR 12 arrives at the synchronous input of the regisr 2 address, in which the address A ,,,, the next micro-command is entered,

L / A

obtained through the switch 6 addresses from the output of the adder 7,

Changing the contents of register 2 of the address again starts the reading process from the micro-instruction memory block 1 and the corresponding fields of the next micro-command appear at its outputs. The pulse from the output of the delay element 14 records, in register 4 of the mask, the field 25 of the new microcommand and the unmasked bits of the input 20 logically and are connected to the inputs of the element OR 1 The device enters into the waiting mode at least one moment

ten

15

about 20

25

 1 803608

This is one of the events specified in field 25 of the event microcommand mask.

It is assumed that at time t2, the input 20 only received signals from masked events, i.e.

events marked in the event mask field 23 with the value / 0. Obviously, the corresponding elements AND block 0 of the elements AND also do not pass the signals of the events under consideration to the inputs of the element OR 11, therefore its output does not change and the device remains in standby mode.

If at the time t3 comes at least one of the expected events, the signal from the output of the element OR 11 restarts the one-shot 8 and t0D

Thus, the issuance of microcomoperations field 22 is carried out at the instants of time determined by the onset of the expected events.

A sign of the end of the microprogram is a microinstruction, in the field 25 of the event mask of which zeros are written. When sampling the specified microcommand and entering the field 25 into the register 4 of the mask, the event input 20 by the block 10 of the elements AND is logically disconnected from the element OR 11, i.e. none of the various events will be able to continue to run the one-shot 8.

The sampling process of microinstructions can also be interrupted in the forced order, by giving a signal to the forced stop input 17. In this case, the start trigger 5 is reset to the zero state, blocking the passage of the control signal from the output of the one-shot 8 through the AND 15 element to the 2 address register, to the micro-register 3 and to the mask register 4,

When generating the address A of the next microcommand, the following cases are possible: the implementation of linear sections of the microprogram without checking the logical conditions. In this case, zeroes are written in the condition mask field 23, i.e. Moo O ... QO, and in the address field 24 - the address A of the next micro-instruction. At the same time, the output of the adder is

35

40

45

50

ASL A

+ X d

mu

the implementation of unconditional jumps in the firmware, in this case, in the condition mask field 23, the zeros are written, and in the address field 24, the address

transition; realizations of branches with different configurations of checked logical conditions. In this case, in the field 23 of the condition masks, units are recorded in those bits whose corresponding conditions need to be checked. In the field 24 of the address, the address A of the microcommands is written, which must be executed if all the logical conditions to be verified are false For a given instinct of the logical conditions being checked x, x ,,, .. x, the address АРС (FOR, placement of microcommands on which branching must be performed, defined as

,-one

ik-i + ..., + 2 x

 A + 2

lk

For example, a microinstruction on which control must be transferred, provided that x 1 0 (false), x g 1 (true), he 1 (true), should be located at

Aro, 3m A + 2 A + 6,

ABOUT

+ 21. 1 + 2.

where A is the address where the microinstruction is located; it is executed if all the conditions x, yx, x are false

1 1 uh

Claims (1)

Invention Formula A microprogram control device containing a microinstructions memory block, micro-operations register, address register, adder, start trigger, two delay elements, one-shot, two OR elements, elements and two blocks of AND elements, with the device start input connected to the first start trigger installation input, the second installation input of which is connected to the forced stop input of the device, the output of which is connected to the output of the register of micro-operations, whose information input is connected to the output of the code of micro-operations 50 0 five 0 five 0 Q five memory, microinstructions, the output of the mask, the condition of which is connected to the first input of the first block of elements And, the second input of which is connected to the input of the logical conditions of the device, the output of the trigger trigger is connected to the first input of the element And, differing from the fact that, with the aim of paQ - the scope of application due to the realization of the possibility of a programmatic choice of an arbitrary set of events of the end of micro-operations and the possibility of an arbitrary choice of the initial microcommand from an external source; Holds the mask register and the address switch, the output of which is connected to the information input of the address register, the output of which is connected to the address input of the microcommand memory block, the output of the event mask of which is connected to the information input of the mask register, the output of which is connected to the first input of the second block of And elements, the second the input and outputs of which are connected respectively to the input of events of the end of the device micro-operations and the input of the first OR element, the output of which is connected to the reset input through the one-shot and the mask and the second input of the AND element, the output of which is connected to the synchronous input of the register of microoperations and the first input of the second OR element, the second input of which is connected to the output of the first delay element, whose input is connected to the control input of the address switch and the device start input, input of the operation code which is connected to the first information input of the address switch, the second information input of which is connected to the output by an adder, the first and second inputs of which are connected respectively to the output of the first block ale And the output of the microinstructions memory block address, the output of the second element OR is connected to the synchronous input of the address register, and through the second delay element to the synchronous input of the mask register. 2 Fi.Z