SU1019450A1 - Microprogram control device - Google Patents

Abstract

1. MIKROPROGRAMMNSE CONTROL, soperzhaschee block pas: m ti firmware vyhots which is connected to the first data register vhotsom mikrokomana unit check conditions, the first information which ahots soetsinen with vyhotsom transition trigger, which installation vhoa soetsinen yield the branch instruction decoder, an address register return, characterized in that, in order to reduce the equipment, it has an address counter, switchboard, return trigger, digital security (micro-operation factors, a sign of conditional transition, com teams of post-return operations and return commands, the output of the decoder of post-operation operations commands connected to the reset inputs of the transition and return triggers, the output of the latter connected to the second information block of the condition checker, the first and second outputs of which are connected to the counting and setting inputs of the address counter, the output of which is connected with the information input of the return address register and the address input of the return memory block and the address input of the microprogram memory whose output is connected to the first control input of the condition checker, to the first information input of the switch and to the input of the conditional jumper decoder, the output of which is connected to the BTOf, iM control input of the conditioner, and to the second information IROJSH1 register of microeromants, the first output of which is connected with information inputs of the ayshifratorsh transition commands, nocqeBoaapaiw operations commands, return commands and micro-operations, the second output — with the control inputs of the transition command decoders, post-return operations and microoperations, the output of the latter is connected to the operational output of the device, the output of the return command decoder is connected to the setup input of the return trigger and to the control input of the switch, the output of which is connected to the information input of the address counter, and the second information input is connected to the output of the address register return, the control input of which is connected to the output of the switch. The CO of the transition command, the third information input of the condition control unit is connected to the input of the device. 2. The device according to claim 1, characterized in that the precursor condition block comprises a switch and an element AND, the first, second and third information inputs of the block are connected respectively to the first, second and third information inputs of the switch, the output of which is connected to the first input of the element And, the second entrance of which

Description

with the second control input of the block, and the direct and inverse outputs with the second and first outputs of the block, respectively

official, first pack | The power supply terminal is connected with the control input of the switch.

The invention relates to automation and computer technology and can be used in specialized processes.

Known firmware devices. in control, the first register of the acres, the first block of memory, the first block of check, the second register of the address, the group of elements I, the second block of memory, the second unit of the check of conditions, and the recording of the device directly connected to the input of the first register and to the input of the record of the second register is connected through the AND element connected to the control and installation inputs of the device. The control input of the device sub-keys to the inputs of a group of elements I. In this device, the first and second blocks of memory work alternately, the outputs of which are connected to the output of the device, and the blocks of conditional signals alternately form signals for writing to the corresponding address registers. When a control signal arrives at

The installation input of the device element is locked and the new signal is not recorded in the second address register. The firmware is executed, and in the second address register, the value of the address at which the firmware is interrupted is saved. When the control signal arrives at the control input ycTpcdtcTBa, the address signal stored in the second address register goes through the group of elements And to the second memory block, and the firmware is resumed from where it was interrupted .l3.

A disadvantage of this device is that when interrupting a firmware version, the entire memory block is shut down, therefore it is impossible to organize. calling in such a device the interruption of the firmware and the transition to the implementation of its frequently occurring part of the standard micro subprogramme — stored in

the same memory block as the firmware, and the subsequent returns to firmware upgrade. This disadvantage necessitates repeated repetition of the standard parts in the microprogramme, which complicates the process of compiling and debugging the microprogram and increases the required memory capacity.

The closest to the proposed technical essence and the achieved result is the device containing the first memory block of the microprogram connected in a ring, the register of microinstructions and the address counter, the second input; which is connected to the operational input of the device through the block I, trigj "p and the decryptor, the output of the microinstructions register is the output of the device microoperations, and its other output is connected to the address modifier, the second input of which is connected to the address input of the device and the output is the address output of the device, which when connected to the second memory block of the microprogram, the output of which through the Condition Checker block is pushed to the input address register, and the second output to the operational input devices. In this case, the selection in the second memory block of the microprogram of the command for accessing the firmware control device is triggered by the descrambler and the trigger and the signal from the operation input of the device through the block of AND elements into the address register. At the same time, in the input address register, the address of the command in which the firmware control device is accessed is stored. Next, the microprogram control unit executes its microprogram by sequentially iterating through the microcommands of the first microprogram memory block and issuing it: to the micro command register, and at the end of the microprogram and micro command register, a signal is generated that turns off the acres motif. At the same time, the signal of the register of the address into the second memory block of the microprogram enters through the second address memory and the execution of the microprogram recorded in the second memory block continues from the point where it was interrupted by f 2. Thus, in a known device, it is possible to access from any place of the second memory block to firmware 1c recorded in the first memory block, which can be considered a standard microprogram, but it is impossible to access some part of the standard microprogram memory microscopic program, with subsequent return to the original place of the mass program. This necessitates repeated repetition of its standard parts in the firmware, which complicates the process of compiling and debugging the firmware and increases the required memory capacity. The essence of the invention is that when switching to standard micro subprograms from an arbitrary location of the microprogram, they record this place in the return address register and memorize the sign of transition to the standard micro subprogramme, into which standard micro subprograms analyze the transition sign and, if present, rewrite my content address counter register of the return address and remember the sign of the return from the standard micro-program; after returning to the original place, the microprograms analyze the sign of the return and when its presence erases both features and continues to generate firmware. The purpose of the invention is to reduce equipment. This goal is due to the fact that in MHKfiQnporpaMMHoe a control device contains a microprogram memory block whose output is connected to the first information input of the microcommand register, a condition checker, the first information input of which is connected to the output of the transition trigger, whose installation input connected to the output of the de-diffuser of the transition command, the return address register, entered the address changer, the switch, the return trigger, the micro-operations de-selectors, the sign of the conditional transition, the commands of the post-return operations and return commands, the output of the command decoder after return operations is connected to the cast inputs of the transition and return triggers, the output of the latter is connected to the second information input of the condition checker, the first and second outputs of which are connected respectively to the counting and installation inputs of the address counter, the output of which is connected to the information input the register of the return address and the address input of the firmware memory unit, the output of which is connected to the first control input of the conditioner, with the first information see the input of the switch and the input of the condition code transition decoder, the output of which is connected to the second control input of the condition checker and the second information input of the micro-command register, the first output of which is connected to the information inputs of the transition command decoder, post-return operations commands, return commands and micro-operations, the second output - with the control inputs of the decoders of the transition command, post-return operations and micro-operations, the output of the latter is connected to the operational output of the device , the output of the return command decoder is connected to the setup input of the return trigger and the control input of the switch, the output of which is connected to the information input of the address counter, and the second information input connected to the output of the return address register, the control input of which is connected to the output of the transition command decoder, the third The information input of the condition checker is connected to the input of the device. The unit, checking the conditions, contains a switch and an element, And, the first, second and third information outputs of the block are connected respectively to the first, second and third information inputs of the switch, the output of which is connected to the first input of the And element, the second input of which is connected to the second control input. the block, and the direct and inverse outputs — with the second and first outputs of the block, respectively; the first control input of the block is connected to the control input of the switch. The drawing shows a functional diagram of the device. The device contains condition block 1, trigger 2 trigger, trigger 3 trigger, decoder 4 signs of conditional jump, microprogramme memory block 5, address counter 6, switch 7, return address register 8, decoder command 9 perehoc, decoder Return control commands , register 11 micromash, 12 mshs oroshifrator, ceshifrator 13 teams of post-return operations. Unit 1 consists of a switch 14 and an electronic device And 15, the device operates as follows: The device is organized according to micro-tacts. In each microacade, an acrera formed in the address counter 6 is fed to microprocessor memory unit 5, from which the next microcommand code is selected, which is recorded in microcommand register 11, decoded by a decoder of 12 msh operations, which signals are sent to the device output. At the same time, the code signal of the next microcommand from the output of the microprogram memory block 5 goes to the decoder 4 signs of the conditional transition. If a conditional transition is encoded in the next micro-command code, then a signal is generated at the output of the decoder 4 that triggers the condition checking unit 1. The latter checks the condition, the HOKfep of which is encoded in the next microcommand and arrives at its input from block 5 of the microprogram memory, and the condition itself arrives at one of its three and formational inputs. If the condition is fulfilled, block 1 generates a signal arriving at the installation input of the address counter 6, to which the 1st records the conditional transition address encoded in the microcommand and fed to the address counter 6 and the microprogram memory block S via switch 7 located in its basic condition. Thus, a conditional transition is made. In case the condition being tested is not fulfilled or a regular condition command is not coded in the next microcommand, condition checker 1 generates a control signal at its second output that arrives at the counting input of the address b counter, in which the current address is added to the current address. The code signal of the next microcommand from the output of the register 11 also goes to the decoders 9, 10 and 13, moreover, if a conditional instruction is encoded (zhoaa, then the signal from the output of the decoder 4 through the second input of the register 11 microinstructions comes to its second move, prohibiting the inputs of the decoders 9, 12 and 13, preventing them from false triggering. If, in the next microcommand of the block 5 memory, the command for transition to the standard microsubprogram is coded, then the decoder 9 of the transition to the standard microprogram, the signal of which It enters the control input of register 8 of the return address and writes the current value of the address in counter 6 to it, and also enters the setup input of trigger 2 of the transition flag and sets it to the storage state of the transition. In the next cell of the microprogram memory 5 the microcommand of the conditional branch is coded depending on the state of the return trigger 3. Due to the fact that trigger 3 is in the initial state, a conditional branch is performed at the start address of the standard micro subprogram. In the subsequent microtates, a standard micro subprogram is executed, at the end of which a conditional jump instruction is coded by the condition of trigger 2 jumps. Due to the fact that the trigger 2 is set to the hrsgen mark in-mode of the transition sign, Byolne jumps to the return command. When a return command arrives in register 11 micro-commands, decoders 4 and 10 are triggered. With this signal from decoder U, switch 7 is transferred to the mode of signal return from register 8 of return address, trigger 3 is set to return sign storage mode, and unconditional transition is made to register address 8 After the transition to the command whose address is written in register 8, this command is repeated, and after it the command of the conditional retraction of the return trigger condition 3 is repeated. Due to the fact that the trigger 3 is set to xp “mode of the return sign, the rotary transition to the standard microprogram does not occur, and the device executes the command of post-return operations, when the decoder 13 is triggered to the micro-command register 11, the output signal of which sets the triggers 2 and 3 to the initial state. Next is the next part of the firmware. If the standard micro subprogramme is executed not after a peer hotspot from an arbitrary place of the microprogram, but in the order of its turn, then at its end when executing the conditional branch command according to the condition of the second trigger 2 transition, the latter appears in the initial state and therefore the go to the return command did not is:

Claims (2)

1. A microprogram control device, comprising a microprogram memory block, the output of which is connected to the first information input of the micro-command register, a condition checking block, the first information input of which is connected to the output of the transition trigger, the installation input of which is connected to the output of the transition command decoder, a return address register that differs the fact that, in order to reduce equipment, it contains an address counter, a switch, a return trigger, microoperation decoders, a conditional transition sign, last command evo-erate operations and return commands, the output of the decryptor instruction descrambler input being connected to the reset inputs of the transition and return triggers, the output of the latter connected to the second information input of the condition checking unit, the first and second outputs of which are connected respectively to the counting and setting inputs of the address counter, the output of which connected to the information input of the return address register and the address input of the return memory block and the address input of the microprogram memory block, the output of which is connected to the control input of the condition checking unit, with the first information input of the switch and with the input of the conditional sign decoder, the output of which is connected to the second control input of the condition checking unit and with the second * information input of the micro command register, the first output of which is connected to the information inputs of the transition command decoders , commands for post-return operations, commands for return and micro-operations, the second output - with control inputs of decoders of the transition command, post-e-operations and micro-operas of the latter, the output of the latter is connected to the operational output of the device, the output of the return command decoder is connected to the installation input of the return trigger and to the control input of the switch, the output of which is connected to the information input of the address counter, and the second information input is connected to the output of the return address register, whose control input is connected to the output of the transition command decoder, the third information input of the condition checking unit is connected to the input of the device. 2. The device pop. 1, characterized in that the condition checking unit comprises a switch and an And element, wherein the first, second and third information inputs of the block are connected respectively to the first, second and third information inputs of the switch, the output of which is connected to the first input of the And element, the second input of which SU. 1019450 is connected to the second control input of the block, and the direct and inverse outputs are connected to the second and first outputs of the block, respectively, the first control input of the block is connected to the control input of the switch.