SU496549A1 - Device for displaying information - Google Patents

Description

one

The invention relates to digital processing: ad-hoc technology, in particular to automaton, enterprise management systems. These and technological processes, which form various printed documents from the alphabetical and digital information days in the form of headings - the names of the production department, the date of the current time, etc.

; Known devices for. information output, containing sequentially connecting a block of analysis of calls connected to a block / sample, a block of permanent memory, a buffer register, a data register connected to a print control block connected to a print flea, an address register ,, I connected to the sample block and the buffer I register, the address decoder connected to the sample block, and the permanent memory block.

However, the inability to form a printed header of an arbitrary format and content reduces the value of ordinary documents and makes them difficult to read,. The purpose of the invention is to expand the functionality of the device, t, e; (25

Reception of any text of heading, any formats of heading and the document, operative replacement of one text (format) by another.

For this purpose, a character decoder, a delimiting register and j two elements AND are entered into the device, the ox decoder being connected to the address register, the permanent memory unit and the sampling unit; connected to the delimiter register,:. one output of which is connected with the code of the first AND element connected to the control unit — printing, the second one with the input of another AND element connected; Go to the print control block, and the second inputs of the elements And are connected to the block of permanent memory.

Fig, 1 shows the functional /; device layout; in fig. 2 is a block diagram of an algorithm for operating the device and FIG. 3 functional block diagram; constant na-J; m ti (BPP) ....

A device for outputting information consists of a control unit & control unit (BMU) 1 that generates a nocvi -J signaling not only for the output mode, but also for co-operation of the print control unit (OPS) 2 realizing coping with an external printing unit (PSU) 3, for example with an electrified typewriter. The BMU includes a unit for analyzing calls, an address register 5, a buffer register 6, a sampling unit 7, d & address cipher 8, character 9 decoder, data register 10, PPC 11, elements 12 and 13, dividing register 14. BUP consists of information register 15, data management block 16 and block 17 (service signals. On the bus 18; signals from the processor, bus 20 - control signals of the MBU, the code of alphanumeric characters (ATS) enters the BUP, at 21, the data code is transmitted through bus 22. The bus 23 is designed to output information signals to the print unit 3, and the bus 24 is for transmitting control signals from the printing unit 3 to the PCB. d of the block of analysis of calls 4 is connected to the input of the register of address 5, the output of which is connected to the input of the buffer register 6, and its output is connected to the input of the block of the analysis of calls 4. The output of the register of address 5 is also connected to the inputs of the decoder 8 and 9, whose outputs are connected to input runway 11. The output output of the control unit is connected to the input of block 4, and the code output is connected to the inputs of elements 1 and 13, the second inputs of which are connected to the outputs of register 14, and its installation input is connected to the output of the symbol decoder 9. The output of element 12 connected to the BUP, issues control is signals that implement uop in all modes including the mode and output a printed document. The output of the element 13 is connected to the input of the data management unit 16, and its output is connected to the input of the register information 15; the output of the latter is connected to the printing unit 3 by the threshold 3. The processing signal processing unit 17 is connected by bus 24 to the power supply unit 3. Bus 19 is connected to the input of the register Yu, through which data is received from the processor to the MBU; the output of register 10 is connected to the inputs of blocks 4 and 16. Sample block 7 is connected to the control & ng inputs of blocks 4, 5, 8 and 9. The control unit is AND elements whose output buses are connected to two groups of gates — address and code. Address gates determine the address code of the following microcommand., Code gates determine the control signals that are executable for this mic | omandy. In microcommands containing the same (parts of alphanumeric characters, the address part is missing. The total volume of the PPO must be equal to - the total number of microconservation in the PPO; fl. Is the total number of microcommands that implements all centralized control modes and output mode; / 1 - The total number of alphanumeric and service characters needed to implement the output mode. ADC address codes can be located in the buffer memory (part of the general operating memory) in a specific volume array with a known starting address. It works as follows: General firmware, determining the presence of the requirement to form the header AnZag - block 26 sets the initial address of the array with the addresses of the HeaderMzag header - block 26. By-: barely performing reads Thu - block 27 and analyzing the readiness of the external device AnVU - block is if the external device is unavailable - exit from the program, in case of readiness - analysis of the presence of the AnPO access character. block 29. If the cell is accessed for the first time, then the corresponding control signal Issue 1 is the block 30, the microcommand address containing the AUC code from register 10 is rewritten into register 5 through the access analysis block 4. The micro-command address obtained in this way is processed in the usual way: its address is decoded on the character decoder 9, the output of which sets the dividing register 14 to the one state, which allows the passing of the ACS code from the control panel through the element 13 and the data management unit 1b to the information register 15. Since the code read from the buffer memory nJDOHeccopa does not contain the address of the following command, then after executing the DA and 32 blocks (first access to the cell) or after executing blocks 31 and 33 (the second call to the cell) PARARB is performed - block 34 - the next microcoam is written; 1dy to the buffer register 6. SetP - block 32 and CBS - block 33 switch registers of access control registers to the cell from the ASC (in Fig. 1, these registers are not shown). After issuing the ATS code in the VyDSM PSU, unit 37 records the address of the MP command from register 6–16 register 5 via address analysis block 4 of the PBAA block 38. Block 39 analyzes whether the processing of the header array has completed or not. If the processing is not over, it is analyzed recognizes calls to the code on the U AnP register - block 35, if the code had one call - block 27 and then the entire sequence occurs; if there were two accesses, then + 1 NAV is performed — the Ze block — an increment of the buffer memory address counter by one, and then block 27, and so on. In the case of the end of the processing of the array of heads, the StirP is performed — a block 40 erasing features and exiting the program. From register 1O, data codes are transmitted to the PCB; in this case, the segment register 14 is in the zero state. | Prvdmet invention device for displaying information, | ) containing a serially connected call analysis unit connected to a selector unit, a permanent memory unit, a buffer register, a data register connected to the print control unit connected to the print unit, an address register connected to the sample box and the 6j ferric register , address decoder, iioz: key to the sampling unit, and the unit given by ti, is different from the fact that, O, to expand the functionality of the capabilities, it has a character decoder entered, separating the register to two elements | Ment And, and the decoder. character co | connected with the address register, the memory storage unit and the sampling unit, and Chen Chan to the dividing register, one you: the course of which is connected to the input of the first, And, connected to the printing block, the second - to the input of another And element, connected to the control unit Cgblock, and the second inputs of the elements And are connected to a block of permanent memory.

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Fig 2