GB1529644A - Data display system designed as a microcontroller - Google Patents

Abstract

1529644 Data processing BUNKER RAMO CORP 19 March 1976 [31 March 1975] 11220/76 Heading G4A A fixed address supplied to an address register E addresses the first word of a control table in a main memory 17 to derive the first half of the starting address of data for a first channel, which is transferred via an interface J, multiplexer D and address register E to a random access memory H; this is then repeated for all other channels. The above is repeated to derive the contents of the second, third and fourth words of each control table, which are, respectively, the second half of the data starting address and the first and second halves of an entry marker. The fifth word in each control table, which indicates the operation mode, is then addressed by address register E and written in a display channel data store M from which it is read to provide a mode character on the respective display. The contents of random access memory H as addressed by a channel address counter K are transferred via multiplexer D to address register E and status and device counters F, G, and the address of the entry marker from random access memory H is compared at I with the data starting address from address register E. If the inputs to comparator I are equal a multiplexer L passes to display channel data store M a fixed code to display a cursor. If the inputs to comparator I are not equal data from main memory 17 addressed by address register E is transferred via interface J and multiplexer L to the display channel data store M. The address register E then acts as a counter to access the subsequent data from main memory 17. This is carried out for each channel. Display channel data store M includes two registers for each channel. End of line and end of frame codes are detected by interface J. The system is controlled by microprograms stored in a programmable read-only memory C addressed by a status register A and a microstep counter B.