SU1118992A1 - Informaion exchange device - Google Patents

Abstract

A DEVICE FOR INFORMATION EXCHANGE, containing blocks of microprogram memory, microprogram control, transceiver, synchronization, shift registers, address registers and data, address decoders, command codes and direct memory access control, control register, and the microprogram control block contains the conditions multiplexer , the trigger of signs, the group of elements AND-OR, the register of the address of the micro-operation, with the first information input-output of the device connected to the first information input and output of the device address and data registers whose address output and address transceiver unit output form the device’s address output, address device whose input is connected to the address inputs of address decoders and command codes, and the second information output of the address and data register block is connected to the first information input of the block transceivers, the information output of which is connected to the second information input of the block of address and data registers, the first inputs of the AND-OR elements of the group of the microprogram control block and the first The information input of the shift register unit, the second information input of which is the second information input of the device, the identification record of the read / write identification of the device is connected to the control inputs of the decoder of the command codes, addresses and direct memory access control outputs, the first outputs of the decoders of the command codes and control pr My memory access is connected to the device readiness output, the first and second information outputs of the shift register unit are connected respectively to the second information output y and the second information input of the transceiver unit, the input and output of which are connected respectively with the first output and the trigger input of the microprogram control unit signs, the input (L of the strobe information of the address and data registers is connected to the second output of the command code decoder, the third output of which is connected to the second the inputs of the elements of the AND-OR group of the microprogram control unit, the outputs of which are connected to the information input of the register of the address of the micro-operations of the microprogrammed control unit The output of the microprogram memory unit is connected to the control input of the transceiver unit, to the control inputs of the condition multiplexer trigger. the sign and to the fourth inputs of the elements of the AND-OR group of the microprogram control unit and the information input of the control register, the output of which is connected to the identification output of the device's write-read, with the control the ling inputs of the blocks of the shift registers, address registers and data, with the control input of issuing commands of the decoder of command codes and with the second input

Description

Management Direct Access Memory Decoder, the second output of which is connected to the address resolution output addresses of the transceiver blocks and the address and data registers, the input device sign is connected to the information input of the conditions multiplexer of the firmware control block, the second output of the firmware memory block is connected to the gate input control register, the first output of the synchronization unit is connected to the synchronization inputs of the transceiver unit, the trigger of the feature and the address register of micro-operations the microprogram control, the second output of the synchronization block is connected to the sampling input of the microprogram memory, the fifth inputs of the AND-OR group are connected to the output of the multiplexer of the conditions of the microprogram control block, the output of the address decoder is connected to the address of the address of the decoder of the command codes, characterized by In order to increase the reliability of the device operation by making it possible to read the contents of the microprogram memory, a microprogram address decoder is inserted into the device, a read control lock, a data multiplexer, an input address switch, an output data switch, the read control block contains the And element and the access trigger, the input of the firmware address decoder is connected to the device’s address input, and the output is connected to the first input of the I control block of the read, the second input of which is connected to the identification entry of the read-write device, and the third input of the element I is connected to the output of the control register, the output of the element I is connected to the first input of the trigger reversed and connected to the control inputs of the input address switch and the output data switch, the output of which is connected to the first information output of the device, and the information input of the output data switch is connected to the information output of the data multiplexer, the information input of which is connected to the first output of the firmware memory block, and the control input data multiplexer is connected to the first output of the input address switch, the information input of which is connected to the address input of the device, and the second output the input address switch is connected to the address input of the microprogram memory block, the second access trigger input of the read control block is connected to the output of the device address decoder, and the output of the access trigger trigger of the read control block is connected to the microprocess control microprocessor address register and synchronization block inputs.

one

The invention relates to computing and can be applied, for example, in memory systems in the construction of controllers for controlling accumulators made on movable magnetic media, such as magnetic disks and magnetic tapes.

Advances in the development of modern integrated technology have led to the widespread use of BIS microprocessors and, accordingly, semiconductor BIS chargers for building controllers of external devices.

At the same time, the number of LSIs or EPROMs required for implementing the microprogram memory is often more than the number of microprocessor LSIs necessary for implementing the control and processing parts of the device, since the microprogram memory usually has a large size of stored microcommands. At the same time reliability

Such BIS memories are small, for example, BIS ROMs with electric programming tend to restore jumpers, and various BIS PROMs have a limited storage time when the power supply is turned off and a limited number of access cycles to the memory cells without destroying the recorded information.

All this requires periodic monitoring of the contents of the controller's firmware, which is an important factor in ensuring the reliability of the device.

A device for controlling a memory device on a magnetic disk with self-monitoring means is known, which contains information processing means, including a microprocessor (MP), memory and control blocks, an address and information bus with corresponding links 1.

The disadvantages of the known device are the inability to control the contents of the storage devices. For storing the control program microcodes, storing the instructions of the control system, as well as the storage device for storing the microcodes of the diagnostic programs, which are the least reliable because of the large number of LSIs.

A controller for flexible magnetic disk drives (prototype) is known, which contains a block of data registers and addresses, command codes, addresses, direct memory access control, a synchronization unit, a transceiver unit, a microprocessor control unit, a shift register unit, a microprogram block. memory, control register. connected by the appropriate connections 2.

The disadvantage of the known controller is its low reliability, due to the lack of control over the contents of the firmware.

The purpose of the invention is to increase the reliability of the operation of the device by making it possible to read the contents of the microprogram memory.

The goal is achieved by the fact that the device containing blocks of microprogram memory, microprogram control, transceiver, synchronization, shift registers, address registers and data, address decryptors, command codes and direct memory access control, control register, and the microprogram block control contains a conditions multiplexer, a trigger for signs, a group of AND-OR elements, a micro-operation address register, with the first information input-output of the device connected to the first information input and the output of the block of address registers and data, the address output of which and the address output of the transceiver unit form the address output of the device, the address input of which is connected to the address inputs of address descriptors and command codes, and the second information output of the block of address registers and data is connected to the first information input of the block transceivers, the information output of which is connected to the second information input of the block of address and data registers, the first inputs of the AND-OR elements of the microprogram control block group the first information input of the shift register block, the second information input of which is the second information input of the device, the identification entry and read identification of the device is connected to the control inputs of the decryptors of the command codes, addresses and direct memory access control outputs, the first outputs of the decryptors of the command and control codes direct memory access is connected to the device readiness output, the first and second information outputs of the block of shift registers are connected respectively to the second information output m apparatus and a second information input transceiving unit, input and output conditions of which are respectively connected to the first output and the input of flip-flop

About the signs of the firmware control block, the input of the gating of the information of the address registers and the data is connected to the second output of the command codes decryptor, the third output of which is connected to the second

g inputs of the AND-OR elements, a group of the microprogram control unit, the outputs of which are connected to the information input of the micro-operation control address register register, the output of which is connected to the third inputs of the AND-OR elements of the microprogram control unit and the address input of the microprogram memory, the first the output of the microprogram memory block is connected to the control input of the transceiver unit, to the control inputs of the conditions multiplexer, the trigger of the feature and to the fourth inputs of the AND-OR elements Rupp microprogram control unit and data input control register, whose output is connected to the output

0 identification of the device's read / write, with the control inputs of the blocks of the shift registers, the address and data registers, with the control input of the issuance of instructions by the descrambler of command codes and with the second input of the control of the descrammer

5 direct memory access, the second output of which is connected to the inputs of the resolution of issuing the address of the transceiver unit blocks and the address and data registers, the input of the device tag is connected to the information

Q input of the multiplexer of the conditions of the microprogram control unit, the second output of the microprogram memory block is connected to the input of the control register gating, the first output of the synchronization block is connected to the synchronization inputs

5 transceiver unit, trigger and microprocessor address register register of microprogram control unit, the second output of synchronization unit is connected to the gate input of microprogram memory block, fifth inputs of OR-group elements are connected to output of multiplexer of conditions of microprogrammed control unit, output of address address master is connected to address input command codes decryptor, address decipher entered

5 microprograms, read control block, data multiplexer, input address switch, output data switch, the read control block contains the And element and the access trigger, while the input of the microprogram address decoder is connected to the address input of the device, and the output is with the first input of the And block element read control, the second input of which is connected to the identification identification-read input of the device, and the third input of the AND element is connected to the output of the control register; the output of the AND element is connected to the first input the access trigger and is connected to the control inputs of the input address switch and the output data switch, the output of which is connected to the first information output of the device, and the information input of the output data switch is connected to the information output of the data multiplexer, the information input of which is connected to the first output of the microprogram memory, and the control input of the data multiplexer is connected to the first output of the input address switch, whose information input is connected to the address input of the device and the second output of the input address switch is connected to the address input of the microprogram memory block, the second input of the access control trigger of the read control block is connected to the output of the device address decoder, and the output of the control trigger of the read control block is connected to the microprocess control control block and block inputs sync.

FIG. 1 shows a diagram of the proposed device; in fig. 2 is a diagram of a firmware control unit; in fig. 3 is a flowchart of the operation of the device in the operating mode and in the mode of reading the contents of the microprogram memory.

The device contains a firmware address decryptor 1, a read control block 2, an input address switch 3, a data register and address block 4, an address decoder 5, a command code decoder 6, a direct memory access decoder 7, a synchronization block 8, data multiplexer 9 , transceiver unit 10, microprogram control unit 11, data output switch 12, shift register unit 13, control register 14, microprogram memory block 15. The read control block 2 comprises an AND element 16 and a call trigger 17.

The diagram (Fig. 1) indicates: 18 and 19-address and first information inputs-outputs of the device; 20-22-entries for identification of the read-write, the second information and the input feature of the device; 23-25 - outputs readiness device, the second information and identification

read-write device; 26-28 - the first, second and third inputs of the element And 16 block 2; 29-32 — control and information inputs and the first and second outputs of co. 5 mutator 3; 33-37 - control, first information, permission to issue addresses, gating information and the second information inputs of block 4; 38-40 The first information, second information and address outputs of block 4; 41 and 42 - address and control inputs of the decoder 5; 43-46 - address, command control, call and control inputs of the decryptor 6; 47-49 first, second and third exits of debris torus 6; 50-53 — control input, first and second outputs, second control input of the decoder 7; 54-56 - input lock, the first and second outputs of block 8; 57 and 58 control and information inputs of multiplexer 9; 59-64 — synchronization, address issuance control, first information, conditions, control, and second information inputs of block 10; 65-67 - information, conditions and address outputs of the block 10; 68-74 - entrances.

5 75 and 76 - outputs of block 11; 77 and 78 — Information and control inputs of the switch 12; 79-81 - the first and second information and directors JY inputs 82 and 83 - the first and second information outputs of the shift register 13; 84 and 85 0 information input and register strobe input 14; 86 and 87 - address input and sync input unit 15; 88 and 89, the first and second outputs of block 15.

Unit 11 contains the conditions multiplexer 90, trigger 91 signs, output 92, the group of elements AND-OR 93, register 94 addresses microcommand.

In the diagram (Fig. 2) are marked: 68-74 inputs, 75 and 76 - the outputs of the block 11; 95 and 96 information and control inputs

0 multiplexer 90; 97-99 - first, synchronization and control inputs of the trigger 91; 100-104 - the first, second, third, fourth and fifth inputs of the group of elements AND-OR 93, 105-107 - information, synchronization and input lock register 94.

The decoder 1 generates a signal to access the firmware memory when setting the address code code of the firmware memory to the address input 18 of the device 0.

Unit 2 provides the read mode of the firmware memory and controls the read cycle of its contents.

The switch 3 is intended for addressing the information read from block 15. 5 Block 4 is intended for organizing the exchange of information between the input-output 19 of the device and block 10, as well as issuing the low byte of the address to the output 18 of the device in the direct memory access mode.

The decoder 5 generates a signal to access the device when setting the device address code at input 18.

The decoder 6 generates the control signals with which the device performs I / O commands.

The decoder 7 generates memory access control signals in the direct access mode.

Block 8 synchronizes the work of other blocks of the device. When reading the contents of the firmware memory, block 8 blocks the signals at its outputs, which ensures the safety of information in the registers of blocks 10 and 11 and blocks the generation of control signals in register 14. Block 8 contains, for example, a generator and two elements I.

The multiplexer 9 is intended for multiplexing the bits of the micro-command code, since its width exceeds the input-output size 19 of the device.

Unit 10 is designed to receive, store and output digital information. It operates under the control of signals at input 63 and consists of a set of registers, multiplexers, a matching circuit (OR) to determine conditions (features).

Block 11 controls the selection of micro-instructions from block 15.

Switch 12 is designed to provide input-output 19 of a device read information from the microprogram memory.

Block 13 is designed to convert data formats when writing information to a drive and playing it.

Register 14 generates the control signals necessary for controlling other units of the device and setting the storage modes of operation.

The unit 15 is intended for storing and issuing the code of the addressed microcommand, as well as decoding under the control of the signal at the input 87 of its part.

The multiplexer 90 is designed to select and output to the input a group of elements AND-OR 93 signals from input 95.

The trigger 91 of signs is intended for receiving and temporarily storing condition signals from block 10.

The group of elements AND-OR 93 forms the control of the signals at the input 103 on the basis of the signals at the inputs 100- 102 and 104 of the address of the next microcommand.

Register 94 is designed to receive and temporarily store the microinstruction address code. Under the control of the signal at input 107, it turns off its output (turns into a high output impedance state).

The device works as follows. Address I / O 18 (0–15 bits of the address code), the first information I / O, 19 (JO-7 bits of the data code), input 20 and output 23 are used to send I / O commands, organizing direct memory access and reading the contents of the firmware memory.

For the operation of the device in the operating mode, a control information block (CID) is formed in advance in the memory of the system, in which information is stored, necessary for performing all operations: the operation code, the address of the information on the media,

The address of the memory with which the device exchanges when performing its operations.

The bytes of the PID are loaded into block 10 in the mode of direct memory access.

0 To load the bytes of the AIS, the device receives the full 16-bit address of the first byte of the AIS, i.e., it performs two output commands.

Getting the address of the first byte of the BUI,

The output of the device status, completion, and results of the operation is performed by input / output commands.

When setting I / O commands to input 18, a code arrives that determines

0 device address (3-7 bits) and command code (0 -2 bits), arriving respectively on decoders 5 and 6. Decoder 5 generates a signal to access the device, which, acting on decoder 6, enables code decryption

commands, and the act on the trigger 17 provides the operating mode of the device. The decoder 6, under the control of signals at its inputs (input 43, determines the command code, and 46, the command type (input or output) controls the exchange of information between input-output 19 and unit 4, and controls the starting address of the specified program microprogram.

Upon completion of the execution of an input or output command (controlled by a signal at input 44), the decoder 6 generates an end signal, which arrives at the output 23 of the device.

Access to the memory in direct access mode (both for receiving bytes of the ACID and data exchange recorded on the carrier or read from the carrier) is performed by the decoder 7, at input 53 of which signals are received that determine the moment of the start of the call and the type of write or read) to memory and on

5, the input 50 is the signals synchronizing the operation of the decoder 7 with the operation of the system memory during recording and reading in the memory. The decoder 7 determines the timing of the output of signals to output 23, the issuance of an address code to output 18, and also controls the exchange of information on input-output 19 with block 4.

After loading into block 10 through block 4 of the corresponding bytes of the CID, block 10 sets to the inputs 100 a group of elements AND-OR 93 of block 11 an operation code for determining the initial microprogram address for performing the specified operation.

When sampling the corresponding microcommand, the signals from the output 88 of the block 15 control the operation of the blocks 11 and 10, and using the signals from the outputs 88 and 89, the formation of the control signals of the register 14, the signals from the output of which are controlled by other blocks, and also used to set the modes drive (entering the output 25 of the device).

The device performs a specific set of operations, typical of which are write operations, read operations, and media formation.

For operations related to recording information on a carrier; information from block 4 (received in direct access mode) is fed through block 10 to input 79 of block 13, where it is converted into storage data format and fed to output 24 of the device.

When reading, the information from input 21 enters block 13, where, after conversion, is transmitted through block 10 to inputs 37 of block 4, and then to output 19 when implementing the direct memory access mode.

The synchronization of the operation of the device is carried out by the clock pulses produced by block 8, and the signals at input 56 are shifted in phase relative to the signals at input 55, which ensures decoding of reliable information in block 15.

To read the contents of the firmware memory, the processor of the system exposes the code address of the firmware memory to the input 18 of the device. In this case, the high-order bits of the address code are fed to the input of decipher 1, and are used to set the base address of the entire array of addresses in the firmware memory. The low bits of the address code from input 18 through switch 3 are used to address a word of readable information.

If there are signals at inputs 26 (base address of firmware memory 27 (memory read signal) and 28 (device is not in the state of recording information on the media), AND element 16 generates a signal that sets the trigger 17 to one and allows switching 3 and 12.

A trigger 17 blocks the operation of block 8, which ensures that information is stored in blocks 10 and 11 and blocks the generation of control signals from register 14. In addition, the signal from trigger 17 disables the outputs of register 94 of block 11.

After switching on the switch 3, the signals from input 18; the input to the input 86 of the block 15 controls the selection of the addressable microcommand, and the input to the input 57 of the multiplexer 9 controls the selection of the addressable byte of the microcommand word. The reading byte of the micro-command goes through the switch 13 to the output 19 of the device. After completion of the read cycle, the code of the address of the firmware memory is removed from input 18, as well as the corresponding signals from input 20. In this case, switches 3, 12 are blocked by AND 16.

Similarly, other bytes of firmware memory can be read.

The device is switched to operating mode by an input or output command. The signal from the output of the decoder 5 resets the trigger 17, which ensures the restoration of the operating mode of the device.

Content Information Received

0 of the microprogram memory block, may be subjected (for the purpose of control) to various processing, for example: printing (display); determination of the checksum and its comparison with the constant; comparison of the read information with the control

5 array, etc.

The contents of the firmware memory are read in the presence of an enable signal at input 28, the absence of which determines the mode of recording information on the media or the malfunction of some controller blocks, for example blocks 11 and 15, of register 14. A sign of this malfunction is to receive zero information when reading the contents of the firmware.

5 The technical and economic effect of the application of the present invention is to ensure the controllability of the microprogram memory and other blocks of the device (which increases the reliability of correct operation, reduces the likelihood of distortion of information on the media, reduces the search time and determining the nature of the malfunction).

63 71

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Claims (1)

DEVICE FOR INFORMATION EXCHANGE, containing blocks of microprogram memory, microprogram control, transceiver, synchronization, shift registers, address and data registers, address decoders, command codes and direct memory access control, control register, wherein the microprogram control block contains a condition multiplexer, a feature trigger , a group of AND-OR elements, a micro-operation address register, while the first information input-output of the device is connected to the first information input and output of the reg an address and data line, the address-output of which and the address output of the transceiver block form the address output of the device, the address · input of which is connected to the address inputs of address decoders and command codes, and the second information output of the address and data register block is connected to the first information input of the transceiver block the information output of which is connected to the second information input of the block of address and data registers, the first inputs of the AND — OR elements of the microprogram control unit and the first information the input of the shift register block, the second information input of which is the second information input of the device, the write-read identification of the device is connected to the control inputs of the decoders of command codes, addresses and direct memory access controls, the first outputs of decoders of command codes and direct memory access control connected to the readiness output of the device, the first and second information outputs of the shift register block are connected respectively to the second information output of the device and the second the information input of the transceiver unit, the input and output of the conditions of which are connected respectively to the first output and input of the trigger of signs of the firmware module, the input of gating information of the address and data registers is connected to the second output of the decoder of the command codes, the third output of which is connected to the second inputs of the AND — OR group elements microprogram control unit, the outputs of which are connected to the information input of the microoperation address register of the microprogram control unit, the output of which is connected with the third inputs of the AND — OR group elements of the microprogram control unit and with the address input of the microprogram memory block, the first output of the microprogram memory block is connected to the control input of the transceiver unit, to the control inputs of the condition multiplexer, sign trigger and to the fourth inputs of the AND — OR elements of the microprogram block control and information input of the control register, the output of which is connected to the identification output of the read-write device, with the control inputs of the blocks of the shift register , address and data registers, with the input for controlling the issuance of commands of the decoder of command codes and with the second input of the control of the decoder for direct access to memory, the second output of which is connected to the inputs for resolving the addresses of the transceiver blocks and the address and data registers, the input of the device attribute is connected to the information the input of the multiplexer of the conditions of the microprogram control block, the second output of the microprogram memory block is connected to the gating input of the control register, the first output of the synchronization block under it is connected to the synchronization inputs of the transceiver unit, the trigger of the attribute and the register of microoperation addresses of the microprogram control unit, the second output of the synchronization unit is connected to the gate input of the microprogram memory unit, the fifth inputs of the AND — OR groups are connected to the output of the multiplexer of the conditions of the microprogram control unit, the output of the address decoder is connected to the input of the address of the decoder command codes, characterized in that, in order to increase the reliability of the device by providing the possibility of counting As the contents of the microprogram memory are entered, a microprogram address decoder, a read control unit, a data multiplexer, an input address switch, an output data switch are introduced into the device, the read control unit contains an AND element and an access trigger, while the input of the micro program address decoder is connected to the address input of the device , and the output is with the first input of the AND element of the reading control unit, the second input of which is connected to the identification input of the read-write device, and the third input of the And element connected to the output of the control register, the output of the AND element is connected to the first input of the access trigger and connected to the control inputs of the input address switch and output data switch, the output of which is connected to the first information output of the device, and the information input of the output data switch is connected to the information output of the data multiplexer, the information input of which is connected to the first output of the firmware block, and the control input of the data multiplexer is connected to the first output of the input comm an address tator, the information input of which is connected to the address input of the device, and the second output of the address input switch is connected to the address input of the microprogram memory block, the second input of the read trigger of the readout control unit is connected to the output of the device address decoder, and the output of the readout trigger of the readout control unit is connected to the inputs locking the address register of microoperations of the microprogram control unit and the synchronization unit.