GB1525862A - Microprogramme-interrupted computer - Google Patents

Abstract

1525862 Computer systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 4 Sept 1975 [7 Sept 1974] 36453/75 Heading G4A A computer system (Fig. 1) comprises a power supply unit SC and peripheral apparatus TA, MB connected by individual signalling lines DRE1, DRE2, DRE3 and a switch unit SA to the execution unit of a central processing unit CPU also including a non-volatile processing store MEM for macroinstructions connected to programme counter MPZ (pulsed from a clock TG) of a microprogramme store MPS. The switch unit SA is under the control of the execution unit. A priority sequence for the units SV, TA, TB exists with unit SV having highest priority and peripheral apparatus with little or no buffer capacity having next higher priority. As described the peripheral units are a keyboard TA and magnetic tape unit MB but they may include for example a printer, display, card reader and back-up store. Data is transmitted to and from the unit via switch S and bidirectional line DD. All microprogrammes include a section for interrogating the signal lines DRE1, DRE2, DRE3, there being predetermined maximum time durations between successive connections of each line to the execution unit to prevent loss of information. If a mioroprogramme (which may itself have been interrupted) is interrupted by a signal existing on one of the lines DRE, after the interrupt microprogramme has been completed, further execution of interrupted microprogrammes is carried out in order of priority. Initially at switch on of the power supply the programme counter is set to a predetermined address and pulsed by clock TG so that information stored in store MPS relating to peripheral apparatus is transferred to predetermined addresses in the store MEM. Next a test programme is performed to test the data paths, registers, ALU and core store. Line DRE1 is then interrogated to determine whether a signal from circuit AS exists indicating that a voltage monitoring unit U has detected an error in at least one of the generated direct voltages. If the signal exists a "terminate" microprogramme is fetched which marks instructions in the store MEM which have not yet been completed so that they might be executed when the computer is restarted. A microprogramme loop is then cyclically completed until the voltage is such that the clock pulse generator TG stops. This prevents any functions being incorrectly operated. Storage capacitors ensure that an adequate voltage exists long enough to perform these steps. During normal operation all the units are interrogated sequentially. At switch off of switch SS during interrogation of the lines the signal on line DRE1 results in the state of this switch being subsequently transmitted to the control unit to initiate an appropriate microprogramme section.