CA1063248A - Microprogram-interrupted computer - Google Patents

Abstract

ABSTRACT:
The invention relates to a computer wherein all peripheral apparatus are connected, via a signal-ling line, to a switching unit in the central processor.
Each microprogram comprises one or more sections in predetermined locations so as to control the inter-rogation of one or more of the signalling lines. The information of a signal thus interrogated may control a jump operation in the program. Interruptions in the program can thus occur exclusively at predetermined points. When a plurality of the said signalling lines are simultaneously active, the execution of a micro-program concerning a first peripheral apparatus can be interrupted by a microprogram concerning a second peripheral apparatus, and so on. When a microprogram is terminated, further interrupted microprograms are further completed, possibly in a sequence correspond-ing to the priority of the peripheral apparatus. The device for the power supply which can be switched on and off operates also as a peripheral apparatus, by means of a voltage detector, and has the highest priority.

Description

~063248 The invention relates to a computer configuration, comprising a central control unit which includes a processor store which sustains the information of macro-instructions stored therein in the case of a breakdown of the supply voltage, a microprogram counter having an input which is con-nected to a data output of the processor store and an output which is con-nected to an address input of a microprogram store, an input of the micro-program counter being connected to an output of a counting pulse generator so as to activate each time a predetermined series Or address positions of the address positions of the microprogram store, the central control unit furthermore including an execution device which is connected to the micro-program store, the processor store and external connection lines, the com-puter configuration furthermore comprising a po~er supply apparatus and at least one peripheral apparatus, all the said further apparatus being con-nected to the said external connection lines via data lines.
The processor store of such computers contains the program written by a programmer, that is to say the program translated from a symbolic pro-gramming language such as COBOL or FORTRAN in the form of a sequence of individual machine instructions. Herein, this is to be understood to be the macroprogram. Every or almost every macroinstruction of the macroporgram fetches a sequence of micro-instructions from the microprogram store which control the process for the sometimes very complex execution of the com-puter instruction. Computer instructions of this kind may concern, for example, arithmetical operations, or they can initiate the activation of an input or output apparatus for the transfer of, for example, a data block.
Notably the construction of input and output apparatus determines the speed of the data transfer, which may be substantially lower than that at which the central control unit can take up or output the data. In many cases this can also be due to the mechanical inertia inherent of the construction of many kinds of peripheral apparatus. $herefore, the program is usually composed such that bet~een the transfer of the individual data units the central con-trol unit performs other functions, for example, arithmetical operations or data exchanges with further input/output apparatus, so that the data transfer is effected in a time-multiplex organisation. It is difficult to perform the sequences of operations thus divided in the time such that loss of information occurrence of faults are definitely precluded.
According to the invention, a computer is realized wberein the sequences of micro-instructions to be executed per function can each time be readily interrupted without special, time-consuming and complex steps, such as the protection of data, being required for an interruption and without _ information being lost or faults occurring, also if the said protection of information is not effected. ~his is reali2ed according to the invention in that all the said external connection lines include a switch having an open position and a closed position which can be selectively controlled exclusively by a signal from the said execution device, under the control of the data of at least one address position of each feasible series of the said predetermined series of address positions of the microprogram store the said execution device being capable of generating a series of at least one closing command signal, a closing command signal being capable of each time selectively setting one of the said switches in an external connection line which is connected to a si galling line of the said further apparatus to the closed position so as to make the switch conduct an interrupt si g al then present to the execution device, the said interrupt signal being capable of controlling, with the exclusion of all other data si B als then generated by the said further apparatus, an address signal for the processing store.
Because an interrupt is always controlled by the nicroprogram itself at special relevant instants, these instants can be chosen within the set-up of the microprogram such that this execution can be interrupted without risk, without data protection being necessary. The interruption preferably takes place at instants at which no intermediate results are present in registers, or at instQnts at which such intermediate results are already automatically protected. By a suitable set-up of the microprograms or by suitable spacing of the parts controlling the interrogation, it can be achieved that the time intervals between two successive interrogation operations do not exceed a maximum value. It is thus ensured that each input/output apparatus is interrogated st least once within a given interval. Consequently, notably the loss of input information is avoided. For the interrogation of the individual peripheral apparatus priority control can be provided, it being efficient for the current supply to have the highest priority in the manner yet to be described. It was found that an interval of 1/2 ms for the said maximum time is sufficient in many cases, both for comparatively fast peripheral apparatus for input/output and for signalling a forthcoming breakdown of the voltage. For very fast systems the said interval can be chosen to be shorter; for comparatively slow systems, it may be longer.
Each microprogram execution which controls a data transfer also comprises sections uhich control interrogation operations, as will be explained hereinafter. For example, a plurality of input/output apparatus can be simultaneously operated in accordance with a time multiplex system.
In the case of a plurality of simultaneously actuated apparatus, a plurality of interrupted microprogram executions can arise, i.e. if a first micro-program execution is interrupted by a second, and the latter in its turn is interrupted by a third. ~his is readily possible because each microprogram execution comprises sections during which peripheral apparatus are inter-rogated, the said interrogation being effected independent of the fact uhether the microprogram execution itself was started by an interruption due to an interrogation operation. If the execution of a microporgram has been terminated and no interruption signal is detected on any of the signal lines during interrogation, the previously interrupted microprogram executions are further completed, preferably in accordance with a predetermined priority which may correspond to the priority of the peripheral apparatus. It is only after the completion of all current or interrupted microprograms for peripheral apparatus, that the microprograms which relate only to the central control unit, for example, arithmetical functions, are further executed.
For the switching on and off of the computer, i.e. of the power supply apparatus, further advantageous applications of the idea of the inven-tion are possible. When the computer is switched on, the microprogram counter is set to a predetermined starting address so as to start a pre-determined microprogram. Under the control of the microprogram counter, given basic data for other microprogram executions are then written into the processor store. Finally, the first microprogram terminates in a loop, so that only the interruption signals of the keyboard are interrogated. As will be explained hereinafter, the normal execution of the processor program can be started only by actuation of a given key. For example, by the actua-tion of a ~irst key a program is written in, whilst by the actuation of a second key a program already present in the processor store is ~urther com-pleted~ During the execution of the microprogram, at the beginning thereof only the power supply apparatus is interrogated; in this case this apparatus is treated as a peripheral apparatus, thst is to say the power supply appa-ratus is interrogated so as to check for a possibly forthcoming excessive decrease of the supply voltage. This interrogation is necessary because in the case of a fault in the supply voltage it may occur that the normal execu-tion of the microprogram cannot be terminated without error. The described interrogation is also effected during the execution of all subsequent micro-programs. If it is signalled that an excessive voltage decrease is forth-coming, an other microprogram is executed which terminates in a loop withoutinterrogation operations, because the microprogram counter cannot be stopped.
This will be explained hereinafter. In this manner no incorrect functions can be executed when the final decrease of the voltage occurs.
When the computer is switched off by means of the main switch~ the power supply is preferably not immediately switched off; the on/off position Or the main switch should rather be processed as the status of a peripheral apparatus which, possibly in combination with other conditions, starts a switch-off microprogram, so that information is applied t.o the power supply unit, after which this unit is switched off. Because of the subsequent signalling of the decreasing of the voltage, an automatic ~ump follows to the execution of a ~icroprogram which terminates in a loop without inter-rogation. An example of the above other conditions is formed by a datacommunication transfer from a remote location which is still expected when the operator has already left the computer. The key switch can then already be switched off, but the computer switches itsel~ off completely only after the said transfer has taken place.
The invention will be described in detail hereinafter with refer-ence to some figures. Figure 1 shows a block diagram of a computer con-figuration according to the invention. Figure 2 shows a first flow diagram.
Figure 3 shows a second flow diagram. Figure ~ shows a third flow diagram.
Figure 1 shows a computer configuration according to the invention.
The central control unit CPU is connected, via a line DD, to a number of further apparatus. The line DD is shown to be singular for the sake of simplicitr, but actually comprises a rather large number of individual lines for the parallel transfer of data signals and control signals. The Figure shows only three further apparatus, i.e. the power supply apparatus SV for supplying the working voltage BU for the central control unit CPU, a key-board TA with a full alphanumerical keyboard, a number of function keys, and special keys whereof only the keys RU~ and READ areshown for the sake of simplicity, and a magnetic tape apparatus MB. These apparatus are connected in parallel to the line DD, in parallel to further peripheral apparatus not shown, for example, a printer, a display apparatus, a card reader, a back-ground store or a telephone line. Furthermore, each of the apparatus is con-nected to the central control unit CPU via its own signalling line DREl,2.... If a peripheral apparatus wishes to request a data transfer it dis-patches a signal on the relevant signalling line in the to the central control unit CPU. The signalling lines can transport information in a single direction. This is not an ob~ectionable restriction, because most of the individual lines in the line DD, notably the lines for the actual data transfer, can donduct data in both directions. All data lines originating from the further apparatus terminate in the central control unit CPU in a switch of the switching unit S or in one of the switches SA. These switches are actuated by the central control unit CPU itself, notably via the con-nections denoted by broken lines; they are controlled by the microprogramcontrol unit MPS which contains the microprogram store such that none of the signals originating from the exterior can directly act on the central control unit without corresponding control by the execution of the microprogram. The switching unit S consists of a number of separate switches, i.e. in principle one switch for each parallel line of the cable DD. Generally, these switches are simultaneously connected to the central unit CPU by the microprogram control unit MPS. For given peripheral apparatus, or statuses of peripheral apparatus, it may be efficient to connect only one or a few lines so as to detect the said statuses on the basis of the signals on these lines. The said switches as well as the interrogation switch SA are suitably constructed as electronic switches. The central control unit CPU essentially comprises the said microprogram control unit MPS which contains a microprogram store which is addressed by the microprogram counter, and a processor store MEM
which is constructed, for example, as a known ~agnetic core store. Also an arithmetic and logic unit (ALU) is required for the execution of the normal operations, and a number of registers whicb can operate, for example, as counters and which can be individually addressed. These further elements are commonly used. An output device of this kind, not shown for the sake of simplicity, receives data from the microprogram counter, from the processor store, and from the externally connected apparatus, and dispatches data to the processor store and to externally connected apparatus.
The processor store MEM contains the program which is to be execut-ed by the computer and which contains a series of computer instructions.
These instructions are input externally, i.e. from the magnetic tape appa-ratus MB via the cable DD and switching unit S~ or are obtained by the com-puter itself by conversion of a program written in a symbolic language, for example, COBOL or FORTRAN. Each computer instruction generally fetches a number of micro-instructions in succession which are stored in the micro-program store of the microprogram control unit MPS. Reference should be made to Canadian patent application 233,795 filed August 20, 1975 in the name of Applicant for a more detailed description. In the case of a computer instruc-tion which controls, for example, the input or output of data, it must be checked whether the addressed peripheral apparatus is operational, whether breakdown signals are present, etc. This can be effected as follows. First a command signal is applied to the peripheral apparatus via the switching unit S so as to interrogate a number of indication flip-flops (not shown for the sake of simplicity) in the relevant peripheral apparatus. Subsequently, the relevant status information is returned to the central control unit CPU
via the switching unit S. The data transferred constitute an address or address portion for the processor store and thus controls the ~ump to given proerams, for example, a program controlling the data transfer. In the case of inadmissibility of this transfer, for example, because of an error situa-tion, first a printing program can be applied to a printing device (not shown in Figure 1) so as to print a corresponding information, and subse-quently an other program can be continued. For many peripheral apparatus the transmission speed of the data is much lower than the processing speed in the central control unit. Therefore, often two or more peripheral appa-ratus are simultaneously addressed, the data transfer between the central control unit and the peripheral apparatus being controlled in a time multi-plex manner.
Each execution o~ a microprogram comprises sections, i.e. individ-ual microprogram steps, which control the interrogation of signals on the signalling lines DRE 1, 2 ... from the peripheral apparatus to the inter-rogation switch SA. The sequence in which the said signalling lines areinterrogated is given by a predetermined priority sequence, with the result that in the case of simultaneous appearance of signals from a plurality of peripheral apparatus, an individual treatment in time thereof occurs. The line DRE 1 of the power supply apparatus SV has the highest priority, because a forthcoming breakdown of the working voltage is more important than an arbitrary request signal from an other peripheral apparatus. A given com-puter instruction can control, for example, a data exchange with a given peripheral apparatus. I~ a microprogram function is then directly fetched which transfers a data signal concerning the status of the peripheral appa-ratus to the microprogram control unit via the cable DD and the switchingunit S and which decodes the signal at this location, a signal from an other peripheral apparatus can arrive on the relevant signal line during the de-coding, because the said other peripheral apparatus had already been started for transferring a number of data characters, for example, as is common practice for a punched card reader. However, peripheral apparatus of this kind often have no or only little data buffer capacity; in any case the data capacity is much smaller than necessary to be transferred for one instruc-tion. Therefore, data then applied in the form of one or more characters must be directly processed by the central control unit CPU, i.e. it should be written into the processor store MEM before the punched card reader reads the next punched column, so that the data of the preceding column would be lost.
Therefore, all microprogram executions comprise a section, for example, a micro-instruction, which controls the interrogation of the signal lines DRE
1, 2 ... originating from the further apparatus (SV, TA, MB). In the case of short executions of microprogram sections, this section can be suitably included at the end thereof; in the case of long executions, it may possibly be necessary to effect the interrogation at a plurality of locations (i.e.
instants) thereof; in that case the maximum time interval between two suc-cessive interrogation operations should not be larger than the time within which a character to be transported, for example, has to be processed or out-put. A value of 1/2 ms has already been mentioned for this time interval.
If an interrupt signal from a peripheral apparatus is detected during such a prolonged execution, during interrogation which need not always take place at the end of the said execution but also, for example, halfway the execution, the execution of the current microprogram section is in any case interrupted and an other microprogram execution is fetched, the identity thereof being determined by the information as regards which signalling line carries an interrupt signal. The interrogation of the lines is effected in accordance with a predetermined priority sequence. Peripheral apparatus without buffer capacity or with a buffer capacity for only a few data char-acters then have a higher priority than peripheral apparatus having a buffer capacity for a comparatively large number of data characters, the latter apparatus often being suitable for transferrine information in the form of a complete information block which is then temporarily stored, for example, in its entirety in the in~ormation bufrer. The execution Or this second microprogram (having interrupted the first execution) can also have a com-paratively long duration, so that therein the signal lines DRE 1, 2 ... are also interrogated. Therefore, this second execution can be interrupted for the same reasons as the first execution. In this manner, ultimately a number of executions of microprograms can be interrupted, until finally an execution is completed because no further interrupt signals are detected during the said interrogation. After the said completion, an interrupted microprogram is automatically further completed. If there are a plurality of interrupted microprograms, they can be com~leted after restarting in accordance with a predetermined priority sequence~ Microprograms relating to a peripheral apparatus preferably have the highest priority, in accordance with the priority Or the said peripheral apparatus as regards the said interrogation.
The interrupted executions of microprograms are thus seccessively completed, as long as no signal is detected on the signal lines DRE 1, 2... during the interrogation thereof. During the further execution Or interrupted micro-program sections, the interrogation operations are performed in exactly the same manner as for program sections executed without interruption.
It is only arter all microprogram sections relating to peripheral apparatus have been completed that any further interrupted microprogram sections, such as the formation of arithmetical functions (~or exa~ple, a multiplication) are completed. It is only after no further interrupted microprogram sections are present that the next machine instruction is addressed in the processor store so as to continue the computer program.
For example, a punched card reader can have a comparatively high priority, a magnetic disc store (having a comparatively large information bu~fer) can have a comparatively low priority, and a microprogram execution for internal processing in the unit CPU can have a very low priority. The first micro-program has a very short duration, so it will not be interrupted; the second microprogram has a longer duration (for example, 2 ms), and the latter program may have an arbitrary long duration.
When the installation is first switched on, no program is executed _ g _ for the time being, so also no microprogram activated thereby will be executed, so that initially no interrogation operation can take place. Be-cause external access to the central control unit CPU can be achieved only by means of an interrogation operation by the computer itself, the computer is put into operation as follows. When the power supply is switched on (see hereinafter), the microprogram counter is set to a predetermined starting address. The microprogram counter then continuously receives clock counting pulses from the clock pulse generator TG which have a fixed, uninterruptable frequency~ As a result, the execution of the microprogram beginning at the relevant starting address is automaticall~ started. Under the control of this specific microprogram, given data which are non-destructively stored in the microprogram store for given steps o~ microprograms relating to periph-eral apparatus are written into predetermined address locations of the pro-cessor store MEM. These data indicate, for example, whether the relevant peripheral apparatus is suitable for transferring data per character or in blocks, and further give information as to how the status information re-turned at the beginning of a transfer is to be processed, notably if an error situation is indicated etc. Information of this kind is necessary as con-ditions for executing sections of microprograms relating to the relevant peripheral apparatus, for example, to indicate the possibility of continua-tion of a microprogram. They are written into the processor store so as to achieve that, also when a processor store is put into operation, for example, after a repair so that the processing store can have a random, unknown data contents, the entire installation is ready for use without special steps being required. Prior to that or after that, a microprogram section can be executed for the automatic testing of given sections of the installation.
According to the test program, first the data paths are tested, followed by the registers, the arithmetic and logic unit, and finally the core store;
it is notably checked that all addresses are correctly written and read.
When the microprogram section started at the starting address has been automatically executed, at the end thereof an instruction is present for each time cyclically interrogating the signal lines of the peripheral apparatus. The installation can then be externally controlled, for example, in that a starting command is given in a manner yet to be described.
In order to obtain an unambiguous starting condition, for example, at the end of the first, automatically completed microprogram section only the keyboard is interrogated. In the case of a newly delivered computer or processing store, in any case first a program must be stored which is already present, for example, on the tape of the magnetic tape apparatus MB. The operator then first presses the button RD which causes the keyboard decoder TE in the keyboard TA to generate a signal on the line DRE~2 (generally, the depression of an arbitrary, for example, an alphanumerical key of the key-board produces a signal on the line DRE2, the identity information being transferred on the cable DD and processed under the control of the unit CPU).
If the said signal is detected during the interrogation of the lines DREl,

2 ..., a microprogram section is fetched which transfers the status of the keyboard TA, in this case the fact that the button RD is depressed, to the microprogram control unit MPS via the line DD and the switching unit S. In the microprogram control unit MPS, this information is used to fetch a fur-ther microprogram section which initiates the data transfer from the magnetic tape apparatus MB. During the reading of the program from the magnetic tape apparatus MB into the processor store MEM, the lines DREl, 2... need not be interroeated, because in as far as this magnetic tape apparatus MB serves only for reading in programs, no peripheral apparatus can be activated.
There is only one exception to this rule which will be described hereinafter.
Generally, very soon after the switching on of the device the waiting loop occurs wherein the keyboard is interrogated, because the starting test pro-gram has only a brief duration, for example, 0.1 s. When the button RD is operated, the installation returns to this loop after the reading of the magnetic tape cassette, so that a plurality of cassettes can be read, if desired. The said loop is ultimately left only after the depression of the button RN, and further peripheral apparatus can be put into operation only after that.

Interrogation takes place only at the end of the said writing of the program, i.e. only the signal line DRE2 Or the keyboard TA is inter-rogated. The operator then has to press the button RN ("execute program"), after which the status information of the keyboard TA is again transferred to the microprogram control unit so as to be decoded. The decoding controls the reading of a predetermined address of the processor store NEM, and the contents Or the said storage location are used as the address Or the storage cell which contains the first computer instruction to be executed. The nor-mal execution of the program then starts.
The power supply unit SV provides the power supply for the central control unit CPU. The line UN is connected to a normal outlet socket Or the supply mains. When the mains switch SN is closed, a variety Or direct volt-ages are derived from the mains supply voltage by means Or the symbolically denoted rectifier GL, the said voltages possibly being controlled and being applied to the central control unit CPU via the multi-core line UB. Further-more, the generated direct voltages are applied to a voltage monitoring unit U which supplies an alarm signal if at least one of the direct voltages decreases below a predetermined value. These various values have been chosen such that they are passed only in the case of a serious defect in the rec-tifier unit or in the case of breakdown of the mains. The alarm signal con-trols the circuit AS so as to supply a signal on the line DREl. This is theonly line which is also interrogated by the central control unit CPU during the microprogram section executed immediately after the switching on of the computer. This is because, even if no further peripheral apparatus can have become active, the voltage can have become too low. In the case of a further decrease, after some time a regular operation of the computer is no longer ensured. Therefore, if the central control unit CPU detects, during the interrogation of the status information (i.e. the voltage information) of the power supply apparatus, that an excessive voltage decrease is forth-coming, a specific "termination" or "conclusion" microprogram section is fetched which provides the macro-instructions or computer instructions in the processor store which relate to peripheral apparatus and which have not yet been completed, with a special marking information, for example, by storing a "1" bit in a location of the processor store reserved for therelevant peripheral apparatus. Subsequently, a ~ump is initiated to a microprogram loop wherein the signal lines are no longer interrogated. This microprogram loop is then cyclically completed until the voltage on the line BU has decreased so far that the clock pulse generator for the microprogram counter stops to operate. In this manner no further functions are executed in the period of time expiring before the voltage has definitely become too low. As a result, no incorrect functions can be executed because of incor-rect operation of specific parts of the computer at an excessively low work-ing voltage. The sections of the microprograms controlling the interrogationof the signal lines thus partly do not interrogate all lines, but in given microprogram sections only the voltage supply and the keyboard are inter-rogated. The voltage supply always has the highest priority. In the case of an instantaneous breakdown of the mains, special storage capacitors (not shown in the figure for the saXe of simplicity) in the power supply apparatus SV ensure that an adequate voltage is supplied for 1 to 2 ms to ensure that the computer remains operational. This time is longer than the said l/2 ms, so that after the interrogation time is left (at least approximately l/2.ms) for executing a few program steps. The computer can be driven into the ter-mination loop also in the case of an excessively high supply voltage.
Special conditions are also applicable during the switching off ofthe computer, because the microprogram counter cannot be stopped. The key switch SS acts as a main switch for the computer and directly switches on the mains switch SN via the command decoder BE. ~he immediately subsequent operations have been described above. When the key switch SS is switched off, the "off" position, however, acts only as a special status of the power supply apparatus SV which generates a signal on the signal line DREl via the circuit AS. If this signal is detected by the central control unit CPU
during the interrogation, the position of the key switch SS, decoded in the command decoder BE, is applied to the microprogram control unit MPS and is decoded therein. Depending on the programming, a microprogram section can be started which first transfers an information to the power supply apparatus SV, the said information subsequently switching off the mains switch SN viathe command decoder BE. On the other hand, it is alternatively possible that the "off" position of the key switch is used by the microprogram control unit MPS only as a condition for the fetching of the switch-off microprogram section, the switch-off micro~rogram section being actually started only after all other conditions have been satisfied. As a result, it is possible to switch off the computer also if the operator is absent, for example, wben the last punched card of a bin has been read, or when a given data transfer to a remote station has been completed. After the switching off of the mains switch SN, the completion of the microproeram, however, is not yet a~utomat-ically terminated, but possibly a few short program steps can also be com-pleted. This may be arbitrary steps ~ se, but also steps, for example, which store the location within the program in a predetermined storage loca-tion for statistical purposes in the case of an interruption. Finally, the voltage monitor U signals a forthcoming breakdown of the voltage, the ter-mination microprogram section being started only after that. The instruction which switches off the mains switch SN via the command decoder BE in the power supply apparatus SV can alternatively be transferred, depending on the programming, without switching over of the key switch SS, so that the com-puter is switched off even thougb the key switch is still in the "on" posi-tion.
If the computer has been switched off after actuation of the volt-age monitor U, regardless the cause and after it has been switcbed on again, and the last (partly) executed program of the processor store MEM must be continued, the button RN on the keyboard TA must be depressed again. As has already been discussed, a given storage cell of the processor store MEM is then read, this storage cell notably operating as a program counter for the computer program in normal operating conditions. The computer program can thus be continued at the same location where the interruption appeared, because the processor store is a magnetic core store which maintains the information also after the switching off of tbe voltage supply. In the case of the termination microprogram section, it can definitely occur, after the signalling of a forthcoming breakdown of the voltage, that the computer hasalready started to execute further computer instructions from the processor store MEM, but has not yet completed these instructions, because the asso-ciated microprogram sections were interrupted. When the mains voltage is switched off, the logic sates of the individual microprogram sections are lost, and therefore all computer instructions in the processing store MæM
whose associated micro-instruction sections have not yet bee~ terminated are marked, for example, by storage in a reserved bit position in an other sec-tion of the core store. After the restarting of the computer, the micro-instruction sections associated with the marked computer instructions arestarted again. Part of the microprogram is then executed twice, but on the other hand it is guaranteed that no program step is sXipped, so that no information is lost. For example, a "print" macro-instruction to a printing device first causes positioning of the printing member, after which the information is blockwise transferred. Further positioning can each time take place between successive blocks. If this transfer is interrupted, the micro-program is restarted from the beginning, first the positioning last executed being repeated and subsequently the essentially incompletely printed block of information is transferred again and printed. It may then be that in the same position the originally printed character is printed again. Generally this will not cause ambiguity.
Figures 2, 3, 4 show flow diagrams for the procedures described above. As is usual, the diamond-shaped stages in the diagrams have two out-puts, depending on whether the reply to the question posed therein is pos-itive or negative. In the latter case, the output provided with a horizontal stroke is applicable. The square stages indicate executed (micro) program sections which do not give rise to a choice. The outputs E lead to the termination microprogram of Figure 4. In Figure 2 the stages are reached as follows:
1. START: voltage is switched on (no buttons yet depressed).
2. FIRST TEST PROGRAM: the first test program is executed as described.

3. TEST POWER BREAKDOWN: detect the condition of the power supply apparatus.

4. TEST MEMORY, INCREMENT COU~TER: a fixed number of, for example, 100 storage addresses of the processor store are tested.

5. CARRY COUNTER: if the counter has counted to its maximum value, all addresses have been tested.

6. STORE ROM TO ME~ORY: the fixed condition descriptions of the peripheral apparatus have thus been laid down in the processing store.

7. See 3.

8. TEST READ: has the key RD been depressed~

9. READ CASSETTE, INCREMENT COUNTER: a number of characters are trans~erred from the magnetic tape apparatus to the processor store.

10. See 3.

11. CARRY COUN~ER: if the counter (may be a counter other than that of stage 5) has counted to its maximum value, the complete tape contents have been transferred.

12. TEST RUN: has the key RN been depressed? The positive output of this stage 11 can possibly be connected to a loop wherein only stage 12 and a PBD
test are included.

13. READ ADDRESS ZERO: the first word is to be transferred from the proces-sor store to the microprogram counter. Possibly this may also concern an other word which is first addressed directly or indirectly (via the first directly addressed word).
When a signal is applied to the (not shown) card reader - as an example of a peripheral apparatus without buffer - and a signal is applied to the printer - as an example of a peripheral apparatus with mechanical inertia and a data buffer - these apparatus are started in Figure 3 at the stages 16 and 17, respectively.
18. See 3.
19. DRE PUNCH CARD READER: testine for the interrupt signal of the card reader.
20. READ CHARACTER: one character is fetched.
21. DRE PRINTER: testing as regards the receivability of an information block in the printer.22. TRANSFER BLOCK: transferring an information block (for example, ôO
characters) to the printer.
23. INTERNAC EXECUTION: an arithmetical or other operation, not concerning a transfer, is executed by the execution unit. This unit is in this case activated only i~ DRE PRINTER = FALSE, because a block trans~er has a com-paratively long duration. The stage 23 has a limited length, for example, corresponding to approximately the time required for the stage 22. For example, if there are two buffered peripheral apparatus tX,Y) and one non-buffered apparatus (Z), the arithmetical operations are started only if noneof X, Y requests a transfer; after each transfer, and after the arithmetical operations, first the power supply spparatus and then the peripheral appa-ratus X are interrogated again.
If the ~oltage o~ the power supply ~pparatus has decreased too far, the following takes place:

14. MARK PERIPHERALS: for each peripheral apparatus, as has already been described, a marking information is stored.

15. JUMP MICROPROGRAM COUNTER: the described closed loop is thus formed.

Claims (20)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A computer configuration, comprising a central control unit which includes a processing store which sustains the information of macro-instructions stored therein in the case of a breakdown of the supply voltage, a microprogram counter having an input which is connected to a data output of the processing store and an output which is connected to an address input of a microprogram store, an input of the microprogram counter being connected to an output of a counting pulse generator so as to activate each time a pre-determined series of address positions of the address positions of the micro-program store, the central control unit furthermore including an execution device which is connected to the microprogram store, the processor store and external connection lines, the computer configuration furthermore comprising a power supply apparatus and at least one peripheral apparatus, all the said further apparatus being connected to the said external connection lines via data lines, characterized in that all the said external connection lines include a switch having an open position and a closed position which can be selectively controlled exclusively by a signal from the said execution device, under the control of the data of at least one address position of each series of the said predetermined series of address positions of the microprogram store, the said execution device being capable of generating a series of at least one closing command signal, a closing command signal being capable of each time selectively setting one of the said switches in an ex-ternal connection line which is connected to a signalling line of the said further apparatus to the closed position so as to make the switch conduct an interrupt signal then present to the execution device, the said interrupt signal being capable of controlling, with the exclusion of all other data signals then generated by the said further apparatus, an address signal for the processing store.

2. A computer configuration as claimed in Claim 1, characterized in that per apparatus of the said further apparatus the intervals between successive closing command signals have each time predetermined durations during the control by a single series of address positions of the micro-program store.

3. A computer configuration as claimed in Claim 2, characterized in that each of the said further apparatus includes one data line for an inter-rupt signal which can be interrogated by a single closing command signal.

4. A computer configuration as claimed in Claim 1, 2 or 3, wherein the said series comprises at least two successive closing command signals, characterized in that thus a priority sequence for the said further apparatus can be formed, the power supply apparatus having the highest priority.

5. A computer configuration as claimed in Claim 1, wherein each feasible series of the said predetermined series of address positions of the microprogram store whereby a data transport can be controlled also controls a said closing command, characterized in that an interrogated, active inter-rupt signal is capable of terminating the said data transport, while generat-ing an address signal for the processor store.

6. A computer configuration as claimed in Claim 5, characterized in that under the influence of the latter address signal and signals from the counting pulse generator the microprogram counter addresses a closing command signal for one of the said switches which is connected to a status indication of the further apparatus whereby the latter interrupt signal was generated.

7. A computer configuration as claimed in Claim 6, characterized in that a status signal thus received can generate a further address signal for the processing store.

8. A computer configuration as claimed in Claim 7, characterized in that the last of a series of address positions of the microprogram store can generate an address signal for the processing store so as to control a restart condition for the said data transport.

9. A computer configuration as claimed in Claim 8, characterized in that the restart condition is cooperatively controlled by a priority signal from the said further apparatus.

10. A computer configuration as claimed in Claim 8, wherein the said series comprise at least two successive closing command signals which control a priority sequence among the said further apparatus, characterized in that the restart condition is cooperatively controlled according to the same priority sequence.

11. A computer configuration as claimed in Claim 8, 9 or 10, characterized in that the last of a said series of address positions of the microprogram store is adapted for generating an address signal only in the absence of interrupted, non-completed data transports, the said address sig-nal serving for the processing store for generating a further series of address positions of the microprogram store, for controlling an operation without information contact with a said further apparatus.

12. A computer configuration as claimed in claim 1, characterized in that under the control of a signal from a switched-on working voltage of the supply apparatus a predetermined starting address can be formed for the microprogram counter which continuously receives counting pulses from the counting pulse generator in that under the control of the series of address positions of the microprogram store thus started a number of data which are stored in a non-erasable manner in the microprogram store being written in predetermined address positions in the processor store, the said data relat-ing to microprogram steps for at least one of the said further apparatus, under the control of a termination signal of the said series of address positions thus started a series of closing command signals for data lines of the said further apparatus being started so as to make these lines selec-tively conduct an interrupt signal then present.

13. A computer configuration as claimed in Claim 12, characterized in that in the absence of an interrupt signal, the further apparatus are interrogated in accordance with at least two directly successive cycles of closing commands.

14. A computer configuration as claimed in Claim 12, characterized in that the latter series of closing command signals first of all interrogates a data line of a keyboard for an interrupt signal, in the absence thereof a restarting signal being immediately generated for itself.

15. A computer configuration as claimed in Claim 14, characterized in that under the control of an interrupt signal of a READ key of the key-board an address signal of a series of address positions of the microprogram store can be generated in order to take up a series of data from a second peripheral apparatus in the processor store under the control thereof.

16. A computer configuration as claimed in Claim 15, characterized in that the said second peripheral apparatus comprises a background store.

17. A computer configuration as claimed in Claim 14, characterized in that under the control of an interruption signal from an execution (run) key of the key board an address signal of a series of address positions of the microprogram store can be generated so as to generate an address signal under the control thereof for a predetermined address position in the proces-sor store as the starting address for a macroprogram to be executed.

18. A computer configuration as claimed in claim 12, wherein a further address for the processor store can be generated by a status signal received from a further apparatus, characterized in that under the control of a status signal of the power supply apparatus, the said status signal indi-cating a forthcoming breakdown of the power supply voltage, an address signal can be generated for the microprogram store for sequentially addressing a series of address positions with a termination microprogram therein, with the result that incompletely executed macroinstruction addresses in the processor store are provided with a marking signal, a cycle of terminating address positions being started repetitively, without generating closing command signals.

19. A computer configuration as claimed in Claim 18, characterized in that a predetermined series of address positions of the microprogram store contains a switch-off microprogram, under the control of a transfer of a predetermined instruction signal to the power supply apparatus, controlled by the switch-off microprogram, the mains switch, included therein being switched off, under the control of a status signal of the supply apparatus which announces the said forthcoming breakdown, the termination microprogram being subsequently addressable.

20. A computer configuration as claimed in Claim 19, characterized in that the "off" position of a main switch of the supply apparatus starts the switch-off microprogram only in co-operation with at least one further condition signal.