JPS6242254A - Channel initializing system - Google Patents

Abstract

PURPOSE:To perform the channel initialization processing at a high speed by putting a branch instruction onto a control storage to jump a basic processing routine to an address following the address set when a reset processing routine is through. CONSTITUTION:In a basic processing routine for loading an initial microprogram, the basic processing routine is generally carried out after the rest processing routine through a specific address of a control storage 201. A service processor SVP5 starts the start signal 51, that is, the signal is activated by the SVP5. Then a clock generator 205 is triggered and the clock is set under a RUN state. Thus a control storage address register 2040 is started and a microword register 202 is also set under a RUN state. Then a channel device is started again.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a service processor, which is a small computer that is attached to a device with complex logical functions such as a central processing unit (CPU) and executes system maintenance functions. , relates to a microprogram configuration for speeding up initialization processing of a plurality of channel devices in a computer system equipped with a channel device that connects input/output devices and executes channel control of input/output operations. That is, in order to speed up the initialization processing of each of the plurality of channel devices, a branch instruction that jumps to the basic processing sequence following a microinstruction for reset processing is stored in a control storage in a control unit according to a microprogram method inside each channel device. Store.

After the reset process, the service processor starts the clock, so that the branch instruction is immediately executed and the process jumps to the basic process.

Conventionally, a scan-in method has been used to start execution of this type of initialization processing. That is, at the end of the reset process, each channel is in a stopped state, but at this point the service processor stores the basic processing routine in the control storage address register inside the sequencer that executes the microprogram sequence in each channel device. cents the first address of. That is, scan-in was performed via the address bus. However, in the connection system between the service processor and each channel device, the data bus and address bus are in a loop, so in order to scan the start address of the basic routine into the control storage address register of each channel device, It had the drawback of being extremely slow.

In the present invention, a branch instruction pointing to the start address for the basic processing routine is inserted into the control storage of each channel device after the reset processing is completed, and after the reset processing, the control address register points to the address of the branch instruction. The service processor then activates a start signal to each channel device, that is, a signal that is simultaneously distributed to each channel on one bit line. This causes each channel device to put the stopped clock signal into the RUN state.

The branch instruction is immediately executed. Therefore, the basic
The processing routine will be executed at the speed of the microinstruction execution step, and the initialization process of the channel device will be accelerated.

[Industrial application field]

The present invention relates to a service processor that performs maintenance functions, which is composed of a compact mini-computer attached to a device with complex logical functions such as a central processing unit (CPU), and a channel that controls channels of input/output devices. The present invention relates to a method for speeding up initialization processing by devising a channel microprogram in each channel device of a plurality of channel devices in a computer system equipped with the device.

In particular, the present invention relates to a channel initialization method that speeds up initialization processing by inserting in a control storage a branch instruction that jumps to a basic processing routine at the next step after the end of a reset processing routine.

[Conventional technology]

Dissimilar input/output devices in computer systems.

There is a channel control method as a method for efficiently performing information transfer operations between main storage devices and central processing units (CPUs), that is, input/output operations, and improving system efficiency. In other words, C
The operating speeds of the PU and input/output devices are balanced, and the efficiency of the system can be improved.

When the CPU executes an input/output command, it gives the input/output device number to the channel device and instructs the input/output device to start. The control information of the input/output device includes the address of the main storage device that performs input/output after a channel command, the number of data to be transferred, and the like. When the CPU finishes instructing the channel device to perform input/output operations, it returns to the original execution of the arithmetic processing unit and is released from input/output operations. On the other hand, the channel device decodes the channel command and activates the specified input/output device. The channel device sequentially executes commands given by the channel program, and when the input/output operation is completed, it interrupts the CPU and notifies the end of the input/output operation. Generally, a channel device that performs channel control of input/output operations has a processor that follows a microprogram control method inside, and executes a microprogram regarding each channel of a plurality of channel devices. In this case, the microprogram is stored in the control storage in each channel device, and includes, in addition to the input/output control routine, a reset processing routine and a basic routine for initial microprogram loading, that is, initialization. In large computer systems, such multiple channel devices are connected to the central processing unit (CPU), and are also attached to devices with complex logical functions such as the CPU to perform system maintenance functions. A service processor is installed. The purpose of the service processor is to detect failures in equipment that have made it unusable,
Operations necessary for system maintenance, including repair functions for repair, such as displaying and updating register contents and hardware status information.

Alternatively, it is possible to display the start and stop of various operations, etc. Generally, this service processor is connected to the CPU and each channel device by a data and address bus, and the bus connection in this case follows a loop method. At power-up or when the reset button is pressed, the microprogrammed processor in each channel unit resets the reset button in internal control storage.
7. Execute the processing first. Then, after the reset process is completed, that is, if there is no error process and the operation is normal, the reset process routine stops once at the next address. That is, the channel device enters a clock stop state. From this point on, the basic routine will be executed.

Conventionally, the start address of the basic routine is transferred from the service processor to each channel device via the data address bus, and set or scanned into the controller storage address register in the processor in each channel 'JB. was running. In this case, in order to execute the basic routine for initialization, the service processor scans in the start address of each channel device via the loop communication, which takes a very long time. especially.

If there are a large number of channel devices, the disadvantage is that it takes a considerable amount of time, 2 hours, to execute the basic routine. As described above, in this type of conventional initialization method, the service processor scans in a fixed value, which is the start address of the basic routine, into the control storage address register in each channel, and then starts the microprogram of the channel device. Therefore, scanning in the first address takes several tens of milliseconds, and in the case of a plurality of channel devices, it takes several seconds.

[Problem that the invention seeks to solve]

An object of the present invention is to eliminate the drawbacks of this type of conventional channel initialization method, and to insert a jump instruction pointing to the start address of the basic routine at the address next to the reset processing routine in control storage, so that the service processor can After the reset processing routine has been completed, the jump instruction is executed by simply causing the device to run the clock using a start signal. Therefore.

The invention works at the speed of microprogram steps.

It provides an extremely fast initialization method in which basic routines are executed.

[Means for solving problems]

The present invention aims to alleviate the above-mentioned problems in a computer system comprising a central processing unit, a service processor, a plurality of channel devices, and the like.

A branch instruction indicating the start address of the basic routine is stored in a control storage for storing a microprogram in a processor according to a microprogram method in each channel device at an address next to the address where the microstop microinstruction is stored; From a state in which the channel device executes the microstop microinstruction and is in a microstop state, the plurality of channel devices execute the jump instruction in parallel at the microinstruction speed via a start signal given from the service processor. This is achieved by providing a channel initialization method characterized by simultaneously executing the basic routine.

[For production]

In the present invention, the microstop microinstruction at the end of the reset processing routine is placed in control storage within the processor within each channel device.

In other words, since there is an instruction to stop the clock after the reset processing routine ends, when each channel device executes this instruction and enters the hold state, the start of the channel basic routine is placed at the address next to the microstop microinstruction. The speed is increased by inserting and executing a branch instruction that points to an address. That is, since the contents of the control storage address register in the hold state point to the address of the branch instruction, the service processor is activated, ie.

A system is commonly used in which the branch instruction is executed by running the clock to execute the basic routine at microstep speed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a plurality of channel devices connected to a central processing unit (CPU) 1, for example channel devices 2, 3, . and 4
1 is a system configuration diagram of a computer system consisting of 03 channels and a service processor 5. FIG. The central processing unit is an arithmetic unit that follows a so-called program method that sequentially executes instructions in the main memory 6, processes data in the same main memory 6, and stores the results in the main memory 6 again. It is. On the other hand, each channel device 2, 3.4 performs channel control of the input/output device connected to each device, that is,
Control and CPU 1 and main memory device 6 that assist input/output operations
It contains a processor for channel control, which is the control for communicating with. The service processor 5 is a processor that is attached to a device with complex logical functions such as the CPU and executes system maintenance functions.
It consists of a compact minicomputer or microcomputer. The service processor 5 performs repair operations when a failure occurs or operations necessary for maintenance functions to maintain the entire system.

For example, displaying or updating register contents or hardware status information, displaying or updating main memory or control equipment, starting or stopping operations, or collecting login and logout information to display information on a CRT display device. It displays repair and maintenance information.

In such a computer system, when the power is turned on, the CPUI and the processors inside each channel device 2.3.4 first execute an initialization routine. That is, IPL (initialization program load) will be executed.

At this time, the microprogram in the CPUI and the microprogram in the control storage in the processor of each channel device are executed, but the execution of the initialization routine generally requires the assistance of the service processor 5.

That is, the microprogram in each channel device executes a reset processing routine when the power is turned on or the reset button is pressed. if.

If the device runs normally without errors, a microstop instruction will have been inserted at the end of the reset processing routine when the reset processing is completed.

This instruction is executed, the clock is stopped, and each channel device 2, 3.4 is placed in a hold state. As shown in the figure, the service processor 5, CPUI, and each channel device 2, 3.4 are connected in a loop manner through data and address buses. That is, when data and addresses are transferred from the service processor 5, they are transferred to the CPU 1, channel device 2, . Channel device 3. For example, when data or addresses are transferred to channel device 4, they are transferred via the CPUI or channels 2 and 3, and generally when data or addresses are transferred.

The speed becomes slower.

On the other hand, signals other than the data address 9, for example, a start signal, are sent to the CPUI channel device 2. Channel device 3. Each of the control lines is connected in parallel to the channel device 4 as a 1-bit control line. Therefore, if each channel device 2, 3.4 is in a hold state and the service processor 5 initiates a start, multiple channel devices 2, 3.
．． 3.4 enters the clock RUN state and the microprogram starts. in this way.

In the computer system shown in FIG. 2, the start address of the basic processing routine in the control storage is transferred from the service processor 5 to each channel device 2, 3.4 to each control storage address register via the bus. It will be faster to start them in parallel using a control signal such as a start signal.

The present invention has focused on this fact, and when each channel device 2.3.4 enters a stopped state after the reset processing is completed, the
When starting a basic routine for initialization to be performed next, the address of the basic routine is not transferred via the bus, but is transferred to the address next to the microstop microinstruction at the last address of the reset processing routine. A jump instruction to jump to the start address of the routine is inserted, and this instruction is activated by the start signal. After the reset processing routine is completed, the control storage address register of each channel device 2, 3.4 points to the address where the jump instruction is stored, so the service processor 5 activates the start signal to run the clock. By this, the jump instruction is executed simultaneously in each device, and the basic routine for initialization is executed at the speed of a microprogram step.

In order to explain in detail the initialization method of the present invention described above, the explanatory diagram of the microprogram method shown in FIG. 1 will be used. In FIG.

A processor 20 is present in each channel and is a microprogram based processor. The microprogram is stored in control storage 201. Control storage 201 is comprised of so-called random access memory or read-only memory. When the control storage 201 is generally addressed by the control storage address register 2040, the addressed one microinstruction is outputted to the output 2011 location via the address decoder 2010 and sent to the microword register 202. Then, the contents set in the microword register 202 are transferred as a control signal to another processing system 2, such as an arithmetic processing system, inside the channel device, and the channel control routine is executed. A control storage address register 2040 for addressing the control storage 201 is located inside the so-called microinstruction sequencer 204 and serves as a program counter for the so-called control storage 201 . Namely.

When an address is set in the control storage address register 2040, it is generally decoded to point to the start address of a specific routine within the control store 201 specified by that address. Then, after the start address is started, it acts as an incrementer that is incremented by 1, but if there is a branch instruction in the control storage 201.

The destination address in the branch instruction is set in the microword register 202 via the output of the control storage, and in the second clock cycle, the destination address is set in the control storage address register 2040 in the sequencer 204 and the address decoder 2010 is set in the microword register 202 through the output of the control storage. The basic routine at the jump destination will be executed.

In the sequencer 204 that controls such a control storage 201 and its address.

Each microprogram step is clocked by a clock generator 20.
5 is executed very fast according to the clock generated from 5. When the processor 20 starts up.

That is, when the power is turned on or the reset button is pressed, the contents of the control storage address register 2040 are, for example, all O, and the O address of the control storage 201 is specified. Then, according to the clock input, the data is stored from address O to address n, and a cent processing routine is executed. A microstop microinstruction is stored at the last address of the reset processing routine, that is, address n, and when this instruction is executed, it acts on the clock generator 205 in the processor 20, causing the clock to be stopped. Therefore, the contents of the control address register 2040 are stored at the address n next to the n address where the microstop microinstruction is stored.
It points to address +1 and becomes stopped. However, if there is an error while executing the reset processing routine, the process jumps to the error processing routine, so the reset processing routine is executed only when there is no error.

It will stop at address n only when it is normal.

In the basic processing routine for initial microprogram loading, the routine to be executed next after the reset processing routine is completed is generally the basic processing routine. This will start from a specific address in control storage 201. The start address of the basic routine is the control storage address register 2.
In the conventional method, this was executed by scanning in at 040, but the present invention eliminates such a scan-in operation and transmits the start signal 5 from the service processor.
This is done by starting 1. That is,
This is done by the service processor 5 triggering the clock generator 205 by activating the start signal 51 and putting the clock in a stopped state. When the clock enters the RUN state, the control storage address register 2040 enters the START state,
Microword register 202 will also go into the RUN state and the channel device will be restarted.

At the stage where the reset processing routine has finished processing from address 0 to address n, the control storage address register 2040 points to address n+1, so if the next microstop instruction (address n) in the control storage 201 If the branch instruction pointing to the address where the basic routine for initialization is stored at address n+1 is cleared, the start signal 51 is activated by the service processor 5, and the clock generator 2 is activated.
When 05 enters the RUN state, this branch instruction is executed first. This branch instruction stores the start address of the basic processing routine, so n
+1 address branch instruction is control storage 20
1 and set in the microword register 202, the start address of the basic routine is set in the control storage address register 2040. This content is control storage 20
1 address is specified.

The start address of the basic routine is specified, and the basic routine will be executed from then on. In other words, in the present invention, in the microprogram in the channel device,
The last n of the reset processing routine for addresses 0 to n.
After entering the microstop microinstruction at the address and completing the reset processing routine, each channel device 3.4.5 enters the microstop state and waits for a start command from the service processor 5. Each channel device 3, 4.5 simply restarts the microprogram by the service processor 5 simply sending a start signal 51 via the start signal line 51 to all channel devices simultaneously, and the control storage address 20
40 i.e.

The vehicle will run from the contents of address n+1. The time it takes for the processor activated by the start signal 51 to execute the basic routine is the clock period for executing the microprogram, that is, the clock cycle of the processor, so that the basic routine is executed at high speed. Furthermore, since the start signal is connected from one service processor to multiple channel devices in parallel via a 1-bit line, execution from the start to the execution of the basic processing routine is extremely fast. It turns out. In other words, the channel initialization method of the present invention is different from the conventional method in which the service processor 5 scans in a fixed value corresponding to the start address for the basic routine into the control storage address register 2040 of each channel device 2, 3, 4. and remove each channel device 2, 3 from the service processor 5.
At the same time, a start signal sent via a 1-bit line is used to run the clock, and the basic processing routine is jumped to at a microstep speed, thereby executing the routine at high speed.

〔Effect of the invention〕

In this way, the present invention inserts a jump instruction that executes the basic processing routine into the control storage at the address next to the address at the end of the reset process.

By activating it with a start signal from the service processor, the initialization process can be speeded up.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a microprogram method for explaining the initialization method of the present invention. FIG. 2 is a configuration diagram of a computer system consisting of a central processing unit, three channel devices, and a service processor. ■...CPU. 2.3.4... Channel device. 5...Service processor. 6... Main memory device. 20...processor. 50...Address bus. 51...Start signal line. 52...Hold signal. 201...Control storage. 202...Microword register. 204...Microinstruction sequencer. 2010...Address decoder. 2040...Control storage address register.ゝ－；：

Claims (1)

[Claims] In a computer system consisting of a central processing unit, a service processor, a plurality of channel devices, etc., a microstop microprocessor is provided in a control storage for storing microprograms in a processor according to a microprogram method in each channel device. A branch instruction indicating the start address of the basic routine is stored at an address next to the address where the instruction is stored, and the channel device executes the microstop microinstruction and is in the microstop state, and then the service is started. A channel initialization method characterized in that the plurality of channel devices simultaneously execute the basic routine in parallel with the jump instruction at a microinstruction speed via a start signal given from a processor.