JPH0147818B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an information processing device, particularly an information processing device including a main processing device including, for example, a scalar calculation section and a sub-processing device including, for example, a vector calculation section, so that the calculation sections of both processing devices are independent of each other. Make sure to perform arithmetic processing,
When an interrupt cause occurs in either or both of the above two processing units, the main processing unit executes the interrupt processing all at once, and the interrupt causes corresponding to the processing in each of the above processing units are independently handled. The present invention relates to an information processing device configured to hold information.

Generally, in an information processing apparatus that performs vector calculation processing, it is necessary to be able to perform not only vector calculation processing but also scalar calculation processing. In this case, since the vector arithmetic processing and the scalar arithmetic processing can generally be executed independently of each other, a scalar arithmetic section and a vector arithmetic section are provided to perform parallel processing. Of course, in some cases, incorrect results may occur if the execution order differs between scalar arithmetic processing and vector arithmetic processing, and in such cases it is necessary to synchronize the execution order between the two. Become.

In such an information processing device, the main processing unit is configured to execute scalar instructions, instruction fetch processing, interrupt processing, etc., while the slave processing unit executes vector requests from the main processing unit. Executing an instruction is being carried out. In general, the execution of a vector instruction requires multiple cycles compared to the execution of a scalar instruction, so for example, by the time an interrupt request is issued from the slave processor side, the program counter of the main processor has already advanced by several steps. Therefore, when the main processing unit executes the interrupt processing, the processing for investigating the cause of the interrupt corresponding to the interrupt is extremely complicated. Furthermore, as mentioned above, since the main processing unit and one or more slave processing units perform parallel processing, for example, when performing retry processing, it is possible to determine in which processing unit the cause of the interrupt has occurred. It is desirable to know this and take appropriate action.

The information processing device of the present invention includes a main processing device and one or more slave processing devices, and the main processing device controls the instruction sequence and sequentially sends the instructions to be executed by the slave processing device to the slave processing device. In an information processing device that requests and executes an instruction to be executed by the main processing device, and the slave processing device executes the requested instruction in pipeline processing, the main processing device and/or the slave processing device When the same type and/or different types of interrupt causes occur in the main processing unit, the main processing unit is configured to execute interrupt processing corresponding to the interrupt cause, and the interrupt cause corresponding to the processing in the main processing unit information is held in the main processing unit, and interrupt cause information corresponding to processing in the slave processing unit is held in the slave processing unit, and the main processing unit and/or the slave processing unit When an interrupt cause occurs, an interrupt request is issued to the main processing unit, and the slave processing unit executes the process assigned to it and completes the process regardless of whether the interrupt cause occurs or not. The main processing unit is configured to report the processing to the main processing unit, and after receiving the completion of processing from the slave processing unit, the main processing unit issues an interrupt processing permission signal corresponding to the interrupt request and executes the interrupt processing. Therefore, the above-mentioned interrupt cause information is read by software and processed all at once. This will be explained below with reference to the drawings.

FIG. 1 is an overall configuration diagram of an embodiment of an information processing apparatus according to the present invention, in which 1 is a memory, 2 is a main processing unit, 3-2, 3-2... are slave processing units, and 4 is an instruction control unit. 5 is a scalar operation section that fetches instructions from memory 1 and performs distribution control; 5 is a scalar operation section that fetches and executes scalar instructions from instruction control section 4; and 6 is a vector operation section that executes instructions. Control unit 4
14-1 represents an interrupt cause holding unit that holds interrupt causes.

FIG. 2 is an explanatory diagram for clarifying the processing mode of the information processing device shown in FIG. 1, and is shown with only one slave processing device. As shown in Figure 2, vector instructions V1, V2,... and scalar instructions
When it is requested to execute SC1, SC2, ..., vector instructions V1, V2, ... and scalar instructions SC1, SC2 can be generated by giving a vector instruction from general or instruction control section 4 to vector operation section 6. ,…
can be executed in parallel. By doing so, it becomes possible to shorten the processing time. FIG. 2 shows how scalar instructions SC1-SC6 are executed serially, and vector instructions V1-V5 overlap and are executed in parallel with the scalar instructions. In the figure, "LAST VU" is a signal that is sent out at the same time as the last vector instruction in a series of vector instructions is sent to the vector calculation unit 6. Also,
In the figure, "CPU RELEASE" is a signal sent from the vector calculation unit 6 to the scalar calculation unit 5 to allow the scalar calculation unit 5 to continue parallel processing.

Now, for example, as shown in Figure 3, if an error occurs while executing scalar instruction SC5 in the scalar operation section, the program counter indicates the position of the scalar instruction SO5, but the is the vector instruction V1 to V5 at the previous instruction position
The processing has not yet been completed, and if an attempt is made to immediately perform an interrupt processing operation when the error occurs, the program logic cannot be guaranteed. Therefore, in the above case, when the processing of the slave processing device is completed, in the example shown in FIG.
The main processing unit starts interrupt processing when the processing of V5 is completed. Of course, if an interrupt cause that prevents continued execution occurs, each processing device processes, for example, a NOP, and reconciles the program status word.

When processing is carried out as described above and an interrupt cause occurs in the main processing unit itself or in a slave processing unit, the interrupt cause is conventionally held in the main processing unit, and the main processing unit investigates the cause when processing the interrupt. It was like that. However, there is no way to later check in which processing device the cause of the interrupt occurred or in response to which processing, and it is only determined by checking each processing device one by one, which makes the processing complicated. becomes.

FIG. 4 shows an embodiment of the main parts of the information processing apparatus of the present invention. Numerals 1, 2, 3, and 6 in the figure correspond to those in Figure 1, 7 is an instruction register, 8 is an instruction buffer, 9 is an instruction decoder, and 10 is one of the vector instruction arithmetic units, which is a pipeline. 11 is an arithmetic control pipeline that controls the pipeline processing of the vector instruction arithmetic unit 10; 12 is a process completion detection circuit;
Reference numeral 3 represents an interrupt condition detection circuit, 14-0 and 14-1 represent interrupt cause holding circuits, 15 represents an interrupt generation flip-flop, 16 represents an OR circuit, and 17 represents an AND circuit.

As mentioned above, when a series of vector instructions V1, V2, V3, and V4 are sent in order from the instruction control unit 4,
In the slave processing unit (vector processing unit) 3, the commands are sequentially set in the instruction register 7, decoded by the decoder 9, and executed. In cases where the processing of the vector instruction V2 sent earlier and the processing of the next vector instruction V3 use the same vector instruction arithmetic unit 10, the vector instruction V3 is temporarily set in the cooling buffer 8 and placed on standby. Sometimes.

The decoder 9 decodes the instruction, and one vector instruction arithmetic unit 10 executes vector arithmetic processing according to the result. In other words, operand data is fetched one after another from memory 1 and sent to arithmetic unit 1.
0 by pipeline processing,
It is returned to memory 1. At this time, the arithmetic control pipeline 11 manages the status of the arithmetic processing.

In this state, if a failure occurs in the slave processing unit 3, the interrupt condition detection circuit 13 detects the interrupt condition and sends an interrupt request to the main processing unit 3.
will be reported. The interrupt cause is held in the interrupt cause holding circuit 14-1. Of course the main processing unit 2
When an interrupt cause occurs in the main processing unit 2, the interrupt cause is held in the interrupt cause holding circuit 14-0 on the main processing unit 2 side.

In response to the above-mentioned interrupt request, the instruction control unit 4 shown in FIG. 1 stops instruction processing including sending vector instructions to slave processing units. On the other hand, slave processing device 3
In this step, processing is performed based on the vector instructions held in the instruction buffer 8 as well as those instructions. Of course, if an interrupt cause that prevents continued execution occurs, subsequent processing will be
It will be treated as NOP.

When all instruction processing is completed in the slave processing unit 3, an operation end signal is sent from the operation control pipeline 11, a memory access completion signal for transferring operation result data is sent from the memory 1, and a buffer empty signal is sent from the instruction buffer 8. When an instruction empty signal is sent from the instruction register 7, the processing completion detection circuit 12 sends a signal indicating the completion of processing in the slave processing device 3 to the main processing device 2. In response to this processing completion signal, in the main processing device 2, the AND circuit 1
The output of 7 is turned on, and an interrupt processing permission signal is sent to an interrupt processing section (not shown). As a result, the interrupt processing section (not shown) starts interrupt processing. At this time, the processing device that has caused the interrupt cause holds interrupt cause information in the interrupt cause holding circuit 14-i, and the contents of the interrupt cause holding circuit 14-i are stored in the main processing device 2. The information is read by the program during interrupt processing, and it is checked in which processing device or in which processing the cause of the interrupt has occurred.

Note that if an interrupt cause occurs in the main processing unit 2 itself, or if an interrupt cause occurs in multiple slave processors, a healthy slave processor will correctly process the vector instructions assigned to it. This is taken into account when performing retry processing.
That is, in the past, processing was performed such as retrying a vector instruction that was being executed in parallel when the cause of an interrupt occurred, using, for example, a scalar instruction, but in the case of the present invention, a correctly executed vector instruction or Instruction groups are excluded from the above processing targets.

Note that in the above, the interrupt cause holding circuit 14-
Although it has been shown that i is held in each processing device, logically speaking, it is not necessarily necessary to hold it in the processing device, and it may be held in the memory 1, for example.

As explained above, in the present invention, since one system is conventionally constituted by a main and slave processing unit, an interrupt cause holding circuit is provided in one system.
This improves the point that only one existed before, and the cause of the interrupt can be held in the execution unit executed by each processing device, thereby greatly simplifying the interrupt processing.

Needless to say, it is optional to further divide the processing in each processing device and hold interrupt causes for each processing device, if necessary.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the information processing apparatus of the present invention, FIGS. 2 and 3 are explanatory diagrams for clarifying the processing mode of the information processing apparatus shown in FIG. 1, and FIG.
The figure shows an embodiment of the main parts of the information processing device of the present invention. In the figure, 1 is a memory, 2 is a main processing unit, 3 is a slave processing unit, 4 is an instruction control unit, 5 is a scalar operation unit, 6
14 represents a vector calculation unit, and 14 represents an interrupt cause holding circuit.

Claims (1)

[Claims] 1. A main processing unit and one or more slave processing units are provided, and the main processing unit controls the command sequence and sequentially requests the commands to be executed by the slave processing unit, and the main processing unit In an information processing device that executes an instruction to be executed in the main processing device and/or in which the slave processing device executes the requested instruction in a pipeline process,
Or, when a different type of interrupt cause occurs, the main processing unit is configured to execute interrupt processing corresponding to the interrupt cause, and the interrupt cause information corresponding to the processing in the main processing unit is Interrupt cause information held in a processing device and corresponding to processing in the slave processing device is configured to be held in the slave processing device, and the main processing device and/or the slave processing device When an interrupt occurs, an interrupt request is issued to the main processing unit, and the slave processing unit executes the process assigned to it regardless of whether or not the cause of the interrupt occurs, and the process is completed by the main processing unit. After receiving the completion of processing from the slave processing device, the main processing device issues an interrupt processing permission signal corresponding to the interrupt request, and executes each of the above when executing the interrupt processing. An information processing device characterized in that interrupt cause information is read by software and processed all at once.