JPS58166454A - Data processor - Google Patents

Abstract

PURPOSE:To retry the execution of an instruction, by providing a register for storing a current address and two flags for indicating the presence of the current address of an instruction to be retried. CONSTITUTION:The output of a flag 29 indicates that host unit instructions are prepared and the value of a new PC is set in a register 7a. The output of a flag 30 shows that an error occurs to a host unit and the value of the new PC is not set in the register 7a. The outputs of those two flags are sent to a microprogram control circuit 33 and a microprogram makes a decision on them. Those are sent through signal lines 31 and 32. Gates 26-28 generate set condition for those flags and their setting timing is controlled by signal lines 34-36 from the microprogram control circuit 33.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that executes an instruction, and is particularly suitable for a data processing device in which the preparation of an instruction and the operands handled by the instruction, and the execution of the instruction are executed by pipeline processing. Concerning the retry method for certain instructions.

One way to improve the reliability of a data processing device, particularly to increase its operating rate, is to recover from temporary malfunctions by retrying. In recent years, data processing systems that have this retry function have
IT is increasing. Data processing mfl that executes instructions
It is common for the unit of retry to be taken as an instruction. In addition, with the increase in reliability, data processing devices are rapidly increasing in speed, and one of the typical technologies is pipeline processing in instruction execution. In the data processing fjli that performs pipeline processing, the next instruction of the currently executing instruction is prepared while the current instruction is being executed, and as soon as the execution of the currently executing instruction is completed, the next instruction is prepared. speed up by making it possible to move on to the execution of the next instruction
liQ is here. In a data processing device that performs such pipeline processing, information for retrying an instruction, such as which instruction! 4 trials, or it is necessary to save the changed memory contents and the contents of general-purpose registers, which inevitably increases the hardware and complexity. That is, when attempting to retry instructions in a data processing device that performs pipeline processing, there is a drawback that the hardware increases and the circuit becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that realizes retrying of instructions by adding a small amount of hardware in a data processing system that uses a pipeline system.

A feature of the present invention is that the middle K of the instruction execution unit of a data processing device that performs pipeline control includes a register (hereinafter referred to as a program counter: PC) that stores the location address in memory of the instruction currently being executed; Two flags are provided to indicate where in the unit that performs pipeline control the location address of the instruction to be retried exists, thereby making it possible to retry the instruction.

FIG. 1 is a book showing a block diagram of an embodiment of a data processing device that performs vibe line processing to which the present invention is applied.

The data processing device includes a total of five instruction fetch units 3, instruction decode units 4, address calculation units 5, operand fetch units 6, and instruction execution units 7.
It is composed of units. Among these units, a unit (in this embodiment, 3
．． 6 and 7) are connected by the internal bus 2 of the processing device.
is connected to. Each unit has registers 38, 48, 5m and 6a that store the memory address of the instruction that it is currently processing.

7a, respectively, and at the same time as the instruction, the contents of these registers, unit 3 → unit 4 → unit 5 →
The instruction is transmitted in the order of unit 6 in a pipeline manner, and then transmitted to instruction execution unit 7), where it is stored in 71 of the units. By the way, while an instruction is being executed in the instruction execution unit 7, the memory address of the currently executing instruction is stored in the register 7m, and if an error occurs during the execution of the instruction. , if it becomes necessary to retry the wrinkle instruction, the contents of the register 7a are transferred to the upper unit 3 again.
It is possible to re-execute the process by setting it again and returning the vibe line processing to its previous state.

However, the problem here is that the contents of register 7a do not always indicate the address of the instruction to be re-executed. For example, if an error occurs in a machine cycle that ends an instruction, the address of the next normal instruction may or may not have already been set in register 7a. The unit 7 is provided with a register 7b that stores the memory address of the previous instruction.

FIG. 2 shows an embodiment of the instruction execution unit 7, which is the main part of the present invention. The instruction execution unit 7 includes
A signal line (PC line) 23 for passing the memory address of the instruction from the upper operand fetch unit 6
, a signal line (READY line) 24 that indicates that the next instruction is ready, and a signal line (ERROR line) 25 that indicates that an error has occurred in the next instruction. It has a register 7a that stores the address of the instruction currently being executed, and a register 7b that stores the address of the previous instruction.

When retrying the instruction, the instruction is re-executed using the register 7m, the father's value 7b, or the PC value of the upper unit. Flags 29 and 3o indicate which PC contents should be used for retrying.The output of flag 29 indicates that the upper unit instructions are complete and the new PC value is in register 7! Indicates that IK has been set. The output of flag 30 indicates that an error has occurred in the upper unit, and a new PC is required.
Indicates that the value of register 7aK is not set.
The outputs of these two flags are led to the microprogram control circuit 33 to enable determination by the microprogram. They are transmitted on signals @31.32. 26, 27 and 28 are for generating setting conditions for each flag, and their setting timing is determined by the signal lines 34 and 35 from the microprogram control circuit 33.
．． 36.

FIG. 83 shows the output states of flags 29 and 30. The location of the retry rounding instruction address is indicated by h written at the bottom of the figure.

As described above, according to the present invention, with a slight increase in hardware, in a pipeline-controlled data processing device,
Instructions can be retried.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a pipeline-controlled data processing device to which the present invention is applied; FIG. 2 is a diagram of an embodiment of an instruction execution unit that is the main part of the present invention;
A is a diagram explaining the operation of FIG. 2. 7...Instruction execution unit, 7a, 7b...Register, \1st'fJ2th

Claims (1)

[Claims] 1. In a data processing device in which instruction execution is performed by pipeline processing, the unit that executes instructions has a first register that stores the memory address of the currently executing instruction, and a memory address of the previous instruction. A second register that stores the memory address of the next instruction to be executed at the end of one instruction is set in the #ggt register, and a first flag that indicates whether the memory address of the next instruction to be executed is set in the #ggt register and the next instruction at the same time. A second flag is provided to indicate that an error has occurred, and it is determined in which register the memory address of the instruction for retrying is stored in accordance with the contents of the first and second flags. A data processing device characterized in that the data processing device performs an instruction retry.