JP2782471B2 - Data transfer retry control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a retry control method for data transfer to a memory / I / O via a bus in a processor having a microprogram-controlled CPU. A macro program memory for storing a macro program, a macro program counter for designating an address of the macro program memory, and a micro memory for storing a micro program. In a retry control method of data transfer in a processor having a program memory, a micro sequencer designating an address of the micro program memory, and a CPU operating based on a micro instruction read from the micro program memory, a predetermined When a bus transfer error occurs due to execution of a micro instruction of a micro program that decodes and executes a macro instruction, the CP
By re-executing the micro-instruction of the micro-program for decoding and executing the predetermined macro-instruction by aborting the operation of capturing the read data of U, updating the transfer address of the data, and updating the address specified by the micro-sequencer, The bus transfer is re-executed up to a predetermined number of times if the bus transfer error is not resolved.

[Industrial applications]

The present invention relates to a retry control method for data transfer to a memory / I / O via a bus in a processor having a microprogram-controlled CPU.

[Conventional technology]

FIG. 9 is a diagram showing a configuration example of an information processing apparatus using a conventional processor. Information processing devices such as various computers and programmable controllers are generally ninth
As shown in the figure, it comprises a processor 100, a memory 200, an I / O device (input / output device) 300, a transmission interface 400 and the like. The processor 100 performs data transfer via the system bus 500 when exchanging information with the memory 200, the I / O device 300, the transmission interface 400, and the like. The processor 100 employs a microprogram control method, and is a macro program including macro instructions obtained by compiling or assembling a source program described in a high-level language such as FORTRAN or COBOL or a controller language for a program controller. The execution of
Decoding is performed by a microprogram.

Processor 100 includes a microprogram memory 101 that stores a microprogram of microinstructions.
(Hereinafter abbreviated as μ-MEM101), a micro-sequencer 102 (hereinafter abbreviated as μ-SQC102) for supplying an address to the μ-MEM101 at regular intervals (microcycles), and read from the μ-MEM101. A pipeline register 103 (hereinafter, abbreviated as PLR103) that holds the read microinstruction and outputs various control signals from the microinstruction, performs various operations instructed by the microinstruction read from the PLR103, and as a result CPU (central processing unit) 104 that outputs various flags such as sine code (S), zero detection (Z), carry detection (CY), overflow detection (OVF), etc., when inputting bus data on system bus 500 A bus parity checker / generator 121 that performs parity generation performs a parity check of bus data and outputs data to the system bus 500. Bus access time monitoring circuit 122 for monitoring access time
A bus transfer error detection circuit 120 including a slave device abnormality signal determination circuit 123 that constantly monitors an abnormality state of a slave device at a transfer destination via the system bus 500; a macro program memory 105 storing the macro program; A macro program counter 106 (hereinafter referred to as MPC10) that supplies an address to the macro program memory 105
6), a physical address generation circuit 107 for generating a physical address from an address operand of a macro instruction read from the macro program memory 105, and a transfer address for holding an address of transfer data added from the physical address generation circuit 107. A register 108 and a bus error signal or CPU added from the bus transfer error detection circuit 120.
And a test condition selection circuit 109 for selectively outputting the value of each flag of S, Z, C, Y or OVF added to 104 to the μ-SQC 102.

The bus transfer error detection circuit 120 detects the occurrence of a parity error by detecting the bus parity checker / generator 121, the bus access time abnormality by detecting the bus access time monitoring circuit 122, and the data transfer by detecting the slave device abnormality signal determination circuit 123. A bus error signal is output due to any factor of slave device abnormality.
The MPC 106 and the transfer address register 108 respectively provide a program count enable signal (PCE),
The address signal is set when the address latch enable signal (ALE) becomes active. Also,
The CPU 104 is connected to the system bus 500 via a local data bus 130.

In the above configuration, the macro instruction in the macro program memory 105 addressed by the MPC 106 is decoded and executed by the interpreter composed of a plurality of corresponding micro instructions stored in the μ-MEM 101 via the μ-SQC 102 by MAP processing. Is done. There are several types of macro instruction transfer instructions depending on the transfer mode. For example, 32-bit read / write transfer, 16-bit read / write transfer, 8-bit read / write transfer,
And signed transfer of 16/8 bit length (with sign extension during transfer)
Convert to 32-bit length). And μ-MEM101
An interpreter corresponding to each of these macro instructions is stored therein.

At the time of execution of each transfer instruction, at the same time when the interpreter in the μ-MEM 101 is started, the address operand in the macro instruction read from the macro program memory 105 is transferred by the physical address generation circuit 107 to the transfer address as a physical address. After that, the ALE signal is activated to be latched in the transfer address register 108. Then, by starting the interpreter, CP
When U104 starts data transfer via the system bus 500, a transfer address is output from the transfer address register 108 to the system bus 500, and the corresponding memory 200 or
Information is exchanged with the I / O device 300 and the like.

In the data transfer via the system bus 500, the bus transfer error detection circuit 120 causes the system bus 5
The parity check of the bus data on 00, the time monitoring of the bus access, and the abnormal state of the slave device at the data transfer destination are always checked, and in the event of an abnormality, a retry process is performed in order to cut off a temporary defective operation. Then, when the retry processing has failed, the RAS processing routine in the system management program is notified of the failure, and a decision is made from the viewpoint of the system such as continuous operation or system stop due to degeneration.

Next, a retry control method for data transfer via a bus in the above conventional example will be described with reference to the flowcharts of FIGS. Note that the retry counter RTC
The value of (hereinafter simply referred to as RTC) determines the number of retries. In this example, it is assumed that the number of retries is set to three.

First, in the 32-bit data read interpreter shown in FIG. 10 (a), after reading 32-bit data via the system bus 500 (SA1), the bus transfer error detection circuit 120 generates a bus error. Is determined (SA2), and when a bus error occurs, a 32-bit length data read-only retry subroutine is called (SA
3).

On the other hand, when the bus error does not occur and the data transfer is normally performed, the MPC 106 is counted up by the MAP processing, and the processing shifts to the next macro instruction.

The bus error determination in the process SA2 is performed by the bus transfer error detection circuit 120 shown in FIG. 9 outputting the bus error signal detected in the 32-bit data transfer to the μ-SQC 102 via the test condition selection circuit 109. , Μ-SQC102.

FIG. 10 (b) is a flowchart showing a retry subroutine exclusively for reading 32-bit length data.
The bit-length data read-only retry subroutine
This is an example in which the number of retries is set to three.

Next, the processing of this subroutine will be described with reference to the following.

First, 4 is stored in the retry counter (RTC) (S
B1).

 Subtract "1" from the RTC value (SB2).

Determine whether the value of RTC is equal to "0" (SB3),
If it is not equal to "0", the 32-bit data is read again (SB4).

Next, a bus error is determined (SB5). If a bus error has occurred, the process returns to the process SB2 again to read out the 32-bit data again.

On the other hand, if a bus error has not occurred in the above process SB5, the retry read has succeeded, this subroutine is exited by return, the process returns to the interpreter, and the MAP process is performed. To go.

When the re-reading of the 32-bit data fails in the above process SB4, the above processes SB2 to SB5 are repeated up to three times.
After determining that RTC = 0 in 3 and starting the RAS processing of the system management program, exit this subroutine by return,
The processing shifts to the system management program processing by interruption.

Also, in the 16-bit read interpreter, the eleventh
By the 16-bit read interpreter shown in FIG. 7A and the 16-bit read-only retry subroutine shown in FIG. Also, in reading / writing of other various data bit lengths and various transfer modes, similar processing is performed by an interpreter for performing the transfer processing and a dedicated retry subroutine prepared for each of the interpreters.

[Problems to be solved by the invention]

As described above, in the conventional data transfer processing via a bus by an interpreter corresponding to one macro instruction, a step of always checking whether a bus error has occurred after data transfer processing such as memory read / write is performed. This is necessary, and when the number of steps of the microprogram for decoding and executing one macro instruction is small, the processing speed is greatly affected. (If the microprogram that decodes and executes one macro instruction is one step, the processing time of the transfer instruction is doubled.) Also, if there are a plurality of data transfer access modes (for example, 32-bit read / 16-bit Read, 8-bit read, 32-bit ride, 16-bit write, 8-bit write, etc.), a plurality of retry processing routines must be prepared for each of these access modes. However, there is a disadvantage that the size of the image becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transfer retry control method that can speed up data transfer and reduce the used capacity of a microprogram memory.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

According to the present invention, a macro program memory 1 for storing a macro program, a macro program counter 2 for specifying an address of the macro program memory 1, a micro program memory 3 for storing a micro program, and specifying an address of the micro program memory 3 A micro sequencer 4 and a CPU 5 that operates based on micro instructions read from the micro program memory 3
Is assumed to be a data transfer retry control method in a processor having

In the data transfer retry control method of the present invention,
When a bus transfer error occurs due to execution of a microinstruction of a microprogram that decodes and executes a predetermined macroinstruction, the CPU 5 reads the read data, updates the data transfer address, and updates the address specified by the microsequencer 4. If the bus transfer error is not eliminated by aborting and re-executing the micro-instruction of the micro-program for decoding and executing the macro-instruction, the above-described bus transfer is repeated up to a predetermined number of times.

The repetition count of the re-execution of the micro-instruction of the micro-program for decoding and executing the predetermined macro-instruction is:
For example, this is performed by executing the interrupt processing routine 3a stored in the microprogram memory 3 started after the occurrence of the bus transfer error.

Further, the interrupt processing routine 3a is configured such that each time it is activated, the value of the macro program counter 2 at the time of the current bus transfer error and the value of the macro program counter 2 at the time of the previous bus transfer error are set. By comparing the value with the value, it is determined whether or not there is a bus transfer error due to the execution of the same macro instruction, and only when it is determined that the same macro instruction has been executed, the microprogram for decoding and executing the macro instruction is executed. The number of re-executions of the microinstruction may be counted.

Further, even if the interrupt processing routine 3a re-executes the microinstruction of the microprogram for decoding and executing the macroinstruction causing the bus transfer error by the predetermined number of times, the bus transfer error is not eliminated. In this case, the transfer address of the data may be changed to a dummy address under which the bus transfer error under the control of the microprogram operating system does not occur, and the process may return.

In a case where processing such as increment / decrement of the counter 7 is performed simultaneously with the bus transfer operation in one microinstruction, the microinstruction output from the microprogram memory 3 is stored in a pipeline register. At the same time as latching to 6, a process such as increment / decrement of the counter 7 is executed (that is, although described by the same microinstruction,
Only processing such as increment / decrement of the counter 7 is executed one clock cycle ahead of the bus transfer operation. If a bus transfer error occurs during the execution of such a microinstruction, a microprogram control type processor further comprising storage means 8 for storing information such as a count operation for the counter 7 at that time. When an error occurs, the microinstruction stored in the storage means 8 is latched into the pipeline register 6 and, at the same time, the value of the counter 7 or the like is read based on the processed information such as the count operation. After returning to the previous state, the micro-instruction may be re-executed.

[Action]

CPU5 of the microprogram control type processor
If a bus transfer error occurs when a microinstruction of a microprogram that decodes and executes a predetermined macroinstruction is executed, the CPU 5 aborts the read data fetch operation and the update of the data transfer address, and the microsequencer 4 microprogram counter (μ
-PC) is also aborted, and after the retry control processing by the bus transfer error interrupt, the microinstruction of the microprogram for decoding and executing the predetermined macroinstruction is executed again in a state before the instruction execution. The re-execution of the bus transfer by the re-execution of the microinstruction is repeated up to a predetermined number of times if the bus transfer error is not eliminated.

In the retry control process by the bus transfer error interrupt, when it is determined that the retry has failed, the transfer instruction is changed to the operating system of the microprogram and the interrupt is returned, thereby forcibly executing the microinstruction without causing a bus error. You can get out.

When processing such as increment / decrement of the counter 7 is performed simultaneously with the bus transfer operation in one microinstruction, the microinstruction output from the microprogram memory 3 is transferred to the pipeline register 6.
At the same time as latching the counter 7 and executing the processing such as increment / decrement of the counter 7 (that is, although described by the same microinstruction, only the processing such as increment / decrement of the counter 7 is one clock cycle ahead of the bus transfer operation). If a bus transfer error occurs during the execution of such a microinstruction, information such as the count operation of the counter 7 at that time is stored in the storage means 8, and in the bus transfer error interrupt processing, After the values of the counter 7 and the like are returned to the state before the execution of the microinstruction based on the information such as the count operation stored in the storage unit 8, the microinstruction is executed again. Also in this case, the re-execution of the microinstruction is repeated a predetermined number of times.

As described above, when a bus transfer error occurs due to execution of a microinstruction of a microprogram that decodes and executes an arbitrary macroinstruction, the microinstruction is automatically repeated a predetermined number of times and a data transfer retry is performed. As described above, it is not necessary to provide a dedicated retry subroutine for each microprogram interpreter corresponding to various data transfer macro instructions. If no bus transfer error occurs, the next macro instruction can be executed immediately.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a system configuration diagram of a processor according to one embodiment of the present invention. In the figure, the same blocks as those shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The micro sequencer (μ-SQC) 150 includes an interrupt vector register 151 storing various interrupt vectors, and a PLR.
(Pipeline register) Branch operation instruction (BOP) output from 103, bus transfer error detection circuit 1
A branch control circuit 152 that decodes the bus error signal output from 20 and the signal output from the test condition selection circuit 109 and outputs various control signals, and a micro program memory (μ-MEM) 101 for a predetermined period (micro cycle) ), A microprogram counter (μ-PC) 153 for supplying the address, a microstack (μ-stack) 154 for stacking the value of the μ-PC 153 by a predetermined number of words, and an interrupt output from the interrupt vector register 151. Vector address, jump address output from pipeline register 103, macro program memory
The head address of the micro-imprinter (μ-imprinter) that decodes and executes the macro instruction output from 105, and the μ-output from μ-PC 153 and μ-stack 154.
A multiplexer 155 selects one of the addresses of the MEM 101 and supplies the selected signal to the microprogram memory 101 as an address signal.

In addition, the CPU 160 performs an arithmetic and logic operation on the data AD and the data BD output from the cache memory 161 by using an ALU.
(Arithmetic Logic Unit) 162, an input / output buffer 163 for outputting the output of the ALU 162 to the local data bus 600 and inputting / outputting data on the local data bus 600, AL
A multiplexer 164 for selecting either the output of the U162 or the output of the input / output buffer 163 and outputting it to the cache memory 161 and the bus error signal and the write signal WT for the cache memory 161 are added, and the bus error signal is activated. Sometimes, the write signal WT is prohibited from being output to the cache memory 161, and the gate 165 is configured to prohibit the write operation of the cache memory.

Further, when the bus error signal and the address latch enable signal ALE are added and the bus error signal is active, the output of the address latch enable signal ALE to the transfer address register 108 is inhibited, and the transfer address is latched in the event of a bus error. Gate 171 to be prohibited, bus error signal and program count enable signal PC
A gate 172 that prohibits the program count enable signal PCE from being output to the macro program counter MP106 when E is added and the bus error signal is active, and prohibits the MPC 106 from counting when a bus error occurs.
When the bus error signal and the operation permission signal are added and the bus error signal is active, the output of the operation permission signal to the various execution circuits 174 constituted by the register and the counter is prohibited, and the various execution circuits 174
And a gate 173 that prohibits the operation. The address signals A and B for the cache memory 161 are
Output from In addition, a control signal for the CPU 160
Are also output from the PLR 103.

In the embodiment of the above configuration, the operation of performing the bus transfer of data by decoding and executing the macro instruction by the μ-interpreter and the operation of detecting the bus error during the data transfer are as follows.
This is the same as the above-described conventional example, and a description thereof will be omitted. CP
U160 is instructed by a CPU control signal (CPUC) output from the PLR 103 to perform various operations / transfer controls, and write operations to the address signals A and B of the cache memory 161 and the cache memory 161.

When a bus error occurs, a bus error signal is output from the bus transfer error detection circuit 120, and writing of read data to the cache memory 161 is prohibited by the gate 165. The transfer address register 108 of the transfer address of the macro instruction to be executed next by the gate 171
Is prohibited, and M
The count operation of the PC 106 is prohibited. Further, the operation of the various execution circuits 174 is prohibited by the gate 173. Similarly, the μ-SQC 150 stores the value of the μ-PC 153 in the μ-stack 154 in a state where the count operation of the μ-PC 153 is prohibited and is not updated via the branch control circuit 152 in the μ-SQC 150. And the multiplexer 155 is
The interrupt vector register 151 is selected without selecting the MAP address of the macro instruction read from the macro program memory 105.
The address of the retry processing routine output from is selected and output to the μ-PC 153 and the μ-MEM 101. As a result, the retry processing routine stored in the μ-MEM 101 is executed. Also, as described above, when a bus error occurs, the value of μ-PC 153 that is not updated
Since the data is stored in the stack 154, when returning from the retry processing routine started by the bus error interrupt with a return instruction, the μ-address of the transfer instruction causing the bus error stored in the μ-stack 154 is stored. , The bus transfer can be retried again.

FIGS. 3 and 4 are flowcharts showing routines in the 32-bit and 16-bit bus transfer processes performed by the microprogram of the first embodiment, respectively.

Since the 32-bit read interpreter and the 16-bit read interpreter perform the MAP process simultaneously with their respective transfer operations, the macro instruction interpreter ends in one clock.

Next, FIG. 5 is a flowchart illustrating an interrupt process for retry control when a bus error occurs. Since the number of retries is assumed to be three, the following description is made on the assumption that "4" is initially set in the RTC before the flowchart of FIG.

In the first embodiment, the processing indicated by the broken-line rectangle
SC4 is not performed.

When a bus error occurs in the data transfer operation of the 32-bit read interpreter shown in FIG. 3, the multiplexer 155 causes the multiplexer 155 to retry the interrupt vector indicated by the interrupt vector corresponding to the bus transfer error stored in the interrupt vector register 151, as described above. The start address of the control processing routine is selected, and the start address is supplied to the μ-MEM 101, whereby the interrupt processing routine for retry control of data transfer shown in the flowchart of FIG. 5 is started.

In this interrupt processing routine, it is determined whether or not the current microprogram counter (hereinafter referred to as MPC) is equal to the previous MPC (SC
1) If equal, go to process SC2; if not equal, go to process SC
Move to 5.

 In process SC2, “1” is subtracted from RTC.

Next, it is determined whether the RTC is equal to “0” (SC3),
If the RTC is not equal to "0", a retry is performed by executing a 32-bit read of the interpreter shown in FIG. 3 by a return instruction (RET). If a bus error does not occur and the retry succeeds, the MAP to be executed simultaneously is executed. By the processing, the processing is continued to decode and execute the next macro instruction. Also,
If an error occurs again in the retry of the 32-bit read, the process shifts to the process SC1 again by the interrupt process.

Also, if the current MPC is not equal to the previous MPC in the above process SC1, the current MPC is cleared by the previous MPC to clear the retry control because it is not a bus transfer instruction by the interpreter of the microprogram that decodes and executes the same macro instruction. After storing in the MPC area (SC5), the RTC is initialized to "4" (SC6).

If the data transfer retry fails,
After the process of bit read → SC1 → SC2 → SC3 is repeated three times, the RTC becomes “0” in the above process SC3, and after starting the RAS process of the system management program (SC7), the dummy address of the microprogram operating system is changed. By storing the data in the transfer address register 108 and returning (SC8), the dummy transfer without causing a bus error is performed and the 32-bit data transfer microprogram step shown in FIG. Move to program processing by interruption.

In the 16-bit read, the transfer process of the 16-bit read interpreter shown in the flowchart of FIG. 4 and the interrupt process for retry control at the time of a bus error shown in the flowchart of FIG. Done. Also, in the read / write of other various bits and various transfer modes, execution of an interpreter for transferring the data and execution of an interrupt processing routine for retry control when a bus error occurs as shown in the flowchart of FIG. The same is done.

By the way, in the processor which executes the microinstruction (μ instruction) of the bus transfer accompanied by the operation simultaneously executed by latching the bus transfer instruction in the pipeline register, the first embodiment cannot completely abort. Hereinafter, a second embodiment corresponding to the case where such an operation is involved will be described.

FIG. 6 is a diagram showing a configuration of the CPU 180 of the second embodiment according to the present invention.

The data stack pointer (hereinafter referred to as DSP) 181 is
This is a pointer when the cache memory 182 is used in a stack structure, and is a microprogram memory (μ-ME
M) The microinstruction read from 191 is set in the pipeline register (PLR) 192, and at the same time, the μ-MEM191 is read.
The count-up / down operation is performed by the count enable signal CTE and the count-up / down signal UP / ▲ ▼ output from the CPU. The AND gate 183 is an AND gate that generates a count-up condition of the DSP 181 at the time of a bus error by using the count enable signal CTEX and the count-up / down signal UP / ▲ X output from the PLR 192. The output of the AND gate 183 is a JK flip-flop. (JK-F / F) 184 is stored.

The AND gate 185 is an AND gate for generating a countdown condition of the DSP 181 at the time of a bus error, and its output is stored in a JK flip-flop (JK-F / F) 186.

The command register (CMR) 187 stores the JK-F / F 184, 186 output from the ALU 188 by executing the microprogram.
Is a register for storing a command for clearing (resetting) the counter up / down information of the DSP 181 stored at the time of a bus error.

Subsequently, the CPU 180, μ-MEM191, and PLR192 having the above configuration
The operation of the second embodiment having the above will be described.

First, the operation when a bus error occurs when the operation of performing the count-up of the DSP 181 is performed at the same time as performing the bus transfer will be described with reference to the timing chart of FIG. Incidentally, when a bus error occurs due to the bus transfer, the abort operations of the microsequencer (μ-SQC) and the CPU 180 (not shown) are the same as those of the first embodiment shown in FIG.

As shown in the timing chart of FIG. 7, at the timing _A of the clock at the time T _A, the data transfer instruction output from the μ-MEM 191 is set in the PLR 192, and at the same time, the DSP 181 is also output from the μ-MEM 191. Count enable signal CTE and count up / down signal UP /
The count-up operation is performed by ▲ ▼, and the count value changes from “5” to “6”. If a bus error occurs when data is transferred at the timing B of the next clock, the count enable signal CTEX output from the PLR 192 and the count up / down signal UP / ▲ ▼
Since the X and the bus error signal become active, the count-up information of the DSP 181 at the time of the bus error is stored in the JK-F / F 184 via the gate 183. At this time, if the retry operation of the data transfer is performed in the same manner as in the first embodiment, the DSP 181 has already counted up and cannot be aborted. However, as shown in the flowchart of FIG. After it is determined in step SC3 of the interrupt processing routine that the RTC is not equal to "0", the JK shown in FIG.
-The processing of FIG. 8 for determining the presence or absence of the DSP 181 count-up command at the time of a bus error based on the output of the F / F 184 is performed.
By incorporating it as SC4, equivalent functions can be realized.

That is, in the flowchart of FIG. 8, JK-F /
Read the outputs of F184 and 186, and if there is a count-up command at the time of a bus error, decrement (subtract) the count value of DSP181 by "1" (SD2) and change the value of DSP181 before executing the data transfer instruction. And the output of JK-F / F184 is returned to the command register 187.
(SD5), the process returns to the execution of the transfer command of the original interpreter by the return command, and the retry is performed.

On the other hand, when the DSP 181 counts down simultaneously with the data transfer instruction, the gate 185 and the JK-F / F 186 read the outputs of the JK-F / F 184 and 186 at the time of a bus error in the same manner as described above, and Recognizing that the countdown command is present, the DSP 181 increments (increases) the count value of the DSP 181 by "1" (SD4), and can retry after returning the value of the DSP 181 to the count value before the execution of the data transfer instruction. As described above, when a bus error occurs, the DSP181
Can be returned before the data transfer is executed, and the retry processing can be performed.

Although the second embodiment is an example of counting up / down of the DSP 181, a bus error is also generated in a bus transfer microinstruction accompanied by various operations executed simultaneously with latching a bus transfer instruction into a pipeline register. A plurality of signals that memorize the operation at the timing of signal generation
By providing the F / F, it is possible to check the output of the F / F before retrying in the bus error interrupt processing, and to return the operation to before executing the data transfer.

〔The invention's effect〕

As described above, according to the present invention, when a bus transfer error occurs due to execution of a microinstruction of a microprogram for decoding and executing a macroinstruction for data transfer, the steps of the same microinstruction are repeated a predetermined number of times and re-executed. Therefore, it is not necessary to execute a step consisting of the same micro-instruction for determining a bus error after executing the micro-instruction for executing the transfer instruction in the interpreter. It can be decrypted and executed with a microprogram at high speed. In addition, for a plurality of macro instructions for data transfer in different modes, it is not necessary to prepare a retry subroutine for each macro instruction because retry is performed on the micro instruction of the micro program that decodes and executes each macro instruction. Therefore, the used capacity of the microprogram memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a system configuration diagram of a processor according to an embodiment, FIG. 3 is a flowchart illustrating a transfer process of a 32-bit read interpreter, and FIG. 5 is a flowchart illustrating a transfer process, FIG. 5 is a flowchart illustrating an interrupt process performed when a bus transfer error occurs, FIG. 6 is a circuit configuration diagram of a CPU according to a second embodiment of the present invention, and FIG. FIG. 8 is a timing chart illustrating the operation of the circuit of the processor that performs the line processing. FIG. 8 is a flowchart illustrating the operation of the processor that performs the pipeline processing when a bus transfer error occurs. FIG. 9 is a configuration example of a conventional processor. FIG. 10 (a) is a flowchart illustrating a conventional 32-bit read interpreter process, and FIG. 10 (b) is a conventional 32-bit read interpreter process. FIG. 11 (a) is a flowchart illustrating processing of a conventional 16-bit read interpreter, and FIG. 11 (b) is a flowchart illustrating processing of a conventional 16-bit read interpreter. 6 is a flowchart for explaining the processing of FIG. 1,105 macro program memory, 2,106 macro program counter, 3,101,191 micro program memory, 3a interrupt processing routine, 4,150,102 micro sequencer, 5,104,160,180 ... CPU, 6,103,192 pipeline register (PLR), 7: Counter, 8: Storage means, 107: Physical address generation circuit, 108: Transfer address register, 109: Test condition selection circuit, 120: Bus transfer error detection circuit, 121: Bus parity checker / Generator 122 Bus access time monitoring circuit 123 Slave device abnormality signal determination circuit 151 Interrupt vector register 152 Branch control circuit 153 Microprogram counter (μ-PC) 154 … Micro stack (μ-stack), 155 …… Multiplexer, 161,182 …… Cache memory , 162, 188… ALU, 163… Data I / O buffer, 164… Mux, 165… Cache memory write inhibit and gate at bus error, 171… Address latch inhibit and gate at bus error 172: MPC count prohibition AND gate at bus error 173: Various register operation prohibition AND gate at bus error 174 Various execution circuits 181 Data stack pointer 183,185 AND gate 184,186 JK −F / F, 187 …… Command register.

Claims (5)

(57) [Claims] A macro program memory (1) for storing a macro program, said macro program memory (1)
Macro program counter (2) for specifying the address of the micro program memory (3) for storing the micro program, micro sequencer (4) for specifying the address of the micro program memory (3), the micro program memory (3) CPU that operates based on microinstructions read from
In the retry control method of data transfer in the processor having (5), when a bus transfer error occurs due to execution of a microinstruction of a microprogram that decodes and executes a predetermined macroinstruction, the CPU (5) reads the read data. Aborting the update of the data transfer address and the update of the address designated by the microsequencer (4), and re-executing the microinstruction of the microprogram for decoding and executing the predetermined macroinstruction, thereby executing the bus transfer. A retry control method for data transfer, wherein the re-executing process is repeated up to a predetermined number of times if a bus transfer error is not eliminated. 2. The method according to claim 1, wherein the counting of the number of re-executions of the micro-instruction of the micro-program for decoding and executing the predetermined macro-instruction is performed by an interrupt process stored in the micro-program memory started after a bus transfer error occurs. 2. The data transfer retry control method according to claim 1, wherein the retry control is performed by executing a routine (3a). Each time the interrupt processing routine (3a) is started, the value of the macro program counter (2) at the time of the current bus transfer error and the value of the macro program counter (2) at the time of the previous bus transfer error are determined. A micro-program for decoding and executing the macro instruction only when it is determined that there is a bus transfer error due to the execution of the same macro instruction, and only when it is determined that the same macro instruction has been executed. 3. The data transfer retry control method according to claim 2, wherein the number of re-executions of the micro instruction is counted. 4. The interrupt processing routine according to claim 1, wherein the bus transfer error is not resolved even if the microinstruction of the microprogram for decoding and executing the macroinstruction causing the bus transfer error is re-executed the predetermined number of times. The microprogram
4. The data transfer retry control method according to claim 3, wherein the operation is changed to a dummy address under which a bus transfer error under the control of the operating system does not occur and the operation is restored. 5. When performing a process such as increment / decrement of a counter (7) simultaneously with a bus transfer operation in one microinstruction, the microinstruction output from the microprogram memory (3) is transferred to a pipeline register (3). Latch to 6) and counter (7)
And a storage means (8) for storing information such as a count operation for said counter (7) when a bus transfer error occurs during execution of a microinstruction for executing processing such as increment / decrement. When the bus transfer error occurs, the value of the counter (7) or the like is returned to the state before the execution of the microinstruction based on the information such as the count operation stored in the storage means (8). 5. The data transfer retry control method according to claim 1, wherein the microinstruction is re-executed thereafter.