JPH04353923A - Parallel instruction execution system for electronic computer - Google Patents

Abstract

PURPOSE:To execute instructions in parallel without complicating the hardware of a control part decoding the instruction and issuing the instruction. CONSTITUTION:A compiler searches a continuous integer operation instruction and a floating point arithmetic instruction, which do not use the same register, among object codes obtained by compiling a source program. If such an instruction string exists, the prescribed instruction including the number of the instructions is inserted before the instruction string for executing the instructions in parallel. When the prescribed instruction is received from a buffer, a unit 2 extracts the number of the instructions and informs a unit 3 of it. The unit 3 receives the informed number of the instructions from a buffer 1 and an integer operation unit 6 and a floating point arithmetic unit 7 are made to execute them in parallel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for executing instructions in parallel in an electronic computer.

0002

2. Description of the Related Art Conventional electronic computers that execute instructions in parallel judge whether or not multiple instructions can be executed while being aware of competition for hardware resources when executing instructions. For example, in an electronic computer that has one integer arithmetic unit and one floating point arithmetic unit, if two consecutive instructions are an integer arithmetic instruction and a floating point arithmetic instruction, the two
Two instructions can be executed in parallel, but if two consecutive instructions are both integer arithmetic instructions or floating point arithmetic instructions, contention for the arithmetic unit will occur, so only one instruction can be executed at a time. Can not. Therefore, before executing an instruction, it is necessary to determine whether multiple instructions can be executed in parallel, and conventionally, this determination has been made by hardware.

0003

[Problems to be Solved by the Invention] In conventional electronic computers, the ability to execute multiple instructions in parallel was determined by hardware, so the amount of hardware required for the control unit that decodes and issues instructions (dispatch) The number of circuits increases, and the circuit delay in that part becomes large. Therefore, there is a problem in that it is not possible to shorten the period of the basic clock, and it is not possible to increase the speed. Furthermore, if the number of instruction execution units that execute instructions in parallel increases further, the processing for determining whether parallel execution is possible will become complex, and it is expected that it will be difficult to perform this process using hardware. Ru.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel instruction execution method for an electronic computer that solves these problems and enables parallel execution of instructions without complicating the hardware of a control unit that decodes and issues instructions. Our goal is to provide the following.

[0005]

[Means for Solving the Problems] The present invention is a parallel instruction execution method for an electronic computer that is equipped with a plurality of instruction execution units and executes a plurality of instructions in parallel, in which a string of instructions is generated and can be executed in parallel. a compiler means for inserting a predetermined instruction including information on the number of instructions that can be executed in parallel before an instruction string consisting of a plurality of instructions; and a storage means for holding the instruction string generated by the compiler means. , a parallel information decoding unit that outputs predetermined information indicating the number of instructions that can be executed in parallel based on the information on the number of instructions included in the instruction when the predetermined instruction is received from the storage means; When the predetermined information is received from the decoding unit, the same number of instructions as the information indicates is received from the storage means, and the instructions are issued to the plurality of instruction execution units to execute each instruction in parallel. It is characterized by having a unit.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the main parts of an example of an electronic computer based on the parallel instruction execution system of the present invention. In this embodiment, for simplicity, it is assumed that the instruction execution unit includes one integer arithmetic unit and one floating point arithmetic unit. The compiler of this electronic computer has the following functions. That is, the compiler searches for consecutive integer arithmetic instructions and floating point arithmetic instructions that do not use the same register in the object code obtained by compiling the source program. If such a sequence of instructions exists, an instruction as shown in FIG. 2 is inserted before the sequence of instructions in order to execute those instructions in parallel. In other words, the first four bits of the instruction code part are all "4", and the lowest four bits are "0010".
Insert an instruction that is . The lowest 4 bits indicate that the following two instructions can be executed in parallel. It is assumed that the instruction code "1111" is originally an undefined instruction code in this electronic computer.

In FIG. 1, 6 is an integer operation unit, 7
is a floating point arithmetic unit, and 1 is an instruction buffer that holds object code obtained by compiling a source program by a compiler. The parallel information decoding unit 2 receives an instruction from the instruction buffer 1 through the instruction transmission means 4, and when the instruction code is the above-mentioned undefined instruction code, extracts the number of instructions included in the instruction that can be executed in parallel. , and notifies the unit 3 through the transmission means 5.

The instruction decode issue unit 3 receives and decodes instructions from the instruction buffer 1, and sends the instructions to units 6,
The command word and operand data are transmitted to 7 through the transmission means 8. When the number of instructions that can be executed in parallel as notified by unit 2 is 2, two consecutive instructions are received from buffer 1 and units 6 and 7 execute them in parallel. Note that the unit 3 has a built-in register file, and operand data necessary for calculations is extracted from the register file.

Next, the operation will be explained. First, three instructions as shown in FIG. 3(A) are transferred from instruction buffer 1 to unit 2.
, 3 will be explained. However, the n-th instruction (shaded area) in the figure is the instruction in FIG. 2, the n+1-th instruction is an integer arithmetic instruction, and the n+2-th instruction is a floating-point arithmetic instruction. When unit 2 receives this n-th instruction from the buffer, all 4 bits of its instruction code part are "1", so it calculates "2" as the number of consecutive instructions that can be executed in parallel using the lowest 4 bits. extract it and notify it to unit 3.

When unit 3 receives this notification, it receives the n+1st and n+2nd instructions from buffer 1, and
Operand data necessary for the operation is taken out from the built-in register file and outputted to the transmission means 8 together with the instruction word as the result of decoding the instruction. As a result, the (n+1)th integer operation instruction and the (n+2)th floating point instruction are executed simultaneously, and units 6 and 7 respectively execute integer operation and floating point operation based on the given operand data.

On the other hand, when the instruction sequence shown in FIG. 3(B) is given from buffer 1 to unit 2, since no undefined instructions are inserted, unit 2 uses 1 as the number of instructions that can be executed in parallel. Notice. Therefore, in this case, the unit 3 first receives the nth integer operation instruction from the buffer 1, decodes it, outputs the integer operation instruction word and operand data to the unit 6, and causes the unit 6 to execute the integer operation,
Next, the (n+1)th integer operation instruction is received, and the unit 6 is caused to execute the integer operation again.

0012

[Effects of the Invention] As explained above, in the electronic computer based on the parallel instruction execution method of the present invention, the compiler means
When parallel execution of instructions is possible, a predetermined instruction including information on the number of instructions that can be executed in parallel is inserted into the instruction string, and when the parallel information decoding unit receives the above predetermined instruction, it Based on the number information included in the instructions, the instruction decode issue unit is notified of the number of instructions that can be executed in parallel, and the instruction decode issue unit receives the notified number of instructions and sends them to multiple instruction execution units simultaneously. Execute commands. That is, in an electronic computer based on the parallel instruction execution method of the present invention, the number of instructions that can be executed in parallel is determined by the compiler means, so the instruction decode issuing unit does not need to have a function for this purpose, and therefore its hardware is not complicated. It will never become. In addition, even when there are a large number and types of instruction execution units and it is necessary to judge whether instructions can be executed in parallel based on more complex conditions,
By the method of the present invention, parallel execution of instructions can be easily realized. Furthermore, if the predetermined command is configured by an undefined command code, there is no need to change the command system, so compatibility can be ensured.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an electronic computer based on the parallel instruction execution method of the present invention.

FIG. 2 is a diagram showing the structure of instructions used in the electronic computer of FIG. 1;

FIG. 3 is a diagram showing an example of an instruction sequence for operating the electronic computer of FIG. 1;

[Explanation of symbols]

1 Instruction buffer 2 Parallel information decoding unit 3 Instruction decode issuing unit 4, 5, 8 Transmission means 6 Integer calculation unit 7 Floating point arithmetic unit

Claims (3)

[Claims] Claim 1: In a parallel instruction execution method for an electronic computer that is equipped with a plurality of instruction execution units and executes a plurality of instructions in parallel, an instruction string is generated and the instruction string is made up of a plurality of instructions that can be executed in parallel. a compiler means for inserting a predetermined instruction including information on the number of instructions that can be executed in parallel before the above; a storage means for holding the instruction string generated by the compiler means; a parallel information decoding unit that outputs predetermined information indicating the number of instructions that can be executed in parallel based on the information on the number included in the instruction when an instruction is received; and an instruction decode issuing unit which receives the same number of instructions from the storage means as the number indicated by the information and issues them to the plurality of instruction execution units to execute each instruction in parallel. A parallel instruction execution method for electronic computers. 2. The parallel instruction execution method for an electronic computer according to claim 1, wherein the predetermined instruction is composed of an instruction code in which a specific function is not defined. 3. The parallel instruction execution system for an electronic computer according to claim 1, wherein the plurality of instruction execution units include an integer arithmetic unit and a floating point arithmetic unit.