JPH05233283A - Parallel instruction execution system - Google Patents

Abstract

PURPOSE:To provide a computer capable of attaining parallel instruction execution without increasing the hardware capacity of a decoding part while maintaining interchangeability with an existing computer. CONSTITUTION:This system includes a compiler for storing information relating to the control of parallel instruction execution in an object code by using an undefined instruction word and a parallel information decoding unit 2 extracts parallel execution information from an undefined instruction word and decodes it. An instruction decoding issuing unit 3 issues single or plural instructions to an execution unit based upon the information. A branch instruction execution unit 8, an integer arithmetic unit 9 and a floating point arithmetic unit 10 execute arithmetic based upon the instructions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel instruction execution system for a computer, and more particularly to an instruction dispatch system for issuing a plurality of instructions to an arithmetic execution unit.

[0002]

2. Description of the Related Art Conventionally, in a computer that executes a plurality of instructions in parallel while maintaining compatibility with existing computers, it is determined whether or not a plurality of instructions can be executed while paying attention to hardware resource competition when the instructions are executed. Was.

[0003]

In a conventional computer that executes a plurality of instructions, as described above, whether or not a plurality of instructions can be executed in parallel is determined by hardware when the instructions are executed. Therefore, instruction decoding and instruction issuance are required. The amount of hardware of the control unit that performs (dispatch) increases, and the circuit delay in that part increases, which causes a problem in shortening the basic clock cycle. For example, in a computer having one integer arithmetic unit and one floating point arithmetic unit,
If two consecutive instructions are an integer operation instruction and a floating point operation instruction, the two instructions can be executed in parallel. However, if two consecutive instructions are both integer instructions or floating point instructions, there is contention on the arithmetic unit and only one instruction can be executed at the same time.

In order to make such a judgment by hardware at the time of executing an instruction, its control section becomes complicated. Further, when the number and types of arithmetic units are increased, it may be impossible for hardware to sufficiently judge the possibility of parallel instruction execution. It is an object of the present invention to provide a parallel instruction execution system that can improve the efficiency of use of arithmetic units and execution units and improve the instruction execution performance of the entire computer.

[0005]

In order to achieve the above object, a parallel instruction execution system according to the present invention has a plurality of instruction execution units and can execute a plurality of instructions in parallel.
In a computer that is compatible with the instruction set of an existing computer, it is included in the information that indicates which subsequent instruction can be executed in parallel and the multiple instructions that can be executed in parallel according to the analysis result at the time of compilation. Information that specifies which instruction execution result of a plurality of instructions that can be executed in parallel when the condition of the conditional branch instruction is not satisfied and the instruction word that is undefined in the existing computer are A parallel instruction execution analysis coiler to be stored therein, a parallel instruction execution control register for setting a value with a special instruction, and a signal for enabling or disabling the parallel instruction execution control is output by the parallel instruction execution control transmission means, and the parallel instruction execution control register. The signal from the instruction execution control transmission means is input, the undefined instruction word is decoded according to this signal, the two types of control information relating to parallel instruction execution are decoded, and the result is obtained. A parallel information decode unit for outputting a parallel instruction issue signal and an instruction cancel signal, an instruction decode issue unit for issuing a single or a plurality of instructions to the instruction execution unit according to the parallel instruction issue signal, the instruction cancel signal, and The instruction execution unit can cancel the operation result according to the execution result of the conditional branch instruction. The instruction execution unit may be composed of a branch instruction execution unit, an integer arithmetic unit, and a floating point arithmetic unit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a parallel instruction execution system according to the present invention. In this embodiment, for simplification of description, an example of a computer equipped with one branch instruction execution unit, one integer arithmetic unit and one floating point arithmetic unit will be described. The maximum number of instructions that can be executed in parallel is three.

The instruction buffer 1, the parallel information decoding unit 2, and the instruction decoding issuing unit 3 are included, and the instruction word is transmitted from the instruction buffer 1 by the instruction transmitting means 4 to the parallel information decoding unit 2 and the instruction decoding issuing unit 3.
Is output to. If the instruction word input from the instruction transmitting means 4 is undefined in the existing computer, the parallel information decoding unit 2 extracts the subsequent parallel executable instruction and instruction execution cancel designation information from the existing instruction word and outputs the number of parallel executable instructions. Is transmitted to the instruction decode issuing unit 3 by the parallel instruction issue signal 5, and the instruction execution cancel designation is transmitted to various execution units by the instruction cancel signal 6.

The instruction decode issuing unit 3 transmits the instruction word to the branch instruction executing unit 8, the integer arithmetic unit 9 and the floating point arithmetic unit 10 by the instruction transmitting means 7. Information on whether or not the condition determined by the conditional branch instruction in the branch instruction execution unit 8 is satisfied is transmitted to the integer arithmetic unit 9 and the floating point arithmetic unit 10 by the conditional branch signal 11. In the integer arithmetic unit 9 and the floating point arithmetic unit 10, according to the instructions of the instruction cancel signal 6 and the conditional branch signal 11, the execution result is canceled without storing the operation result in a register or the like if necessary. The contents of the parallel instruction execution control register 12 are transmitted to the parallel information decoding unit 2 by the parallel instruction execution control transmission signal 13.

In the instruction set of the existing computer for which the computer of this embodiment is to maintain compatibility, it is assumed that an instruction code is at the beginning of the instruction word and the instruction word of which the first 4 bits are all 1 is undefined. .. A parallel instruction execution analysis compiler included in the scope of the present invention compiles a source program, and as a result, parallel executable branch instructions and integer operation instructions that do not conflict with each other in computer resources such as instruction execution units and registers in the object code. And search for floating-point arithmetic instructions that are not consecutive. If they are consecutive, in order to execute those instructions in parallel, insert an undefined instruction in which the first 4 bits are all 1's in front of the instruction sequence, and further in the least significant 4 bits of the instruction word. Write the number of instructions that can be executed in parallel. For example, 0011 indicates that the following three instructions can be executed in parallel.

2 and 3 are diagrams showing an instruction sequence and undefined instructions showing this state. In FIG. 2, the instructions from addresses n to n + 2 have independent instruction execution units for integer instructions, floating point instructions, and branch instructions, so that the arithmetic units do not compete with each other. If resources such as registers do not compete, they can be executed in parallel. In this case, the compiler generates an undefined instruction word as shown in FIG. In this embodiment, an instruction string in which an undefined instruction word comes first and which can be executed in parallel is called an instruction block. FIG. 4 shows instruction blocks generated by the compiler for the instruction words from address n to address n + 2 in FIG.

An example of canceling the execution result of another instruction included in the instruction block when the condition of the conditional branch instruction is not satisfied is shown in FIGS. 5, 6 and 7. The figure shows an example of an instruction word, and a portion enclosing a plurality of instruction words with a dotted line represents an instruction block that can be executed in parallel. Here, the undefined instruction word at the head of the instruction block is not described. The example of FIG. 5 shows the state of the instruction block when there is no cancel function. The instruction block 2 is composed of one branch instruction without any instruction that can be executed in parallel.
Therefore, in the example of FIG. 5, it is necessary to execute four instruction blocks from the instruction block 1 until the condition of the instruction block 2 is satisfied and then the instruction block 3 to the instruction block 4 is reached.

On the other hand, in the computer having the function of canceling the execution of the other instruction included in the instruction block when the branch is not taken by the conditional branch instruction as in the present embodiment, as shown in the example of FIG. The instruction block 2 and the instruction block 3 shown in FIG. 5 can be combined into one. The instruction block 3 of FIG. 5 is executed only when the condition of the branch instruction of the instruction block 2 is satisfied. Therefore, by using the execution cancel function of this embodiment, the instruction block 3 in FIG.
Can be included in instruction block 2. By doing so, the instruction blocks 1 to 4 can be executed by three instruction blocks. Since the instructions contained in the instruction block can be executed in parallel,
One instruction block can be executed in one machine cycle. Therefore, FIG. 6 can execute the same instruction in a time shorter than that of FIG. 5 by one machine cycle.

The compiler of this embodiment generates an instruction block as shown in FIG. 7 as an object code for the new instruction block 2 of the instruction string shown in FIG. Here, in the field of execution cancellation designation of the undefined instruction word at the beginning,
If the condition of the conditional branch instruction is not established, a bit string of 011 is inserted, which means that the execution results of the second and third instructions are canceled. Each bit string of this 3-bit length corresponds to an instruction word that can be executed in parallel (maximum 3 instructions can be executed in parallel in this embodiment) included in the instruction block, and if the value of the bit is 1, , If the condition of the conditional branch instruction included in the instruction block is not satisfied, the execution result of the corresponding instruction word is canceled. When it is 0, the execution result of the instruction is not canceled. If the condition is not satisfied in the instruction block of FIG. 7, the execution of the integer instruction and the floating point included in the instruction block is canceled.

The parallel instruction execution method according to the present invention issues an instruction to an execution unit using the instruction block of FIG. 7 as an example. In this embodiment, the command transmission means 4
Outputs four consecutive instructions starting from the instruction to be executed next to the parallel information decoding unit 2 and the instruction decoding issuing unit 3. First, assume that the value of the parallel instruction execution control register 12 is set to 1. In this case, parallel instruction execution is enabled.
The parallel information decoding unit 2 decodes the undefined instruction A at the head of the instruction block in FIG. 7 and reads “The following instruction can be executed in parallel, and the length of the instruction sequence that can be executed in parallel is 3 (from B to B in FIG. 7). 3 instructions of D), of which the second and third instructions cancel the operation result when the conditional branch is not satisfied. "With parallel instruction issue signal 5 and instruction cancel signal 6 It is transmitted to the unit 9 and the floating point arithmetic unit 10. Since the instruction execution result in this unit in the branch instruction execution unit 8 is not canceled by the branch condition, the instruction cancel signal 6 transmits the cancellation designation only to the integer arithmetic unit 9 and the floating point arithmetic unit 10.

In the command decort issuing unit 3, B to D are read from the command sequence input by the command transmitting means 4 accordingly.
3 instructions are taken out and decoded, and the decoding result is outputted to the branch instruction execution unit 8, integer operation unit 9 and floating point operation unit 10 by the instruction transfer means 7. Figure 7
Branch instruction B of branch instruction execution unit 8 to integer instruction C
Is output to the integer arithmetic unit 9 and the floating point instruction D is output to the floating point arithmetic unit 10. In this way, three instructions are simultaneously issued to the arithmetic units and executed in parallel.

The branch instruction execution unit 8 judges the condition of the branch instruction and transmits the result to the integer arithmetic unit 9 and the floating point arithmetic unit 10 by the conditional branch signal 11.
In the integer arithmetic unit 9, the instruction cancel signal 6 cancels the instruction operation result of C when the condition is not satisfied. The floating point arithmetic unit 10 instructs the instruction cancel signal 6 to cancel the instruction operation result of D when the condition is not satisfied. Therefore, if the condition is not satisfied by the conditional branch signal 11, each unit cancels the execution of the instruction without storing the operation result in the register. If the condition is met, the operation result is stored and the result survives.

Next, consider the case where the value of the parallel instruction execution control register 12 is 0. In this case, parallel instruction execution is invalidated. The parallel information decoding unit 2 knows that the parallel instruction execution is disabled by the parallel instruction execution control transmission signal 13, and ignores the parallel execution information embedded in the undefined instruction word and issues a parallel instruction execution instruction. Not transmitted by signal 5 and instruction cancel signal 6. In this case, the undefined instruction word is ignored, and the other instructions are sequentially executed one by one without being executed in parallel. This invalidation control function is used when debugging the hardware of this computer. When the instructions input to the parallel information decoding unit 2 and the instruction decode issuing unit 3 do not include undefined instructions, the instructions are sequentially executed one by one regardless of the contents of the parallel instruction execution control register.

[0018]

As described above, according to the present invention, the compiler determines whether the succeeding instruction sequence can be executed in parallel, and if so, which instruction can be executed in parallel, and stores the result in the instruction sequence. Therefore, it is possible to issue a plurality of instructions that can be executed in parallel to the arithmetic unit without complicating the hardware of the instruction decoding unit.
Further, in this method, it is possible to search for an instruction that can be executed in parallel including the instruction word subsequent to the branch instruction, so that the usage efficiency of the arithmetic unit is improved and the instruction execution performance of the entire computer can be improved.

In the present invention, since the parallel instruction execution information can be stored by using the undefined instruction word of the existing computer, it is possible to realize the computer which can execute the parallel instruction while maintaining the compatibility with the conventional computer. Further, in the present invention, since the carpilla determines the parallel executability of the instruction sequence, it is necessary to determine the parallel executability under more complicated conditions, for example, the number of instructions that can be executed in parallel and the number of operation units are large. This method can be applied to a computer with a configuration.

According to the present invention, the result of the instruction executed in parallel can be canceled according to the condition judgment of the conditional branch instruction. As a result, even in the case shown in FIG. 5 and FIG. 6 of the present embodiment, the compiler can find and fill the instruction block with the instructions that can be executed in parallel, and improve the use efficiency of the execution unit and improve the performance. You can

The function corresponding to the parallel instruction execution control register included in the present invention, that is, the function by which the computer user can easily enable and disable the parallel instruction execution under software control can execute the parallel instruction execution as in the present invention. This is a very effective function for efficient software development in a computer that realizes. In particular, it is an indispensable function in the computer for building the recent open system environment where independent software vendors develop programs.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a parallel instruction execution system according to the present invention.

FIG. 2 is a diagram showing an example of an instruction sequence.

FIG. 3 is a diagram showing an example of an undefined instruction word including parallel instruction execution information.

FIG. 4 is a diagram showing an example of an instruction block capable of executing a parallel execution instruction.

FIG. 5 is a diagram showing an example of a cancel instruction branch instruction, showing a state of an instruction block when there is no cancel function.

FIG. 6 is a diagram showing an example of a cancel designation branch instruction, showing a state of an instruction block when there is a cancel function.

FIG. 7 is a diagram showing an example of an instruction block with a cancel designation.

[Explanation of symbols]

 1 ... Instruction buffer 2 ... Parallel information decoding unit 3 ... Instruction code issue unit 4,7 ... Instruction transmission means 5 ... Parallel instruction issue signal 6 ... Instruction cancel signal 8 ... Branch instruction execution unit 9 ... Integer operation unit 10 ... Floating point Arithmetic unit 11 ... Conditional branch signal 12 ... Parallel instruction execution control register 13 ... Parallel instruction execution control transmission signal

Claims (2)

[Claims] 1. A computer having a plurality of instruction execution units, capable of executing a plurality of instructions in parallel, and compatible with the instruction set of an existing computer, according to the analysis result at the time of compilation, Information about which instruction can be executed in parallel, and which of the multiple instructions that can be executed in parallel when the condition of the conditional branch instruction included in the multiple instructions that can be executed in parallel is not satisfied. Information that specifies whether to cancel the execution result,
Parallel instruction execution analysis coiler that is stored in the instruction word that was not defined in the existing computer, and a value that can be set with a special instruction, and a signal that enables or disables parallel instruction execution control is transmitted. Means for outputting the parallel instruction execution control register and a signal from the parallel instruction execution control transmitting means, decode the undefined instruction word according to this signal, decode the two types of control information relating to parallel instruction execution, and A parallel information decoding unit that outputs a result as a parallel instruction issue signal and an instruction cancel signal; an instruction decode issue unit that issues a single or multiple instructions to the instruction execution unit according to the parallel instruction issue signal; and the instruction cancel signal. And an instruction execution unit that can cancel the operation result according to the execution result of the conditional branch instruction. Parallel instruction execution method, characterized in that configuration was. 2. The parallel instruction execution system according to claim 1, wherein the instruction execution unit comprises a branch instruction execution unit, an integer arithmetic unit, and a floating point arithmetic unit.