JPS6250934A - Interrupting control system of processor - Google Patents

Abstract

PURPOSE:To stop the processing, to generate the interruption, to prevent the changing of the program level, to resume the instruction by the return instruc tion and to execute the processing when the request of the priority level higher than the present program level is detected by the interrupting request from the external part on the way of the execution of the instruction. CONSTITUTION:A work register 65 of an arithmetic unit 6 decides whether or not a priority interrupting existing signal 14 is on. As the result, when it is detected that the interruption with the priority level higher than the present program occurs at the time of on, namely, on the way of the sequence, the first code different from the code by the interruption after the instruction is completed is saved to the main memory device, and the value provided for the interruption is set to a program counter 21. The program level is unchanged, the execution of the present instruction is completed, the execution of the next instruction is started and after the interruption is executed by the program of the branching destination, the return instruction is executed. Thus, the identifi cation code popped from the staff is decided, in case of the first code, the interrupting result saved at the main memory device is recovered, and the processing is resumed from the way of the execution of the instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an interrupt control method for a processing device, and particularly relates to an interrupt during execution of an instruction.

[Background of the invention]

In order to execute character processing and list processing at high speed, these processes are sometimes implemented in firmware, but in this case, since the execution time of one instruction is extremely long, it is necessary to insert an interrupt in the middle of instruction execution. If this is not possible, responsiveness to the outside world will decline.

A known example 1rV is a method for realizing interrupts during instruction execution.
AX 11 Architecture Handb
ookJ and known example 2 "US Patent No. 3401375"
There is a method described in

The relevant part of the known example will be briefly explained. First, for general interrupts, as shown in Figure 2 (a) and Figure 2 (b), when there is an interrupt request, the program counter and program level are switched at the end of the instruction to respond to the interrupt. After processing is completed, the program counter and program level are restored. On the other hand, VAXII Architecture Hand
Procedure described in book P 52 e P 53
In ssor 5tatus Longword, F
By providing a P D (First Part Done) flag and controlling it as shown in FIGS. 3(a) and 3(b), it is possible to interrupt during instruction execution.

However, in this method, intermediate results of repetitive processing are stored using general-purpose registers, so the contents of several of the only 16 general-purpose registers are destroyed by execution of an instruction that includes repetitive processing. Therefore, since general-purpose registers are used for other purposes, it is necessary to save the contents of registers that may be destroyed before executing an instruction that involves repeated processing, and restore the contents after the execution of the same instruction. The disadvantage is that unnecessary processing must be performed.

Furthermore, these instructions do not always take a long time to execute; search, pattern matching, etc. often take a short time to execute, and the time taken up by saving and restoring takes up a large proportion of the time.

Specifically, if you use these instructions to transfer, for example, 16 bytes, and one memory access reads or writes 4 bytes, you will need 4 register save accesses and 4 memory accesses for the original purpose. 8 times and 4 accesses for register recovery, 50% of the time is actually spent saving and restoring the register 9 times.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to realize an interrupt in the middle of instruction execution that alleviates the drawbacks of the conventional example.

[Summary of the invention]

According to the present invention, when the presence or absence of an external interrupt request with a higher priority level than the current program level is detected in the middle of instruction execution, the process is restarted and an interrupt is generated in the middle of instruction execution. In this case, the program level remains unchanged, so the interrupt request is processed as a normal interrupt at the interrupt destination, and after processing, the execution of the instruction is resumed from the point where the instruction was executed by two return instructions. shall be.

FIG. 1(a) and FIG. 1(b) schematically show the control method of the present invention.

The opening in the figure shows processing by one macroinstruction, and the others show processing by microinstructions.

[Embodiments of the invention]

Examples of the present invention will be described below.

FIG. 4 shows a schematic configuration of the basic processing mechanism 2. As shown in FIG.

The system bus interface control mechanism 3 controls data transfer with the main memory and input/output devices via the system bus 1. The instruction decoding unit 4 decodes the macroinstruction and generates a microinstruction start address.

The arithmetic control system 5 controls microinstructions. The arithmetic unit 6 is controlled under microinstructions and performs the actual arithmetic operations.

FIG. 5 shows the configuration of the instruction decoding unit 4.

A program counter (PC) 21 points to the address in main memory of the macro instruction to be decoded. The selector 22 selects the next PC, and when branching, selects the value passed from the B input section or arithmetic unit, and otherwise selects the output result of the incrementer 23. The read macro instruction is set in the instruction buffer register 24, and its output is decoded by the instruction decoder 25 and corresponds to the macro instruction. Microprogram starting address 3
1 is generated. On the other hand, for the interrupt request signal 7 from the system bus, the highest interrupt level is calculated by the concoder 28. The result 32 and the fixed pattern 27 are combined to generate the starting address 33 of a microprogram that performs interrupt processing.1 The interrupt level 32 and the program level 30 are compared by a comparator 29, and the output 14 is on when the interrupt level is higher than the program level and interrupts should be accepted, and off otherwise.

The selector 26 selects the interrupt start address 33 when the priority interrupt presence signal 14 is on, selects the macro instruction start address 31 when it is off, and selects the microprogram start address 13 for the next process. It is said that This mechanism is
Used to insert an interrupt at the end of a macro instruction.

Furthermore, the priority interrupt presence signal 14 is output to the arithmetic control system 2, and is used for interrupts during instruction execution, which is the key point of the present invention.

FIG. 6 shows the configuration of the arithmetic control system 5, and the microprogram is stored in the control memory 44.

A microprogram counter (MPC) 42 indicates the address in the control memory 44 of the next microinstruction to be executed.The selector 41 selects the next MPC. When branching at the starting address 13 based on the calculation result, the output data 16 of the calculation unit is used.

When executing a branch microinstruction, part of the microinstruction 48
When proceeding to the microinstruction at the next address, the output of the incrementer 43 is selected. The next address control system 46 controls the selector 41 based on the part 49 of the microinstruction and the condition fulfillment signal 50. The selector 47 is a selector for condition judgment, and selects which signal is selected by the part 51 of the microinstruction. or control. The priority interrupt presence signal 14 is input to one of the selectors 47, and the microinstruction can determine whether this signal is on or off.

FIG. 7 shows a 5 selector 61 showing the configuration of the arithmetic unit 6.
is program counter 10 program level 12. Any one of the system bus read data 9° microinstruction portions 15 can be selected and placed on the input bus 62. General-purpose register (GRO-GR7) 64 for macro instructions
Or a work register for microinstructions (WKO-W
The output of K7) 65 can be placed on input bus 62 or input bus 63. The arithmetic unit 66 inputs the input bus 62 and the input bus 63, and outputs the calculation result to the output bus 16. This bus includes general purpose registers (GRO to GR7) 64. '
7-Creister (WKO to WK7) 65 and is also connected to other units.

Figure 8 shows macro instructions (character processing instructions,
In steps 101 and 102, the operand is set to the work register WKI.

Set to WK2. This microprogram is WKI
, WK2 as a pointer, steps 103 to 105 are repeatedly executed while updating them, and when a certain condition is met, the program exits to step 106 and ends the instruction execution. In step 103, it is determined whether the priority interrupt presence signal 14 is on, and when it is detected that it is on, that is, an interrupt with a higher priority level than the current program level has occurred in the middle of an instruction, the process proceeds to step 107. In step 107, the address 1003 in step 104 is set in WK7 as the return microinstruction address. Actually, the constant part 15 of the microinstruction in step 107 (see Figure 4) is set to the pattern 1003,
Selector 61. It is set to WK7 through the arithmetic unit 66 (see FIG. 7). At step 108, the process branches to the instruction mid-instruction interrupt processing microprogram correction INT.

FIG. 9 shows a flowchart of the instruction mid-interrupt processing microprogram. In step 110, the general-purpose register GR7 (GR7 is used as a stack pointer) is subtracted by 4, and the result is stored in GR7 and MAR (memory address register: a register of the system bus interface control mechanism 2 and output bus 16 in FIG. 4). can be set from the arithmetic unit 6 through the Set WK7 to MWR (memory write data register: a register of the system bus interface control mechanism 2, which can be set from the arithmetic unit 6 through the output bus 16). At the same time, memory write is started (indicated by the symbol MWT). This activation causes the contents of the MWR to be written to the main memory address indicated by MAR. That is, WK7 is pushed onto the stack. Similarly, in step 111, WK2 is pushed onto the stack, and in step 112, WK2 is pushed onto the stack.
Push I onto the stack. Steps 110 to 112 are processes for saving internal intermediate results. In step 113, "8" is pushed onto the stack as an identification code.

(The "8" pattern is generated in the constant section 15 of the microinstruction.) Step 114 bushes the PC onto the stack, and step 115 bushes the program level onto the stack. (The PC is transferred to the arithmetic unit 6 through the interface 10, and the program level is transferred to the arithmetic unit 6 through the interface 12.) In step 117, execution of the instruction is completed and execution of the next instruction is started. At this point, save information as shown in FIG. 10 has been created in the stack. Next, in step 116, the data read from address 32 of the main memory is set in the PC.

The first 10 addresses of the main memory are an interrupt vector table as shown in Figure 11, and the 32nd address is the starting address (240
0), , are stored. Next, in step 117, the instruction execution ends.

After the processing is completed, the instruction decoding unit branches to the next microprogram according to the first address 13 of the generated microprogram, but at this time, the priority interrupt presence signal 14
Since this is on, the instruction decoding unit generates the starting address of the microprogram corresponding to the priority interrupt, as explained in FIG.

FIG. 12 shows a flowchart of a microprogram corresponding to priority interrupts. As an example, a microprogram corresponding to level 3 interrupts is shown.

In step 120, rOJ is pushed onto the stack as an identification code. In step 121, the PC is pushed onto the stack. Step 122 pushes the program level onto the stack. At this point the stack is number 13
It looks like the picture.

Next, in step 123, the data read from address 12 of the main memory (see FIG. 11) is set in the PC. In step 124, the program level is set to "3", which is a number equal to the interrupt level.

In step 125, instruction execution is ended and execution of the next instruction is started.

After the above processing is completed, the microprogram start address 13 generated by the instruction decoding unit has a program level of "
3'', the priority interrupt presence signal 14 is off, so this address is generated by decoding the macro instruction read out from the PC. The value set on the PC is
As shown in FIG. 11, it is (2180) 1 g.

FIG. 14 shows (2180)1. This is a macro program that supports level 3 interrupts starting from address. In the final step 132 of this program, an interrupt return instruction is executed.

FIG. 15 shows the microprogram of the interrupt return instruction.
In step 140, the value popped from the stack (program level before interrupt=O) is set to the program level. In step 141, the value popped from the stack (
Set the program counter before interrupt (2400)□6) to the program counter. In step 142, the value popped from the stack (identification code = O) is set to WK3.
Set to . In step 143, the value of WK3 is checked. In step 144, it is determined whether the check result is "0". In this case, since WK3 is "0", the condition is met, and the process advances to step 145 to end the instruction execution. As a result, (2400)1. Branches to a macro program that supports interrupts during the instruction at the address.

FIG. 16 shows a macro program that supports interrupts during instructions starting from address (2400). In this program, only the interrupt return instruction is executed.

FIG. 17 shows the microprogram of the interrupt return instruction.
However, the first half is shown in FIG. 15, and this figure is the part related to return from an interrupt during an instruction. First, in step 140 of FIG. 15, the value popped from the stack (program level before interrupt=0) is set to the program level. In step 141, the value popped from the stack (the starting address of the next macro instruction) is set in the PC. In step 142, the value popped from the stack (identification code =
Set 8) to WK3. In step 143, WK3
Check the value of . In step 144, it is determined whether the check result is O.

In this case, since WK3 is "8", the condition is not satisfied, and the process proceeds to step 160 in FIG. 17. In step 160, the value of WK3-8 is checked. In step 161, it is determined whether the check result is "0". In this case WK
Since 3 is "8", the condition is met, and step 162
In step 162, the value popped from the stack (the value of WKI at the time of occurrence of the interrupt) is set in WKI. In step 163, the value popped from the stack (the value of WK2 at the time of occurrence of the interrupt) is set in WK2. Step 16
4, the value popped from the stack (MP to restart
C=1003) in WK7. Step 16
5 sets WK7 to MPC. This set is the 4th
This is done by the selector 41 selecting the output bus 16 in the figure. As a result, the intermediate results WKI and WK2 can be recovered and the interrupted microinstruction can be restarted.

FIG. 18(a) and FIG. 18(b) show a modification of the present invention. Interrupt return instructions are not distinguished by the identification code in the save information to determine whether or not they are interrupts in the middle of an instruction, but by the instruction code. That is, the present invention is characterized in that an instruction mid-instruction interrupt return instruction is provided in addition to the general interrupt return instruction.

〔Effect of the invention〕

As described above, according to the present invention, general-purpose registers are not destroyed by intermediate results, and unnecessary saving and restoring of registers is unnecessary. Specifically, in the case of a 16-byte transfer, 16 times in total (4 accesses for register saving, 8 memory accesses for the original purpose, and 4 accesses for register recovery) would be performed for the original purpose. Only 8 memory accesses are required for this process, which can speed up the process.

[Brief explanation of drawings]

Fig. 1 is a schematic control system of the present invention, Fig. 2 is a general interrupt control system, Fig. 3 is a known interrupt control system, Fig. 4 is an outline of the configuration of the basic processing mechanism, and Fig. 5 is a general interrupt control system. Figure 6 shows the configuration of the instruction decoding unit, Figure 6 shows the configuration of the arithmetic control system, Figure 7 shows the configuration of the arithmetic unit, Figure 8 shows the microprogram for macro instructions that take a long time to execute, and Figure 9 shows the interrupt processing during instructions. Microprogram, Figure 10 shows the configuration of stack save information for interrupts during instructions, Figure 11 shows the configuration of the interrupt vector table, and Figure 12 shows the structure of the interrupt vector table.
The figure shows a microprogram that supports level 3 interrupts, Figure 13 shows the configuration of stack save information for level 3 interrupts, Figure 14 shows a macro program that supports level 3 interrupts, Figure 15 shows a microprogram for interrupt return instructions, and Figure 15 shows a microprogram for level 3 interrupts. Figure 16 shows a macro program that supports interrupts in the middle of instructions, Figure 17 shows a microprogram for interrupt return instructions (related to interrupts in the middle of instructions), Figure 18 (a),
(b) is a diagram showing a schematic control method of a modified example of the present invention. 3... System bus interface control mechanism, 4...
- Instruction decoding unit, 5... Arithmetic control system, 6... Arithmetic unit.

Claims (1)

[Claims] 1. The presence or absence of an external interrupt request with a higher priority level than the current program level is detected during instruction execution, and at the time of said detection, an internal intermediate result and an identification code are detected in the interrupt after the instruction is completed. The first code is different from the code used.
saves the code in the main memory, sets the preset value for intermediate interrupts in the program counter, finishes execution of the current instruction, starts execution of the next instruction, and branches while the program level remains unchanged. An interrupt return instruction is executed in the previous program, the identification code is determined, and if it is the first code, the intermediate result saved in the main memory is recovered, and the code is restarted from the middle of instruction execution. An interrupt control method for a processing device, characterized in that processing is restarted.