JP3171615B2 - Data transfer retry control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a retry control system for transferring data to a memory / I / O via a bus in a microprogram-controlled CPU.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration example of an information processing apparatus using a conventional processor. Information processing devices such as various computers and programmable controllers
Generally, as shown in FIG.
00, an I / O device (input / output device) 300, a transmission interface 400, a system bus 500, and the like.

[0003] The processor 100 includes these memories 20.
0, I / O device 300, transmission interface 400
When exchanging information with the like, data is transferred via the system bus 500. The processor 100 employs a microprogram control method, and is composed of FORTRAN, COBOL, C
A macro program composed of macro instructions obtained by compiling or assembling a source program described in a high-level language such as a high-level language or a controller language for a program controller is interpreted by a micro program.

The processor 100 includes a microprogram memory 101 (hereinafter abbreviated as μ-MEM 101) storing a microprogram composed of microinstructions, and a microprogram counter (hereinafter abbreviated as μ-PC), which is not particularly shown. ), The above μ-MEM101
Micro-sequencer 102 which supplies an address (the value of the μ-PC) every predetermined period (micro cycle).
(Hereinafter abbreviated as μ-SQC102), the above μ-ME
A pipeline register 103 (hereinafter abbreviated as PLR103) that holds the microinstruction read from M101 and outputs various control signals from the microinstruction, and performs various operations instructed by the microinstruction read from the PLR103. As a result, signs (S) indicating positive / negative, zero detection (Z), and carry detection (C
Y), CPU (Central Processing Unit) 104 that outputs various flags such as overflow detection (OVF), etc. When data on system bus 500 is input, parity check of bus data is performed, and when data is output to system bus 500 Is a bus parity checker that performs parity generation.
A generator 121, a bus access time monitoring circuit 122 for monitoring bus access time, and a slave device abnormality signal determination circuit 123 for constantly monitoring an abnormal state of a slave device of a data transfer destination via the system bus 500.
A bus transfer error detection circuit 120 comprising a macro program memory 1 storing the macro program
05, a macro program counter 106 (hereinafter referred to as MP) for supplying an address to the macro program memory 105.
C106), the macro program memory 1
Physical address generation circuit 10 for generating a physical address from an address operand of a macro instruction read out from memory 05
7, a data transfer address register 108 for holding the address of the transfer data output from the physical address generation circuit 107, and a bus error signal applied from the bus transfer error detection circuit 120 or S, Z, CY, Alternatively, it comprises a test condition selection circuit 109 for selectively outputting the value of each flag of OVF to the μ-SQC 102.

Incidentally, the bus transfer error detecting circuit 120
Are caused by the occurrence of a parity error due to the detection of the bus parity checker / generator 121, the abnormality of the bus access time due to the detection of the bus access time monitoring circuit 122, or the abnormality of the slave device at the time of data transfer due to the detection of the slave device abnormality signal judgment circuit 123. A bus error signal is output due to any of the above factors.

[0006] The CPU 104 is connected to the system bus 500 via a local data bus 130. In the above configuration, the macro instruction in the macro program memory 105 addressed by the MPC 106 is set in the MAP processing (mapping processing: the μ-PC is set at the start address of the corresponding micro program processing in accordance with the object code of the macro instruction). Then, the interpreting process is started by the interpreter, which is a microprogram composed of a plurality of corresponding microinstructions stored in the μ-MEM 101 via the μ-SQC 102 by the process of activating the interpreter process.

There are several types of macro instruction transfer instructions depending on the transfer mode, for example, 32-bit read / write transfer, 16-bit read / write transfer, 8-bit read / write transfer. , And signed transfer of 16 / 8-bit length (sign-extended upon transfer and converted to 32-bit length). In the μ-MEM 101, interpreters respectively corresponding to these macro instructions are stored.

At the time of execution of each transfer instruction, the μ-M
Simultaneously with the start of the interpreter in the EM 101, the address operand in the macro instruction read from the macro program memory 105 is stored in the physical address generation circuit 1.
07 to a transfer address which is a physical address,
The transfer address is stored in the data transfer address register 108
Latched. When the CPU 104 starts data transfer via the system bus 500 by starting the interpreter, the data transfer address register 108
, The transfer address is output to the system bus 500, and information is exchanged with the corresponding memory 200 or I / O device 300 or the like.

In the data transfer via the system bus 500, the bus transfer error detecting circuit 120
The parity check of the bus data on the system bus 500, the time monitoring of the bus access, and the abnormal state of the data transfer destination slave device are always checked, and in the event of an abnormality, a retry process is performed in order to cut off a temporary defective operation. If the retry processing has failed, the RAS processing routine in the system management program (RAS refers to the reliability of a measure of reliability).
), Availability, Serviceability
This is a generic term for y), and refers to functions such as control of failures and system states, their data management and operation, troubleshooting methods, and recovery methods. The RAS process is a process that performs the above function. ) And decide on continuous operation or system stoppage due to degeneration from the viewpoint of the system.

When a bus error occurs, a bus error signal from the bus transfer error
The data is output to the PU 104, the μ-SEQ 102, the MPC 106, and the data transfer address register 108. By the output of the bus error signal, writing of read data to a cache memory (not shown) in the CPU 104 is prohibited, and the data transfer address register 108 is prohibited from writing the transfer address of the next macro instruction. At this time, the increment operation of the address is prohibited.) Further, the counting operation of the MPC 106 is prohibited. Μ-SQC 102 is μ-P
Μ-PC in which C count operation is prohibited and not updated
Is stored in a μ-stack (not shown),
A branch is made to an address of an interrupt vector for a bus error interrupt processing routine for performing retry control processing without selecting a MAP address of a macro instruction output from the macro program memory 105. When the μ-SQC 102 returns from the bus error interrupt processing routine with a return instruction, the μ-SQC 102 selects the micro-memory address of the micro-instruction for performing the bus transfer operation saved in the μ-stack. As a result, the steps of the same microprogram are executed again, and a retry of the bus transfer is performed.

FIG. 7 shows a flowchart of a bus transfer process for data read via the system bus 500, which is performed by a conventional microprogram (interpreter).
FIG. 9A shows a bus transfer of 32-bit 1-word data.
FIG. 13B is a flowchart showing the processing of a 16-bit data read interpreter for transferring a 16-bit one-word data by bus. Both of the above two interpreters perform MAP simultaneously with each data transfer. In order to perform the processing, the interpreter of the data transfer macro instruction is completed in one clock.

Next, when a bus error occurs in the bus transfer operation of the 32-bit data read interpreter shown in FIG. 7A, an operation flowchart of the bus error interrupt processing routine started as described above. Is shown in FIG.

In this interrupt processing routine, retry failure is determined by counting the number of retries by a retry counter or the like, and determining whether the counted number of retries exceeds a predetermined number (SA1). ), Return instruction (RE
After the execution of T), a retry is performed by executing the same microprogram step of 32-bit data read shown in FIG. 7A, and if no bus error occurs due to the retry, the retry succeeds and is executed simultaneously. MAP
Through the processing, the processing of decoding and executing the next macro instruction is continued. On the other hand, when a bus error occurs again due to the retry, the process returns to the above-described process by the interrupt process. If it is determined in step SA1 that the number of retries has exceeded the predetermined number due to overflow of the retry counter and the retry has failed, the RAS process of the system management program is started (SA2). Operating system (μ-O
S) Store the managed dummy address in the data transfer address register 108 (SA3) and return (RET)
By doing so, in the same microstep of the 32-bit data read, dummy transfer is performed without causing a bus error, the processing is forcibly terminated, and the processing shifts to the processing of the system management program by a system task level interrupt.

In the 16-bit data read interpreter, the same processing is performed by the processing shown in FIG. 7B and the interrupt processing routine for retry control at the time of a bus error shown in FIG. Also, in reading / writing one word data of other various bits and various transfer modes, an interpreter for executing bus transfer of the data and execution of an interrupt processing routine for retry control at the time of a bus error shown in FIG. Performs the same processing.

Next, FIG. 9 shows a conventional data transfer (block data transfer) of a plurality of words (one word is composed of 16 bits).
Is an operation flowchart of an interpreter that performs the following. This flowchart shows the processing of the interpreter that decodes and executes a macro instruction for block-transferring N words of data from the memory A starting at address A to the memory B starting at address B, as schematically shown in FIG.

In this case, the data transfer register 108
Address register 108 that addresses the storage address of one-word data (16-bit data) of the transfer source
A and an address register 108B for addressing the transfer destination address of the one-word data are provided. Also,
A transfer counter for setting the number of transfer words is also newly provided.

Next, the flowchart of FIG. 9 will be described. In this case, it is assumed that the address A of the memory A is initialized to the address register 108A, and the address B of the memory B is initialized to the address register 108B.

Next, the operation will be described. First, the transfer word number N is stored in the transfer counter (SB1). The 16-bit data stored in the address of the memory A addressed by the address register 108A is read and transferred to the system bus 500, and at the same time, "1" is added to the address register 108A (SB
2). The memory B in which the 16-bit data read above is addressed by the address register 108B
, And at the same time as the transfer, the address register 108B is incremented by "1" (SB3). The transfer counter is decremented by "1" (SB4). It is determined whether or not the value of the transfer counter is “0” (S
B5) If not “0”, the above processing →→→ is repeated. On the other hand, if the value of the transfer counter is “0”, M
By the AP processing, the processing is continued to decode and execute the next macro instruction.

In the data transfer processing of a plurality of words, if a bus error occurs during the data transfer in the above-mentioned processing or the above processing, the above-described interrupt processing for retry control when a bus error occurs shown in FIG. A retry process similar to the process of the interpreter shown in FIG. 7A or 7B is performed.

Therefore, for example, in the case of a bus access time monitoring abnormality (abnormality that results in a non-response state in data transfer) in 2,000-word block data transfer, if the bus access abnormality monitoring time is 200 μs, For a maximum of 400 ms (200 μs × 2000), one macro instruction occupies the processing time of the processor 100.

As described above, when a bus error of abnormal bus access time monitoring occurs in the execution of decoding of a macro instruction for block-transferring a plurality of words of data by an interpreter, the bus access is performed every time one word data is read or written. Since the processing of the CPU 104 is interrupted during the abnormality monitoring time, as the number of words in the block transfer increases, the time during which the block transfer macro instruction occupies the processor 100 increases.

[0022]

As described above, when a plurality of words of block data are transferred in a microprogram interpreter that decodes and executes one macro instruction, a bus error occurs. In the case of a monitoring abnormality (no response in data transfer), one macro instruction occupies the processing time of the processor 100 for a long time.

Generally, a program incorporated in a system is described by a plurality of macro instructions. In an operating system, the execution of the program is managed in units of tasks. The tasks are classified according to the start timing, such as a cyclic task started in the order of the task number, a fixed-cycle interrupt task started at a fixed cycle, an external interrupt task started by an external event interrupt, and the like.

Among the tasks as described above, the fixed-period interrupt task is started at a fixed period, and if the period is short, a bus access time monitoring abnormal bus error occurs and one macro instruction is executed. If the processing time is occupied for a long time, the task including the macro instruction is completed for a long time, so that the congestion of the fixed-cycle interrupt task occurs, which may cause a fatal abnormality in the system.

According to the present invention, a bus error occurs during execution of a macro instruction for performing block data transfer of a plurality of words by a microprogram interpreter due to a bus access time monitoring abnormality, and the data transfer retry is performed. In the event of a failure, the interpreter is forcibly terminated to prevent the processing time from being occupied for a long time due to the bus error. An object of the present invention is to prevent adverse effects on the system such as traffic jams and suspensions of tasks.

[0026]

FIG. 1 is a diagram illustrating the principle of the present invention. The present invention relates to a macro program memory 1 for storing a macro program, a macro program counter 2 for specifying an address of the macro program memory 1,
Retry of data transfer in a processor having a microprogram memory 3 for storing a microprogram, a microsequencer 4 for specifying an address of the microprogram memory 3, and a CPU 5 for performing an operation based on a microinstruction read from the microprogram memory 3 The control method is assumed.

When a bus transfer error occurs due to the execution of a microinstruction of a microprogram for decoding and executing a predetermined macroinstruction, the CPU 5 reads the read data, outputs the write data, and operates the micro sequencer 4. Micro program counter 4a
Aborting the update of the micro-instruction by an interrupt process performed in response to the bus transfer error, and re-executing a micro-program for decoding and executing the predetermined macro-instruction, If a retry of data transfer fails during execution of a microinstruction of a microprogram that decodes and executes a macroinstruction that performs data transfer (performs a block transfer of data) a plurality of times, the retry failure information is used to decode and execute the macroinstruction. Notify the program to forcibly terminate the subsequent decryption execution of the microprogram.

The notification of the retry information to the microprogram in the data transfer is performed, for example, by turning on the flag 6 in the interrupt processing for the bus transfer error. In this case, as described in claim 3, the microprogram includes the flag 6
Is turned on, the flag 6 is turned off, and then the process is forcibly terminated. The flag 6 is provided in the CPU 5, for example.

[0029]

When a micro-instruction of a micro-program for decoding and executing a macro instruction for performing a data transfer (performing a block transfer of data) a plurality of times by the micro-program control type CPU 5 is executed, a bus error occurs when a bus transfer error occurs. A retry process is performed in which the microinstruction in which the bus transfer error has occurred due to the interruption is repeated a predetermined number of times until the bus transfer error is resolved. If the bus transfer error is not resolved even in the retry processing, that is, if the retry processing fails, the fact that the retry failed is returned to the block transfer of the return source via a flag or the like at the time of interrupt return. The macro instruction to be executed is notified to a microprogram (interpreter) for decoding and executing.

The microprogram (interpreter) is
According to the notification, the decoding of the macro instruction for performing the block transfer is forcibly terminated. Therefore, if a bus transfer error occurs in a macro instruction that performs block transfer of data and the retry does not resolve the bus transfer error,
Since the execution of the macro instruction is immediately forcibly terminated, even if a bus error occurs due to a bus access time monitoring abnormality, the processing time of the CPU 5 may be occupied for a long time by the macro instruction for performing the data block transfer. Is prevented.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a system configuration diagram of a processor according to an embodiment of the present invention. In the figure, the same blocks as those in the processor 100 shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. The feature of this embodiment is a portion surrounded by a broken line in FIG. 6, which is enlarged in FIG.

As shown in FIG. 3, the CPU 104 'has a built-in retry failure flag register for storing a retry failure flag indicating whether a retry has failed in a bus transfer. The contents of the retry failure flag register are output to the test condition selection circuit 109 'and input to the μ-SQC 102 as a test condition signal via the test condition selection circuit 109'.

Next, the microprocessor 10 having the above configuration will be described.
FIG. 4 shows an operation flowchart of the interpreter for transferring the 16-bit data at 0 'in N word blocks, and FIG. 5 shows an operation flowchart of the retry failure determination processing performed by interruption when a bus error occurs in the block transfer. .

The basic operation of the interpreter shown in FIG. 4 is the same as that of the interpreter shown in FIG.
In the 16-bit write transfer described above, processing for judging the retry failure flag via the test condition selection circuit 109 'is added. Also, a process of turning off the retry failure flag in process SC6 is added.

In the flow chart of the N-word block transfer shown in FIG. 4, when a bus error occurs in the 16-bit read transfer operation of the process SC2, the interrupt processing shown in FIG. 5 is started, and the conventional example (see FIG. 8) is executed. The retry processing described below is performed in the same manner as in ()). A retry failure is determined by a retry counter or the like (SD1), and if it is not a failure, the same processing as in the conventional example is performed. When it is determined that the retry has failed due to overflow of the retry counter (SD1), the retry failure flag register 501 is set to ON (SD2). After activating the RAS process of the system management program (SD3), the dummy address under the μ-OS management is stored in the data transfer address register 108 (SD4), and the process returns (RET).

Then, the 16-bit read transfer operation of N-word block transfer shown in FIG. 4 is performed again (SC2). In this case, the transfer operation is forcibly terminated by performing a dummy transfer in which no bus error occurs. At the same step as the transfer operation, the μ-SQC 102 determines the flag of the retry failure flag register 501 via the test condition selection circuit 109 ', and since the retry failure flag register 501 is on, the system task is executed by the MAP processing. Level interrupt, and shifts to decoding and execution of macro instruction of system management program processing (SC
6). Also, in the MPA process, the retry failure flag level 501 is turned off and initialized at the same step (SC6), to prepare for the retry process of the next block transfer as shown in FIG.

Processing S for N-word block transfer shown in FIG.
Even when a bus error occurs in the 16-bit write transfer operation in C3, the same processing as the above-described 16-bit read transfer operation in processing SC2 is performed.

In the microprogram interpreter for 32-bit and 16-bit one-word data transfer as shown in FIGS. 7A and 7B, the MAP processing and the retry failure flag are performed in the same steps as the transfer operation. By performing the process of turning off and initializing the register 501, the number of microprogram processing steps in one-word data transfer that ends normally can be increased without increasing the number of processing steps.
Retry failure flag register 501 when a retry fails due to a bus error in word data transfer
Can be initialized.

[0039]

According to the present invention, in a microprogram interpreter for decoding and executing a macro instruction for performing data transfer a plurality of times (performing a block transfer of a plurality of words),
If a bus error occurs and retry processing to cope with the bus error also fails, the interrupt processing notifies the interpreter of the microprogram that decodes and executes the macro instruction of the retry failure and notifies the interpreter of the failure. Since the operation is forcibly terminated, even if a bus error occurs due to a bus access time monitoring abnormality, it is possible to prevent the processing time of the CPU from being occupied for a long time by the macro instruction for performing the block transfer of a plurality of words. Therefore, even in a program composed of macro instructions,
The task of performing the block transfer of the plurality of words is prevented from occupying the execution right of the task for a long time due to the cause of the bus access time monitoring abnormality. As a result, a bus error due to the bus access time monitoring abnormality is prevented. When this occurs, it is possible to prevent the system from being adversely affected by congestion and stoppage of the periodic interrupt task.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of a processor according to an embodiment;

FIG. 3 is a diagram showing a main part of the invention of the embodiment.

FIG. 4 is a flowchart illustrating an operation of an interpreter that transfers 16-bit data in N word blocks.

FIG. 5 is a flowchart illustrating an operation of a retry failure determination process due to a bus error interrupt.

FIG. 6 is a diagram illustrating a configuration example of a conventional processor.

FIG. 7 is a flowchart illustrating a transfer process of a conventional 32-bit data one-word read interpreter and a transfer process of a 16-bit data one-word read interpreter.

FIG. 8 is a flowchart illustrating a conventional interrupt process performed when a bus transfer error occurs.

FIG. 9 is a flowchart illustrating the operation of a conventional interpreter for transferring 16-bit data in N word blocks.

FIG. 10 shows a case where 16-bit data is transferred from memory A to memory B.
It is a schematic diagram which shows the process of transferring a word block.

[Explanation of symbols]

 1 Macro program memory 2 Macro program counter 3 Micro program memory 4 Micro sequencer 4a Micro program counter 5 CPU 6 Flag

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/36 G06F 9/22 G06F 11/00 G06F 11/14 G06F 11/30

Claims (4)

(57) [Claims] A macro program memory for storing a macro program; a macro program counter for designating an address of the macro program memory; a micro program memory for storing a micro program; A micro-sequencer (4) for specifying an address of the micro-program memory (3), and a CPU operating based on micro-instructions read from the micro-program memory (3)
In the retry control method for data transfer in the processor having (5), when a bus transfer error occurs due to execution of a microinstruction of a microprogram for decoding and executing a predetermined macroinstruction, the CPU (5) reads the read data. ,
The output operation of the write data and the update of the microprogram counter (4a) of the microsequencer (4) are aborted, and the retry of the microinstruction by the interrupt processing performed in response to the occurrence of the bus transfer error has failed. In the case, when the retry of the data transfer fails in the execution of the microinstruction of the microprogram for decoding and executing the macro instruction for decoding and executing the macro instruction for performing the data transfer a plurality of times, A retry control method for data transfer, wherein the retry failure information is notified to a microprogram for decoding and executing the macro instruction, and the subsequent decoding and execution of the microprogram is forcibly terminated. 2. A method according to claim 1, wherein the notification of the retry failure information in the data transfer to the microprogram is performed by turning on a flag (6) in an interrupt process for the bus transfer error. Retry control method for data transfer. 3. The data transfer retry according to claim 2, wherein the microprogram turns off the flag (6) and forcibly terminates when the flag (6) is on. control method. 4. The CPU (5), wherein the flag (6) is
4. The data transfer retry control method according to claim 2, wherein the data transfer retry control method is provided in a memory.