JPH0581175A - Retry control system of data transfer - Google Patents

Abstract

PURPOSE:To prevent a macro instruction performing a block data transfer of plural words from occupying a long time in a processing time when a bus error generates owing to the abnormality of a bus access time monitoring, regarding the data transfer by a CPU of a micro-program control system. CONSTITUTION:In an interpreter performing a N-word block transfer for 16-bit data, a retry processing is performed by an interruption processing when a bus error generates in the data transfer operation of 16-bit read (SC2) or 16-bit write (SC3). When the retry processing is failed, it is recovered by turning a retry failure flag register on. The interpreter moves to the decoding execution of the macro-instruction of a system control program processing by the immediate interruption of a system task level in a MAP processing when a flag register is turned on and at the same time turns the flag register off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a retry control system for data transfer to a memory, I / O or the like via a bus in a microprogram controlled CPU.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a configuration example of an information processing apparatus using a conventional processor. Information processing devices such as various computers and programmable controllers
Generally, as shown in FIG.
00, an I / O device (input / output device) 300, a transmission interface 400, a system bus 500, and the like.

The processor 100 uses these memories 20.
0, I / O device 300, transmission interface 400
When exchanging information with the like, data is transferred via the system bus 500. This processor 100 adopts a micro program control system, and FORTRAN, COBOL, C
A macro program consisting of macro instructions obtained by compiling or assembling a source program written in a high-level language such as the above or a controller language for a program controller is decoded by a micro program.

The processor 100 includes a micro program memory 101 (hereinafter referred to as μ-MEM 101) that stores a micro program composed of micro instructions, and a micro program counter (hereinafter referred to as μ-PC) which is not particularly shown. ), The above μ-MEM101
To the micro sequencer 102 that supplies an address (the value of the μ-PC) every fixed period (micro cycle)
(Hereinafter, abbreviated as μ-SQC102), the above μ-ME
A pipeline register 103 (hereinafter, abbreviated as PLR103) that holds the microinstruction read from M101 and outputs various control signals from the microinstruction, and executes various operations instructed by the microinstruction read from the PLR103. The positive and negative signs (S), zero detection (Z), carry detection (C)
Y), CPU (Central Processing Unit) 104 that outputs various flags such as overflow detection (OVF), and when data on the system bus 500 is input, a parity check is performed on the bus data and when data is output to the system bus 500. Is a bus parity checker that performs parity generation /
A generator 121, a bus access time monitoring circuit 122 that monitors the time of bus access, and a slave device error signal determination circuit 123 that constantly monitors an abnormal state of a slave device that is a data transfer destination via the system bus 500.
A bus transfer error detection circuit 120, and a macro program memory 1 in which the macro program is stored.
05, the macro program counter 106 that supplies an address to the macro program memory 105 (hereinafter MP
(Abbreviated as C106), the macro program memory 1
Physical address generation circuit 10 for generating a physical address from the address operand of the macro instruction read from
7, a data transfer address register 108 for holding an address of transfer data output from the physical address generation circuit 107, and a bus error signal added from the bus transfer error detection circuit 120 or the above S, Z, CY, added from the CPU 104. Alternatively, it comprises a test condition selection circuit 109 for selectively outputting the value of each flag of OVF to the μ-SQC 102.

By the way, the bus transfer error detection circuit 120
Is the occurrence of a parity error due to the detection of the bus parity checker / generator 121, the abnormality of the bus access time due to the detection of the bus access time monitoring circuit 122, or the abnormality of the slave device during the data transfer due to the detection of the slave device abnormality signal determination circuit 123. A bus error signal is output due to any of the above factors.

The CPU 104 is connected to the system bus 500 via a local data bus 130. In the above configuration, the macro instruction in the macro program memory 105 addressed by the MPC 106 is set to the MAP processing (mapping processing: corresponding to the object code of the macro instruction, the μ-PC is set at the head address of the corresponding micro program processing). Then, it is decoded and executed by an interpreter, which is a microprogram composed of a plurality of corresponding microinstructions stored in the μ-MEM 101 via the μ-SQC 102 by the process of activating the interpreter process).

There are several types of macro instruction transfer instructions depending on the transfer mode. For example, 32-bit length read / write transfer, 16-bit length read / write transfer, and 8-bit length read / write transfer. , And 16 / 8-bit length signed transfer (sign extension is performed during transfer to convert to 32-bit length). An interpreter corresponding to each macro instruction is stored in the μ-MEM 101.

At the time of execution of each transfer instruction, the μ-M
At the same time when the interpreter in the EM 101 is activated, the address operand in the macro instruction read from the macro program memory 105 is transferred to the physical address generation circuit 1
It is converted to a transfer address which is a physical address by 07,
The transfer address is transferred to the data transfer address register 108.
Latched on. When the CPU 104 starts data transfer through the system bus 500 by starting the interpreter, the data transfer address register 108
The transfer address is output from the system bus 500 to the system bus 500, and information is exchanged with the corresponding memory 200 or I / O device 300.

In the data transfer via the system bus 500, the bus transfer error detection circuit 120
The parity check of the bus data on the system bus 500, the time monitoring of the bus access, and the abnormal state of the slave device of the data transfer destination are constantly checked, and when abnormal, a retry process is performed in order to discard a transient defective operation. Then, when the retry process fails, a message to that effect is issued by the RAS process routine (RAS is a reliability measure of reliability).
), Availability (Availability), Maintainability (Serviceabilit)
y) is a generic term that refers to functions such as grasping the status of failures and system status and their data management operations, methods of dealing with failures, and methods of recovering from failures. The RAS process is a process that fulfills the above function. ) And make a decision from the system standpoint such as continuous operation due to degeneration or system stoppage.

When a bus error occurs, the bus error signal from the bus transfer error detection circuit 120 is C
It is output to the PU 104, the μ-SEQ 102, the MPC 106, and the data transfer address register 108. By the output of this bus error signal, writing of read data to a cache memory (not shown) in the CPU 104 is prohibited, and writing of the transfer address of the next macro instruction is prohibited in the data transfer address register 108. In addition, the address increment operation is prohibited) Furthermore, the count operation of the MPC 106 is prohibited. Also, μ-SQC102 is μ-P
Μ-PC in the state of prohibiting C count operation and not updating
The value of is stored in the μ-stack (not shown),
It branches to the address of the interrupt vector for the bus error interrupt processing routine that performs the retry control processing without selecting the MAP address of the macro instruction output from the macro program memory 105. Then, when returning from the bus error interrupt processing routine by a return instruction, the μ-SQC 102 selects the micro memory address of the micro instruction that performs the bus transfer operation saved in the μ-stack. As a result, the same microprogram step is executed again, and the bus transfer is retried.

FIG. 7 shows a flow chart of a bus transfer process of data read via the system bus 500, which is performed by a conventional microprogram (interpreter).
In the same figure (A), 32-bit 1-word data is transferred by bus.
A 32-bit data read interpreter, (B) in the figure is a flow chart showing the processing of a 16-bit data read interpreter that transfers 16-bit 1-word data by bus. Both of the above two interpreters are MAP at the same time as each data transfer. In order to perform the processing, the interpreter of the macro instruction for data transfer is completed in one clock.

Next, when a bus error occurs in the bus transfer operation of the 32-bit data read interpreter shown in FIG. 7 (A), an operation flowchart of the bus error interrupt processing routine that is started as described above. Is shown in FIG.

In this interrupt processing routine, a retry counter or the like is used to count the number of retries, and it is judged whether or not the counted number of retries exceeds a predetermined number of times (SA1). ), A return instruction (RE
After the execution of T), a retry is performed by executing the same microprogram step of 32-bit data read shown in FIG. 7A, and if a bus error does not occur due to the retry, the retry is successful and simultaneous execution is performed. MAP
Depending on the processing, the processing for decoding and executing the next macro instruction is continued. On the other hand, when the bus error occurs again due to the retry, the above-mentioned processing is performed again by the interrupt processing. When it is determined in the processing SA1 that the number of retries exceeds a predetermined number due to overflow of the retry counter or the like and the retries fail, the RAS processing of the system management program is activated (SA2), and then the micro program Operating system (μ-O
S) Store a dummy address under management in the data transfer address register 108 (SA3) and return (RET)
By doing so, a dummy transfer that does not cause a bus error is performed in the same micro step of the 32-bit data read to forcibly terminate the processing, and the processing of the system management program is shifted to by the system task level interrupt.

Even in the 16-bit data read interpreter, similar processing is performed by the processing shown in FIG. 7B and the interrupt processing routine for retry control at the time of bus error shown in FIG. Further, also in reading / writing 1-word data of other various bits and various transfer modes, an interpreter for executing bus transfer of those data and execution of an interrupt processing routine for retry control at the time of bus error shown in FIG. The same processing is performed by.

Next, FIG. 9 shows the conventional data transfer of a plurality of words (1 word has 16 bits) (block data transfer).
The flowchart of the operation of the interpreter which performs is shown. This flow chart shows the processing of the interpreter for decoding and executing the macro instruction for block-transferring the data in the memory A of N words starting from the address A to the memory B starting from the address B as schematically shown in FIG.

In this case, the data transfer register 108
Address register 108 for addressing the storage address of 1-word data (16-bit data) of the transfer source
An address register 108B for addressing the address of A and the transfer destination of the 1-word data is provided. Also,
A transfer counter for setting the number of transfer words is newly provided.

Next, the flowchart of FIG. 9 will be described. In this case, the address A of the memory A is initially set in the address register 108A, and the address B of the memory B is initially set in the address register 108B.

Next, the operation will be described. First, the transfer word number N is stored in the transfer counter (SB1). The 16-bit data stored in the address of the memory A addressed by the address register 108A is read and transferred onto the system bus 500, and at the same time, the address register 108A is incremented by "1" (SB
2). The memory B in which the 16-bit data read above is addressed by the address register 108B
The address register 108B is incremented by "1" at the same time as the transfer (SB3). The transfer counter is decremented by "1" (SB4). It is determined whether or not the value of the transfer counter is "0" (S
B5), if not "0", the above process →→→ is repeated. On the other hand, if the value of the transfer counter is “0”, M
By the AP processing, the processing is continued until the next macro instruction is decoded and executed.

Also in the above-mentioned data transfer process of a plurality of words, if a bus error occurs during the data transfer in the above process or the above process, the above-described interrupt process for retry control at the time of bus error occurrence shown in FIG. A retry process similar to that of the interpreter process shown in FIG. 7A or 7B is performed.

Therefore, for example, in the case of a block data transfer of 2000 words, if a bus access time monitoring abnormality (abnormality in which no response occurs in data transfer) occurs, if the bus access abnormality monitoring time is 200 μs, For a maximum of 400 ms (200 μs × 2000), one macro instruction occupies the processing time of the processor 100.

As described above, in the decoding execution by the interpreter of the macro instruction for block-transferring the data of a plurality of words, when a bus error of bus access time monitoring abnormality occurs, the bus access is performed every time one word data is read or written. Since the processing of the CPU 104 is interrupted during the abnormality monitoring time, the larger the number of words for block transfer, the longer the time the block transfer macro instruction occupies the processor 100.

[0022]

As described above, when a block data transfer of a plurality of words is performed in the interpreter of the microprogram which decodes and executes one macro instruction, a bus error occurs, and the cause is the bus access time. When a monitoring abnormality (no response in data transfer) occurs, one macro instruction occupies the processing time of the processor 100 for a long time.

Generally, a program installed in the system is described by a plurality of macro instructions, and the execution of the program is managed in units of tasks in the operating system. Then, the tasks are classified into cyclic tasks that are activated in order of task number, fixed-cycle interrupt tasks that are activated at fixed intervals, and external interrupt tasks that are activated by external event interrupts, according to the activation timing.

Of the above tasks, the fixed-cycle interrupt task is activated at a fixed cycle, so if the cycle is short, a bus error of bus access time monitoring error occurs and one macro instruction is executed. If the processing time is occupied for a long time, the task including the macro instruction will end for a long time, which may cause an interrupt congestion of the fixed-cycle interrupt task, which may cause a fatal abnormality in the system.

According to the present invention, while a macro instruction for transferring block data of a plurality of words is being executed by the interpreter of the microprogram, a bus error occurs due to a cause of abnormal bus access time monitoring, and the data transfer is retried. If it fails, the interpreter is forcibly terminated to prevent the bus error from occupying the processing time for a long time, and when a bus error of bus access time monitoring error occurs, a fixed-cycle interrupt is generated. The purpose is to prevent the adverse effects on the system such as traffic congestion and stoppage of tasks.

[0026]

FIG. 1 illustrates the principle of the present invention. The present invention relates to a macro program memory 1 for storing a macro program, a macro program counter 2 for designating an address of the macro program memory 1,
Retry of data transfer in a processor having a micro program memory 3 in which a micro program is stored, a micro sequencer 4 for designating an address of the micro program memory 3, and a CPU 5 which operates based on a micro instruction read from the micro program memory 3. The control method is assumed.

When a bus transfer error occurs due to the execution of the micro instruction of the micro program for decoding and executing a predetermined macro instruction, the read data fetch operation of the CPU 5, the write data output operation of the CPU 5, and the micro sequencer 4 Micro program counter 4a
Of the update, etc., and has a function of re-executing the micro program for decoding and executing the predetermined macro instruction when the retry of the micro instruction by the interrupt processing performed corresponding to the bus transfer error fails, When the retry of data transfer fails in the execution of the microinstruction of the microprogram that decodes and executes the macroinstruction that transfers the data a plurality of times (block transfers of the data), the microcode that decodes and executes the retry failure information. Notify the program to force the subsequent decryption execution of the microprogram to terminate.

The notification of the retry information in the data transfer to the microprogram is carried out by turning on the flag 6 in the interrupt processing for the bus transfer error as described in claim 2, for example. In this case, as described in claim 3, the microprogram has a flag 6
When it is determined that is turned on, the flag 6 is turned off, and then the process is forcibly terminated. The flag 6 is provided in the CPU 5, for example.

[0029]

When a micro-instruction of a micro program for decoding and executing a macro instruction for transferring data a plurality of times (block transfer of data) is executed by the CPU 5 of the micro program control method and a bus transfer error occurs, a bus error occurs. A retry process is repeated in which the microinstruction in which the bus transfer error has occurred due to the interrupt is repeated a predetermined number of times until the bus transfer error is resolved. Then, even if the retry process does not eliminate the bus transfer error, that is, if the retry process fails, the block transfer of the recovery source is notified via the flag etc. at the time of interrupt recovery. Notify the microprogram (interpreter) that decodes and executes the macro instruction to be executed.

The microprogram (interpreter) is
By the notification, the decoding execution of the macro instruction for the block transfer is forcibly terminated. Therefore, if a bus transfer error occurs in a macro instruction that performs a block transfer of data, and the bus transfer error cannot be resolved by retrying,
Since the execution of the macro instruction is immediately terminated forcibly, even if a bus error occurs due to the cause of the bus access time monitoring abnormality, the processing time of the CPU 5 may be occupied for a long time by the macro instruction that transfers the block of data. To be prevented.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a system configuration diagram of a processor which is an embodiment of the present invention. In the figure, the same blocks as those in the processor 100 shown in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. The feature of this embodiment is a portion surrounded by a broken line in FIG. 6 which is enlarged in FIG.

As shown in FIG. 3, the CPU 104 'has a retry failure flag register for storing a retry failure flag indicating whether or not the retry failed in the bus transfer. The content of the retry failure flag register is output to the test condition selection circuit 109 ', and is input to the μ-SQC 102 as a test condition signal via the test condition selection circuit 109'.

Next, the microprocessor 10 having the above structure
FIG. 4 shows an operation flowchart of the interpreter for transferring N-word block of 16-bit data in 0 ', and FIG. 5 shows an operation flowchart of retry failure determination processing performed by an interrupt when a bus error occurs in the block transfer. ..

The operation of the interpreter shown in FIG. 4 is basically the same as the operation of the interpreter shown in the above-mentioned figure, and the 16-bit read transfer of the process SC2 and the process SC3 are performed.
In the 16-bit write transfer, processing for determining the retry failure flag via the test condition selection circuit 109 'is added. Further, a process of turning off the retry failure flag in the process SC6 is also added.

In the flowchart of the N-word block transfer shown in FIG. 4, when a bus error occurs in the 16-bit read transfer operation of the process SC2, the interrupt process shown in FIG. 5 is started and the conventional example (see FIG. 8). The following retry processing is performed in the same manner as in (). The retry counter or the like determines the retry failure (SD1). When the retry is not failed, the same processing as the conventional example is performed. When it is determined that the retry has failed due to overflow of the retry counter or the like (SD1), the retry failure flag register 501 is set to ON (SD2). After the RAS processing of the system management program is activated (SD3), the dummy address under the μ-OS management is stored in the data transfer address register 108 (SD4) and the return (RET) is performed.

Then, the 16-bit read transfer operation of N word block transfer shown in FIG. 4 is performed again (SC2). In this case, the transfer operation is forcibly terminated by performing the dummy transfer in which no bus error occurs. In the same step as the transfer operation, the μ-SQC 102 determines the flag of the retry failure flag register 501 through the test condition selection circuit 109 ′, and the retry failure flag register 501 is turned on. Level interrupt and shift to decoding and execution of macro instruction in system management program processing (SC
6). In this MPA process, the retry failure flag level 501 is turned off and initialized in the same step (SC6) to prepare for the block transfer retry process as shown in FIG.

Processing S of N-word block transfer shown in FIG.
Even when a bus error occurs in the 16-bit write transfer operation in C3, the same processing as the 16-bit read transfer operation in the above-mentioned processing SC2 is performed.

In the interpreter of the 32-bit and 16-bit 1-word data transfer microprogram as shown in FIGS. 7A and 7B, the MAP processing and the retry failure flag are performed in the same step as the transfer operation. By performing the process of turning off the register 501 and performing the initialization, the number of processing steps of the microprogram in the one-word data transfer that normally ends is increased by 1
When a bus error occurs in word data transfer and the retry fails, the retry failure flag register 501
Can be initialized.

[0039]

According to the present invention, in the interpreter of the microprogram for decoding and executing the macroinstruction that transfers data a plurality of times (block transfer of a plurality of words),
When a bus error occurs and the retry process for coping with the bus error also fails, the retry process is notified to the interpreter of the microprogram that decodes and executes the macro instruction from the interrupt process, and the interpreter Since the operation is forcibly terminated, even if a bus error occurs due to an abnormality in the bus access time monitoring, it is possible to prevent a situation in which the processing time of the CPU is occupied for a long time by the macro instruction for block transfer of a plurality of words. Therefore, even in a program composed of macro instructions,
It is possible to prevent the task that performs the block transfer of multiple words from occupying the task execution right for a long time due to the cause of the bus access time monitoring abnormality, and as a result, the bus error due to the bus access time monitoring abnormality may occur. When it occurs, it is possible to prevent the adverse effect on the system due to the congestion or stoppage of the periodic interrupt task.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a system configuration diagram of a processor according to an embodiment.

FIG. 3 is a diagram showing an essential part of the invention of the above embodiment.

FIG. 4 is a flowchart illustrating an operation of an interpreter that transfers 16-bit data in N word blocks.

FIG. 5 is a flowchart illustrating an operation of retry failure determination processing by a bus error interrupt.

FIG. 6 is a diagram illustrating a configuration example of a conventional processor.

FIG. 7 is a flowchart illustrating a transfer process of a conventional 32-bit data 1-word read interpreter and a transfer process of a 16-bit data 1-word read interpreter.

FIG. 8 is a flowchart illustrating an interrupt process performed when a conventional bus transfer error occurs.

FIG. 9 is a flowchart illustrating the operation of a conventional interpreter that transfers N-word blocks of 16-bit data.

FIG. 10: N 16-bit data from memory A to memory B
It is a schematic diagram which shows the process which transfers a word block.

[Explanation of symbols]

 1 Macro Program Memory 2 Macro Program Counter 3 Micro Program Memory 4 Micro Sequencer 4a Micro Program Counter 5 CPU 6 Flag

Claims (4)

[Claims] 1. A macro program memory (1) for storing a macro program, a macro program counter (2) for designating an address of the macro program memory (1), a micro program memory (3) for storing a micro program, A micro sequencer (4) for designating an address of the micro program memory (3), and a CPU which operates based on a micro instruction read from the micro program memory (3)
In a retry control method for data transfer in a processor having (5), when a bus transfer error occurs due to execution of a microinstruction of a microprogram for decoding and executing a predetermined macroinstruction, the read data fetching operation of the CPU (5) ,
The write data output operation and the update of the micro program counter (4a) of the micro sequencer (4) are aborted, and the retry of the micro instruction by the interrupt processing performed in response to the occurrence of the bus transfer error has failed. In the case where the retry of the data transfer fails in the execution of the micro instruction of the micro program which decodes and executes the macro instruction which decodes and executes the predetermined macro instruction, the micro program which decodes and executes the macro instruction which executes the data transfer a plurality of times A retry control method for data transfer, characterized in that the retry failure information is notified to a microprogram that decodes and executes the macro instruction to forcibly terminate the subsequent decode execution of the microprogram. 2. The notification of retry failure information in the data transfer to the microprogram is performed by turning on a flag (6) in the interrupt processing for the bus transfer error. Data transfer retry control method. 3. The retry of data transfer according to claim 2, wherein the microprogram turns off the flag (6) and forcibly ends it when the flag (6) is turned on. control method. 4. The flag (6) is provided in the CPU (5).
4. The retry control method for data transfer according to claim 2, wherein the retry control method is provided in the inside.