JP3621477B2 - How to retry a microprogram - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
Since the system down of the information processing apparatus has a great social impact, it is more important to improve its reliability. For this reason, when a machine check condition occurs, the system is retried (re-execution of an instruction) by retrying unless the memory, registers, etc. are updated, so that a series of subsequent processes can be performed. There is a need.
In the present invention, when various interrupts such as a program interrupt and a machine check interrupt or other events occur in a state (process state) in which a general instruction is executed, a micro process for processing the event from the process state is performed. This is a microprogram retry method in a processor that transitions to the program execution state (end process state). In particular, even if a machine check condition occurs during microprogram execution, the microprogram can be retried. In addition, the present invention relates to a microprogram retry method that relieves an information processing apparatus from intermittent errors that occur during execution of a microprogram and improves reliability.
[0002]
[Prior art]
Conventionally, in an information processing apparatus (state machine) using a pipeline, general processing such as instruction execution is normally performed in a state called a process state. When a machine check condition occurs that directly damages the system and makes it impossible to continue processing during instruction execution in such a process state, in order to improve the reliability of the information processing apparatus, As long as the memory and registers are not updated, the information processing apparatus is retried a plurality of times to recover the information processing apparatus from a system down or machine check interrupt due to an intermittent error. FIG. 6 is a state machine transition state diagram: (1) a process state S1 for executing a general instruction, (2) a clear pipeline state (restore state) S2 for initializing a pipeline, 3) End process state S3 for executing processing according to various interrupts and other events in accordance with the microprogram, (4) Start state S4 for starting processing by the processor CPU, and (5) Processing of the processor CPU There are a stop state S5 for stopping, and a check stop state S6.
[0003]
FIG. 7 is an explanatory diagram of processing units (stages) of instruction execution in pipeline processing. The pipeline is composed of, for example, 10 stages, and is roughly divided into an instruction fetch pipeline until an instruction is read from the main memory or cache memory, and a main pipeline until the instruction is decoded and executed. The instruction fetch pipeline includes (1) instruction fetch address calculation stage I, (2) instruction address conversion stage IT, (3) buffer read stage IB, and (4) instruction input stage IR to the main pipeline. It is made up. The main pipeline includes (1) instruction decode stage D, (2) operand address calculation stage A in the main memory, (3) operand address conversion stage T, and (4) operand read stage B. (5) Computation execution stage E and (6) Computation result storage stage W.
[0004]
FIG. 8 is an explanatory diagram of pipeline processing. If the instruction sequence is as shown in FIG. 8A, each instruction sequentially enters the main pipeline for each stage without waiting for the end of execution of one instruction as shown in FIG. 8B. It is submitted and executed.
In such a state machine, for example, when an interrupt or other event occurs during execution of an instruction in the process state S1, the process proceeds to the clear pipeline state S2, and an instruction being executed on the pipeline in the state S2 or a subsequent instruction is transferred. Cancel and initialize. Thereafter, the process proceeds to the end process state S3, and a predetermined microprogram corresponding to the event that caused various interrupts or state transitions is started, and interrupt processing or the like is performed by the microprogram. After completion of the processing by the microprogram, the process returns to the process state S1 via the start state S4, and the subsequent instruction is executed by pipeline processing.
[0005]
[Problems to be solved by the invention]
By the way, in the conventional information processing apparatus (state machine), when a machine check condition occurs in the end process state, the interrupt point is not guaranteed. For this reason, when a machine check condition occurs in the end process state, the retry cannot be performed, the check is stopped, and the subsequent series of processes cannot be continued. In other words, conventionally, retry has been performed only in the process state, and there has been a problem that the reliability of the information processing apparatus is low.
[0006]
Accordingly, an object of the present invention is to provide a microprogram retry method capable of retrying even if a machine check condition occurs in an end process state and improving the reliability of the information processing apparatus.
Another object of the present invention is to provide a microprogram retry method capable of improving the reliability of the information processing apparatus by continuing the retry until a predetermined number of times is reached if the retry is not successful. is there.
Still another object of the present invention is to provide a microprogram retry method in which the start address of a microprogram corresponding to an interrupt or each event is stored, and the microprogram corresponding to the generated event can be read from the control storage device and retried. Is to provide.
[0007]
[Means for Solving the Problems]
FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is an occurrence event holding unit, which holds events (various interrupts, etc.) that trigger the execution of a microprogram by transitioning from a process state to an end process state, and 2 is an end process Retry is possible to monitor whether a retry is possible or not possible even if a machine check condition occurs in the state. Impossible monitoring unit 3 is a micro that outputs the start address of the microprogram according to the occurrence event. A program address generation unit 4 is a retry control unit that outputs a start address of a microprogram corresponding to the held event if a retry is possible when a machine check condition occurs during execution of the microprogram. A control storage unit (CS) 31 for storing various microprograms is read by the control storage unit. CS address register for storing the addresses, 51 is a decoder for decoding the control field of the microinstruction.
[0008]
When various interrupts such as a program interrupt and a machine check interrupt or other events occur during execution of a general instruction in the process state, the event is stored in the generated event holding unit 1. Thereafter, the process state is shifted to the end process state, and the microprogram corresponding to the generated event is read from the control storage unit 21 and executed. In such an end process state, the retry possible / impossible monitoring unit 2 monitors whether or not a retry is possible even if a machine check condition occurs at the present time. If a machine check condition occurs in the end process state (during execution of the microprogram), the retry control unit 4 checks whether or not a retry is possible, and if the retry is possible, the generated event holding unit 1 The start address of the microprogram corresponding to the event held in is stored in the CS address register 31 from the microprogram address generator 3, and the microprogram is re-executed from the beginning (retry). In this way, even if a machine check condition occurs in the end process state, a retry can be performed, and the reliability of the information processing apparatus can be improved. If the retry is not successful, the reliability of the information processing apparatus can be improved by continuing the retry until a preset number of times is reached.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
(A) Overall configuration of the present invention
FIG. 2 is an overall configuration diagram of the present invention. In the figure, 11 is a microprogram retry control circuit for executing the microprogram retry control of the present invention, and 21 is a control storage unit (CS) for storing various microprograms. Each microinstruction constituting the microprogram has a control field CF and a sequence control field SF indicating the next address. 31 is a CS address register for storing the read address of the control storage unit, 41 is a microinstruction storage register for storing the microinstruction read from the control storage unit, and 51 is a control signal c for decoding the control field CF of the microinstruction. ₁ Decoder 61 for sending ~ cm to a data processing unit (not shown), 61 is a selector for appropriately selecting the start address NEXT CS ADRS of the microprogram output from the retry control circuit and the next address of the microinstruction and setting it in the CS address register 31. is there. The selector 61 sets the address NEXT CS ADRS output from the retry control circuit 11 in the CS address register 31 during the microprogram execution (hardware operation execution), and thereafter controls the sequence of the microinstruction read into the microinstruction storage register 41. The next address in the field SF is set in the CS address register 31.
[0010]
(B) Microprogram retry control
FIG. 3 shows a retry sequence of the microprogram. The upper stage shows the state of the processor of the information processing apparatus, the interruption shows various control signals in the retry control circuit 11, and the lower stage shows the processing contents of the processor. Show.
When a program interrupt occurs due to a program exception (PROGRAM EXCEPTION) during execution of a general instruction in the process state, the program interrupt is latched, and the signal PX LCH is output until the interrupt is cleared. On the other hand, when a program exception (program error) is detected, the state shifts to the restore state, and the signal PIPELINE CLEAR becomes “1”. When the pipeline initialization is completed in the restore state, the hard operation trigger HARD OP TGR is set to “1”. Thereafter, the microprogram corresponding to the program interrupt is read from the control storage unit 21 and the program interrupt process is executed. Is done.
[0011]
If a machine check condition (hard error) ERR occurs during execution of this program interrupt, it is latched (ERROR LCH = “1”), and the hard machine check detect signal HMD becomes “1” after a predetermined time delay. As a result, the hard operation trigger HARD OP TGR becomes low level, and the program interrupt processing is interrupted. A retry possible / impossible monitoring unit described later monitors whether a retry is possible or not even if a machine check condition occurs, and the hard machine check detect signal HMD is "1". If retry is possible, the hard operation retry latch HARD OP RETRY LCH is set to high level. Further, when the hard machine check detect signal HMD becomes “1”, the state shifts to the restore state and the signal PIPELINE CLEAR becomes “1”.
[0012]
When the initialization of the pipeline is completed in the restore state, the hard operation trigger HARD OP TGR becomes “1”, and the microprogram corresponding to the held program interrupt PX LCH is read from the control storage unit 21 and the program interrupt is generated. Re-execute processing (hard operation) (retry). At this time, if the machine check condition does not occur and the program interrupt processing is completed, the end operation END OP becomes high level. As a result, the hard operation trigger HARD OP TGR and the hard operation retry latch HARD OP RETRY LCH go to a low level, and after that, a transition is made to the start state, start processing is performed, and the program interrupt latched at this time PX LCH goes low, then transitions to the process state and subsequent instructions are pipelined.
[0013]
(C) Microprogram retry control circuit
4 and 5 are configuration diagrams of the microprogram retry control circuit.
FIG. 4 is a configuration diagram of the retry possible / impossible monitoring unit, and FIG. 5 is a hardware unit such as an occurrence event holding unit, a microprogram address generation unit, a retry control unit, and the like.
In the retry possible / impossible monitoring unit 2 of FIG. 4, 2a is a flip-flop, 2b and 2c are OR gates, and 2d and 2e are AND gates.
[0014]
The flip-flop 2a is set when the execution of the instruction ends (end operation END OP = “1”) or when the pipeline is initialized in the restore state (CLEAR PIPELINE = “1”), respectively. A high-level retry point signal RETRY POINT is output. Further, the flip-flop 2a is reset by a non-retry point signal RESET RETRY HW detected by hardware such as a general instruction or by a non-retry point signal RESET RETRY MICRO detected by a micro and a retry point signal RETRY POINT Set to “0”. The AND gate 2d outputs a high-level signal ENB RETRY if the number of retries is less than the set number when the retry point signal RETRY POINT is at a high level (RETRY COUNT LESS THAN n = “1”). In the end process state, the AND gate 2e outputs a retry enable signal ENB RETRY HOP when the signal ENB RETRY is at a high level.
[0015]
That is, in the end process state, when retry is possible, and when the number of retries is less than the set number, the AND gate 2e outputs a high-level retry enable signal ENB RETRY HOP. Accordingly, when a machine check condition occurs in this state, a retry is performed as described later. However, if data is written to the register, memory, etc. due to execution of the microprogram in the end process state (hardware operation execution), or if retry is possible, or even if retry is possible, the number of retries exceeds the set number of times, The retry enable signal ENB RETRY HOP goes low, and retry is impossible.
[0016]
In FIG. 5, 1 is an occurrence event holding unit that holds an event (various interrupts, etc.) that triggers execution of a microprogram by transitioning from a process state to an end process state, and 3 is an occurrence event. A microprogram address generator for outputting the start address of a microprogram according to the above, 4 is a microprogram corresponding to the held event if a machine check condition occurs during execution of the microprogram and if a retry is possible This is a retry control unit that outputs the head address of and executes a retry.
[0017]
In the generated event holding unit 1, 1 a to 1 n are flip-flops that hold events (various interrupts, etc.) that cause the microprogram to be executed by transitioning from the process state to the end process state, and 1 s is an OR gate. When the processing enters the start state (START STATE = “1”) or when the processor stops and enters the stop state (STOP STATE = “1”), the flip-flops 1a to 1n are turned on. Reset. That is, each flip-flop 1a to 1n is set when an event that triggers execution of the microprogram in the process state occurs, and the event is processed until the processing for the event is completed or the processor is stopped. Hold.
The microprogram address generating unit 3 includes AND gates 3a to 3n and an encoder 3s. In a retryable state (ENB RETRY HOP = "1"), when a predetermined event occurs and the flip-flops 1a to 1n are set, the outputs of the AND gates 3a to 3n corresponding to the flip-flops become high level. The encoder 3s outputs the start address SW HOP CODE (0: n) of the microprogram corresponding to the generated event.
[0018]
In the retry control unit 4, 4a is an OR gate, 4b is an AND gate, 4c is a flip-flop, 4d is an AND NOT AND gate, and 4e and 4f are address selectors. When an event such as an interrupt occurs in the process state and any of the flip-flops 1a to 1n is set, the output of the OR gate 4a becomes high level. After that, when the transition to the restore state is made and the initialization of the pipeline is completed, a clear pipeline end signal CLEAR PIPELINE END is generated. The flip-flop 4c is set by this signal CLEAR PIPELINE END, and outputs a hard operation trigger signal HARD OP TGR which is a trigger for switching to a hard operation. The address selector 4e outputs the microprogram output from the microprogram address generator 3 when the hard operation trigger signal HARD OP TGR becomes high level and + ACNT0 indicating the first flow of the microprogram becomes high level. Is selected as the next read address NEXT CS ADRS and set in the CS address register 31 of FIG. Thereby, the microprogram processing corresponding to the occurrence event is started thereafter. It should be noted that the hard selector signal HARD OP TGR is at a low level or the address output from another circuit (not shown) is set in the CS address storage unit 31 from the next flow of the microprogram.
The flip-flop 4c is set when the execution of the instruction is finished (end operation END OP = “1”) or when the pipeline is initialized in the restore state (CLEAR PIPELINE = “1”). The
[0019]
4g and 4h are AND gates, 4i and 4j are flip-flops, and 4k is a status control circuit for controlling state transition.
When a machine check condition occurs (ENB RETRY HOP = "1") in the retry enabled state (HMD = "1"), the AND gate 4g outputs a high level signal SET HOP RTRY TGR to set the flip-flop 4i. . When set, the flip-flop 4i outputs a hard operation retry latch signal HARD OP RETRY LCH. In a state where retry is not possible (ENB RETRY HOP = “0”), when a machine check condition occurs (HMD = “1”), the AND gate 4h outputs a high level signal SET HK LCH and outputs the flip-flop 4j. set. When set, the flip-flop 4j outputs the hard machine check latch HK LCH.
[0020]
The status control circuit 4k makes a transition to the restore state when the machine check condition occurs in the retry enabled state and the hard operation retry latch signal HARD OP RETRY LCH becomes high level, and after the restore state ends (pipeline clear ends) After that, control is performed so as to transition to the end process state, and further, control is performed so as to transition to the start state upon successful retry.
When a machine check condition occurs in the retry impossible state and the hard machine check latch HK LCH becomes "1" (negative signal * HK LCH is "0"), all outputs of the AND gates 3a to 3n become low level. Therefore, re-execution (retry) of the microprogram is not possible.
[0021]
(D) Overall control
If a program interrupt occurs due to a program exception (PROGRAM EXCEPTION) during execution of a general instruction in the process state, one of the flip-flops 1a to 1n (FIG. 5) is set. As a result, the microprogram address generator 3 outputs the start address HARD OP CODE (0: n) of the microprogram corresponding to the generated event.
On the other hand, when the transition to the restore state is completed under the control of the status control circuit 4k by the program interrupt and the initialization of the pipeline is completed, the signal CLEAR PIPELINE END becomes high level. As a result, the flip-flop 4c is set, and the hard operation trigger signal HARD OP TGR becomes high level. When the hard operation trigger signal HARD OP TGR becomes high level and + ACNT0 indicating the first flow of the microprogram becomes high level, the address selector 4e outputs the microprogram output from the microprogram address generating unit 3. The leading address HARD OP CODE (0: n) of is set in the CS address register 31 (FIG. 2). As described above, the microprogram processing corresponding to the occurrence event starts.
[0022]
When executing a microprogram (when executing a hardware operation), the retry possible / impossible monitoring unit 2 (FIG. 4) monitors whether a retry is possible even if a machine check condition occurs. A level retry enable signal ENB RETRY HOP is output. In such a retryable state, when a machine check condition occurs (hard machine check detect signal HMD = "1"), the flip-flop 4c is reset and the flip-flop 4i is set to set the hard operation latch signal HARD OP RETRY LCH. Is output. As a result, the status control circuit 4k makes a transition from the end process state to the restore state. When the initialization of the pipeline is completed in the restore state, the flip-flop 4c is set again, and the hard operation trigger signal HARD OP TGR becomes high level. At this time, the microprogram address generation unit 3 outputs the start address HARD OP CODE (0: n) of the microprogram corresponding to the program interrupt held in the flip-flops 1a to 1n.
[0023]
Therefore, the address selector 4e sets the start address HARD OP CODE (0: n) of the microprogram corresponding to the program interrupt in the CS address register 31 again when the hard operation trigger signal HARD OP TGR becomes high level. As a result, the re-execution (retry) of the microprogram process corresponding to the occurrence event (program interruption) is started. If the retry is successful, that is, if the machine check condition does not occur and the program interrupt processing is completed, the end operation signal END OP is generated. As a result, the status control circuit 4k transitions the state to the start state, each flip-flop is reset, and then transitions to the process state to pipeline the subsequent instruction.
[0024]
On the other hand, when the machine check condition occurs in the end process state where retry is not possible, the flip-flop 4j is set and the hard machine check latch HK LCH becomes "1" (negative signal * HK LCH is “0”). For this reason, all the outputs of the AND gates 3a to 3n become the low level, the flip-flop 4c is not set, and the re-execution (retry) of the microprogram is not performed.
The present invention has been described with reference to the embodiments. However, the present invention can be variously modified in accordance with the gist of the present invention described in the claims, and the present invention does not exclude these.
[0025]
【The invention's effect】
As described above, according to the present invention, the process state is changed to the end process state, the event that triggers the execution of the microprogram is held, and during the execution of the microprogram corresponding to the event, Whether or not a retry is possible even if a machine check condition occurs is monitored, and if a machine check condition occurs during execution of a microprogram, if it is in a retryable state, it is retained Since the microprogram corresponding to the event is executed from the beginning, it is possible to retry even if a machine check condition occurs in the end process state, and the reliability of the information processing apparatus can be improved.
Further, according to the present invention, when the retry is not successful, the retry can be continued until the preset number of times is reached, and the reliability can be further improved.
Furthermore, according to the present invention, means for outputting the start address of the microprogram corresponding to the interrupt or each event is provided, and the microprogram corresponding to the generated event can be read and processed from the start address. Even if a machine check condition occurs or a retry fails, the microprogram can be retried as many times as the set number of times.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is an overall configuration diagram of the present invention.
FIG. 3 is a sequence explanatory diagram of retry control according to the present invention.
FIG. 4 is a configuration diagram of a retry enable / disable monitoring unit according to the present invention.
FIG. 5 is a configuration diagram of a microprogram retry control circuit of the present invention.
FIG. 6 is a transition state diagram in the state machine.
FIG. 7 is an explanatory diagram of a processing unit of instruction execution.
FIG. 8 is an explanatory diagram of pipeline processing.
[Explanation of symbols]
1 .. Occurrence holding section
2. ・ Retry possible / impossible monitoring part
3. Microprogram address generator
4. Retry control unit
21 .. Control memory (CS)
31. CS address register
51 .. Decoder

Claims (3)

When various interrupts or other events occur in the general instruction execution state (process state), the microprogram execution state (end process state) is processed from the process state to the event. In the retry method of the microprogram in the end process state of the processing device to which transition is made,
Holds the event that caused the microprogram to run by transitioning from the process state to the end process state,
When the microprogram corresponding to the event is executed, it is monitored whether a retry is possible even if a machine check condition occurs, and when data is written to a register or memory by executing the microprogram , Retry impossible,
When a machine check condition occurs during execution of a microprogram, if the retry is possible, the microprogram corresponding to the held event is executed from the beginning .
A microprogram retry method characterized by the above. 2. The method of retrying a microprogram in an end process state according to claim 1, wherein if the retry is not successful, the retry is continued until a preset number of times is reached. 2. The retry of a microprogram according to claim 1, further comprising means for generating a start address in a control storage unit of the microprogram corresponding to the occurrence event, and reading and executing the microprogram from the start address corresponding to the occurrence event. Method.

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