JPH01293439A - Data processor - Google Patents

Abstract

PURPOSE:To arbitrarily replace and use the information held by ROM fixedly by selecting and outputting the information read from the ROM and the alternate information read in parallel from the ROM corresponding to the information based on a control bit. CONSTITUTION:A multiplexer 7 to receive the information read from a micro ROM 4 and alternate information mucI read in parallel from a micro RAM 5 corresponding to this outputs and selects the alternate information mucI to a microinstruction register 8 when a control bit EB read in a pair with the alternate information mucI is '1.' When the control bit EB is '0,' the microinstruction read from the micro ROM 4 is outputted and selected to the microinstruction register 8. Thus, since in the function diagnosis of LSI having a large logical scale and like a complicated processor, the microprogram and the train are arbitrarily changed and the function diagnosis can be executed, the diagnosis efficiency and the reliability of the diagnosis of the LSI can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a processor that performs data processing by storing information such as microinstructions, macroinstructions, or constant data in a ROM, such as a digital signal processing device having firmware. The present invention relates to techniques that are effective when applied to functional tests for processors and communication control processors.

[Prior art]

Conventionally, microprogram control procedures in digital signal processing processors, communication control processors, and the like equipped with firmware are in the form of sequentially executing microinstructions read from a microROM based on address control by a sequence controller.

In order to easily perform functional diagnosis of such a processor, test firmware can be loaded in the ROM in advance.

An example of a document describing processors with firmware is "Microcomputer Handbook J P2" published by Ohmsha on December 25, 1985.
There are 17 to P243.

[Problem to be solved by the invention]

By the way, according to the inventor's study, in functional diagnosis of LSIs such as large-scale and complex processors, performing functional diagnosis by arbitrarily changing the microprogram or its series improves diagnostic efficiency and diagnosis. We have found that this is desirable for improving reliability.

However, with conventional technology that stores test firmware fixedly in ROM, it is difficult to arbitrarily change the contents of ROM, and moreover, test firmware for LSIs such as large processors with complex logical scale is fixedly stored in ROM. There was a problem in that the storage capacity would be enormous if it were to be stored. These problems are not limited to test firmware, but also apply to test programs that support macro instructions, as well as test information for various control tables and constant data required for multiplication. .

An object of the present invention is to provide a data processing device that can arbitrarily replace and utilize information fixedly held in a ROM. Furthermore, another object of the present invention is to provide a data processing device that can arbitrarily change the flow of data processing based on information fixedly held in a ROM.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a RAM is provided that can be accessed in parallel with the ROM and can hold information that replaces the information held in the ROM and a control bit that indicates the validity of this replacement information in correspondence with the address of the ROM. The information read from the RAM and the corresponding alternative information read in parallel from the RAM are selectively output based on the control bits.

It also has a ROM and a RAM that are accessed individually and independently based on the output address signal of the sequence controller that generates the address of the instruction, and the address set in the address setting means that can set the desired address of the instruction and the above sequence. Comparing the output addresses of the controllers and, based on the comparison result, selectively outputting an instruction held by an instruction holding means capable of holding a desired instruction or an instruction read from the ROM based on an output address signal of the sequence controller. This makes it possible to execute any instruction output from the instruction holding means instead of the ROM, or to execute an instruction read from a RAM that is accessed based on the execution of this instruction.

[For production]

According to the above-mentioned means, the information fixedly held in the ROM can be arbitrarily replaced with the information held in the RAM, etc., and the flow of data processing based on the information fixedly held in the ROM can be arbitrarily changed. It is possible to change the function diagnosis flow of an LSI such as a large and complex processor with a large logical scale based on the information held in the RAM, thereby improving the diagnostic efficiency and reliability of the diagnosis. etc.

[Embodiment 1] FIG. 1 shows the main parts of a processor that is a first embodiment of the present invention. The processor shown in the figure is, but is not particularly limited to, a dedicated processor such as a digital signal processing processor or a communication control processor that has firmware that performs data processing instructed by commands supplied from a host processor, and is a known processor. It is formed on a single semiconductor substrate such as a silicon substrate using semiconductor integrated circuit manufacturing techniques.

The processor shown in FIG. 1 is enabled to interface with an external host processor or the like via an input/output controller 1. The processor shown in FIG. As internal buses coupled to this input/output controller 1, a first bus BUS1 and a second bus BUS2 are representatively shown.

Each internal bus BUSI and BUS2 has an instruction control unit 2.
and execution unit 3 are combined.

The command control unit 2 basically sequentially generates various types of control information according to a predetermined procedure based on a series of microinstructions corresponding to commands supplied from the outside. The execution unit 3 includes various registers, arithmetic units, etc., and executes commands by performing calculations based on control information generated by the instruction control unit 2, data supplied from the outside, and the like.

The instruction control unit 2 of this embodiment has a micro ROM 4 and a micro RAM 5 that can be accessed in parallel. The micro ROM 4 fixedly holds a series of micro instructions for protocol processing and arithmetic processing that are originally necessary for a dedicated processor. As an example is shown in FIG. 2, the micro RAM 5 is capable of holding alternative information μcI for replacing the microinstruction held by the micro ROM 4, and a control bit EB indicating the validity of this replacement information μcI. Ru. In this embodiment, the control bit EB is defined as "1" being valid and "0" being invalid.

The micro RAM 5 is arranged overlappingly in the address space of the micro ROM 4, but the micro RAM of this embodiment
Since the storage capacity of the micro RAM 5 or the storage area of the alternative information μcI and the control bit EB therein is smaller than the storage capacity of the micro ROM 4, the address signal of the number of bits corresponding to the storage capacity of the micro ROM 4 is adapted to the storage capacity of the micro RAM 5. An address modification circuit 6 for converting into an address signal of the number of bits is provided, and the micro RAM 5 is supplied with the generated address signal via this. As a result, when the micro ROM 4 is addressed, a predetermined area of the micro RAM 5 corresponding to that address is also addressed in parallel, and information read from both is supplied to the multiplexer 7.

The initial setting of the address modification logic in the address modification circuit 6, for example, the setting of the value to be subtracted from the input address signal as modified information, is not particularly limited, but if the setting operation is instructed by the multi-bit mode data MODE, , possibly directly from the outside via the first bus BUS 1 and the input/output controller 1.

Alternative information μcI and for micro RAM 5.

The setting of the control bit EB is not particularly limited, but when the setting operation is instructed by the multi-bit mode data MODE, the address signal supplied from the outside via the first bus BUSI and the input/output controller 1 may be set. This is performed based on data supplied from the outside via the second bus BUS2 and the input/output controller 1.

The multiplexer 7 converts the information read from the micro ROM 4 and the alternative information μcI correspondingly read from the micro RAM 5 in parallel to the information read from the micro ROM 4.
Output is selectively controlled based on the control bit EB read out in pair with I. When the control bit EB is "1", the alternative information μcI is selected for output, and when the control bit EB is rOJ, the microinstruction read from the micro ROM 4 is selected for output.

The microinstruction, which is the information selected to be output from the multiplexer 7, is supplied to the microinstruction decoder 9 via the microinstruction register 8. The microinstruction decoder 9 decodes the microinstruction code supplied to it, generates various internal control information, and supplies this to each section.

Incidentally, the micro ROM 4 and the address modification circuit 6 are supplied with an address signal generated by the sequence controller 10. This sequence controller 10 takes in and decodes commands supplied from the outside, and receives address information supplied from a command register and command decoder 11.

It is output as the first microinstruction address for executing the command, and information in the next address field included in the previous microinstruction is selected and outputted as the address of the second and subsequent microinstructions.

Next, the operation of the first embodiment will be explained.

Specify the test mode using the mode data MODE,
In addition to initializing the address modification circuit 6, the control bit EB indicates alternative information μcI to be used in place of the microinstruction held in the micro ROM 4 and its validity.
is set in a predetermined area of the micro RAM 5 corresponding to the address of the micro R.0M4.

Here, alternative information μcI set in the micro RAM 5
is, but is not particularly limited to, a microprocessor instruction or a series thereof that should be replaced in order to change a normal microflow for functional diagnosis of a microprocessor.

After such initial settings, when a predetermined command is given for functional diagnosis of the microprocessor of this embodiment, the sequence controller issues a predetermined microinstruction to the micro ROM 4 and address modification circuit 6 based on the decoding results. Provides the first microaddress in the series.

As a result, when the micro ROM 4 is addressed, a predetermined area of the micro RAM 5 corresponding to that address is also addressed in parallel, and information read from both is supplied to the multiplexer 7.

The multiplexer 7 receives the information read from the micro ROM 4 and the corresponding alternative information μcI read in parallel from the micro RAM 5.
When the control bit EB read out as a pair with I is "1", the alternative information μC is output selected to the microinstruction register 8, and when the control bit EB is "0", the microinstruction is read out from the micro ROM 4. is selected for output to the microinstruction register 8.

Therefore, in the data processing procedure by the microprocessor, the control bit EB on the micro RAM 5 that is accessed in parallel with the micro ROM 4 is set to "1" for the normal micro flow according to the information held in the micro ROM 4.
It will be replaced by the microinstruction or its series as the alternative information μcI set in .

According to the above embodiment, the following effects can be obtained.

(1) The flow of data processing based on microinstructions fixedly held in the micro ROM 4 can be arbitrarily changed based on information held in the micro RAM 5, which is accessed in parallel with the micro ROM 4.

(2) As a result of the above effects, it becomes possible to perform functional diagnosis by arbitrarily changing the microprogram or its series in the functional diagnosis of LSIs such as large-scale and complex processors. Diagnostic efficiency and diagnostic reliability can be improved.

(3) Since it is possible to set the control information for the address modification circuit 6 and the data for the micro RAM 5 according to the control sequence inherent in the instruction control unit itself, the micro program generated by the processor itself can be stored in the micro RAM 5. It becomes possible to give the microprocessor a new function of writing data and executing data processing based on this data.

[Embodiment 2] FIG. 3 schematically shows an instruction control unit of a processor according to a second embodiment of the present invention.

The instruction control unit 20 shown in FIG. 3 differs from the above embodiment in that it sequentially generates various control information according to a predetermined procedure based on a series of microinstructions corresponding to commands supplied from the outside. However, the configuration for using the contents of the micro RAM instead of the micro ROM is different.

The instruction control unit 20 of this embodiment has a micro ROM 21 and a micro RAM 22 that can be accessed individually. The micro ROM 21 fixedly holds a series of micro instructions for protocol processing and arithmetic processing that are originally necessary as a dedicated processor.

The micro RAM 22 holds a desired sequence of micro instructions in an address space different from that of the micro ROM 21 . Therefore, micro ROM21 and micro R
Each AM 22 is accessed independently based on an address signal supplied from the sequence controller 23.

The instruction control unit 2o of this embodiment includes a micro ROM 2
It has an address setting register 24 that can set a desired address in one address space, and a comparator 25 that compares the address set in this register with the output address of the sequence controller 23. Further, the comparator 25 compares the instruction setting register 26 that can hold a desired microinstruction with the microinstruction held in the instruction setting register 26 or the instruction read out from the microROM 21 based on the output address signal of the sequence controller 23. A multiplexer 27 is provided to selectively output the results based on the results.

The output terminal of this multiplexer 27 and the micro R
The data output terminal of AM 22 is coupled to a microinstruction register 28 as shown in the first embodiment.

In addition, the above micro RAM 22, address setting register 2
4 and the instruction setting register 26, their initial values are set externally in response to the test mode, as in the first embodiment, or are set according to the control sequence inherent in the instruction control unit 20 itself.

Next, the operation of the above embodiment will be explained.

First, when replacing an instruction in the micro ROM 21 with a desired microinstruction, the microinstruction to be replaced is set in the instruction setting register 26, and the address of the microinstruction to be replaced is set in the address setting register 24. I'll keep it. As a result, when the address output from the sequence controller 21 matches the address in the address setting register 24, the output control signal COMP of the comparator 25 detecting this causes the multiplexer 27 to select the microinstruction stored in the instruction setting register 26. It is given to the microinstruction register 28 in place of the microinstruction in the ROM 21. Thereby, the instruction control unit 20 performs the processing instructed by the microinstruction.

Next, a description will be given of an operation in which the flow of data processing based on information fixedly held in the micro ROM 21 is arbitrarily changed based on information held in the micro RAM 22.

At this time, the instruction setting register 26 contains the micro RAM 22.
A branch instruction for accessing a predetermined area of the micro ROM 21 is stored, and the address of the branch instruction to be inserted in the series of micro instructions in the micro ROM 21 is set in the address setting register.

As a result, when the address output from the sequence controller 21 matches the address of the address setting register 24, the multiplexer 27 transfers the microinstruction stored in the instruction setting register 26 to the microROM 21 by the output control signal of the comparator 25 that detects this. is given to the microinstruction register 28 in place of the microinstruction. The instruction control unit 20 performs branch processing of the microflow specified by the microinstruction, and the series of microinstructions to be executed next is transferred from the microRAM 22 to the microinstruction register 2.
7 are given sequentially.

Therefore, the flow of data processing based on the microinstructions fixedly held in the microROM 21 can be arbitrarily changed based on the instructions held in the instruction setting register 26 and the information held in the microRAM 22 of the branch destination branched by the instruction. It can be made possible. As a result, when diagnosing the function of an LSI such as a large and complex processor with a large logical scale, it becomes possible to perform the function diagnosis by arbitrarily changing the microprogram or its series. The diagnostic efficiency and reliability of diagnosis can be improved.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, the command control unit and internal bus configuration are not limited to the above embodiments, and can be modified as appropriate.

Further, the micro RAM may be configured to utilize a partial area of the data memory.

In the above explanation, the invention made by the present inventor will mainly be applied to dedicated processors such as digital signal processing processors and communication control processors that have firmware that performs data processing instructed by commands, which is the field of application that formed the background of the invention. Although the case where the present invention is applied has been described, the present invention is not limited thereto, and can be applied to various other data processing devices. RAM or ROM
The information held is not limited to the microinstructions configuring the test firmware, but can also be other microinstructions, macroinstructions, and even information for configuring control tables and data tables. The present invention is capable of replacing at least the contents of ROM with an arbitrary address,
It can be applied to conditions for data processing by adding desired information to any address.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, information fixedly held in ROM can be arbitrarily RA
This has the effect that it can be used in place of the information held in M, and the flow of data processing based on the information fixedly held in the ROM can be arbitrarily changed based on the information held in the RAM. This makes it possible to arbitrarily change the functional diagnostic flow of an LSI such as a processor with a large logical scale and complexity, thereby improving the diagnostic efficiency and reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a processor according to the first embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of alternative information and control bits held in the micro RAM, and FIG. 3 is a diagram showing the present invention. FIG. 2 is a block diagram showing main parts of an instruction control unit in a processor according to a second embodiment of the present invention. 1...Input/output controller, BUSI, BUS2...
- Internal bus, 2... Instruction control unit, 3... Execution unit, 4... Micro ROM, 5... Micro RAM, μcI... Alternative information, EB... Control bit, 6...・Address modification circuit, 7... Multiplexer, 8... Micro instruction register, 9.
...Microinstruction decoder, 10...
Sequence controller, 11... Command register and command decoder, 20... Instruction control unit,
21...Micro ROM, 22...Micro R△M
, 23... Sequence controller, 24... Address setting register, 25... Comparator, 26...
- Instruction setting register, 27... multiplexer.

Claims (1)

[Claims] 1. It has a ROM and a RAM that can be accessed in parallel, and the RAM stores information that replaces the information held in the ROM and a control bit that indicates the validity of this replacement information, corresponding to the address of the ROM. and a selection circuit that selectively outputs the information read from the ROM and corresponding alternative information read in parallel from the RAM based on the control bit. data processing equipment. 2. The ROM stores microinstructions, and the replacement information held by the RAM is microinstructions that should replace the microinstructions stored in the ROM, as set forth in claim 1. data processing equipment. 3. The RAM is supplied with an address signal via an address modification circuit that converts an address signal with a number of bits corresponding to the storage capacity of the ROM into an address signal with a number of bits that matches the size of a predetermined storage area of the RAM. 3. The data processing device according to claim 2, wherein the data processing device is a data processing device. 4. An address setting means having a ROM and a RAM that are accessed independently based on the output address signal of the sequence controller that generates the address of the instruction, and capable of setting a desired address of the instruction, and the address set thereon and the above. A means for comparing output addresses of the sequence controller, an instruction holding means capable of holding a desired instruction, and the above-mentioned comparison of the instruction held by the instruction holding means or the instruction read out from the ROM based on the output address signal of the sequence controller. A data processing device comprising a selection means for selectively outputting an output based on a comparison result by the means, and an instruction register coupled to an output terminal of the selection means and an output terminal of the RAM. . 5. A patent claim characterized in that the RAM has a series of instructions different from the instructions held in the ROM, and the instruction holding means stores a branch instruction for accessing a predetermined area of the RAM. The data processing device according to item 4.