JP2006221606A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor capable of identifying whether a function to be deleted in the future or a function newly added or changed this time is used or not. <P>SOLUTION: In this data processor, a first control register (24) is used for holding of first information (SIFI) for selectively instructing to make execution of a part of instructions of an instruction set executable in the data processor impossible. An instruction decoder (22) executably decodes the part of instructions when the first information is a first value, decodes the part of instructions such that an exception factor code (ECCDI) distinguishable from the other exception factor can be generated when the first information is a second value, and makes an instruction execution procedure transit to execution of a prescribed exception processing program. When considering to coping with the next machine type, the second value is set to the first information, and software is executed, so that use of an instruction not supported in the future or use of an instruction added or changed this time can be detected by exception occurrence. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an upward compatibility technique in a data processor, and relates to a technique effective when applied to, for example, a microcomputer for device embedded control.

  In order to maintain compatibility, the upper compatible microcomputer can use the instruction set and functions of the lower microcomputer. However, an excessive control logic must be installed only for maintaining compatibility, and the speeding up of data processing may be hindered. With respect to upward compatibility of microcomputers, Patent Document 1 discloses a data processing apparatus capable of increasing the number of general-purpose registers while maintaining upward compatibility. That is, register designation information for designating a register is divided into two parts. These two parts are arranged in different basic units on the basic unit of the instruction code. If one instruction code is omissible and the omissible instruction code is omitted, the control unit (CONT) performs a register selection operation implicitly assuming predetermined register designation information. According to this, if only the implicitly-designable general-purpose register (existing general-purpose register) is used, the instruction code that can be omitted can be omitted, and the instruction code is not increased. If at least a conventional equivalent general-purpose register is used, a conventional equivalent instruction code may be used. By not increasing the instruction code, the processing speed is not reduced.

Japanese Patent Laid-Open No. 2001-202243

  This inventor examined the case where the upper compatibility with respect to a part of function was canceled with respect to a future next microcomputer. Some of the current users may be using the functions that are scheduled to be withdrawn. In the case of an upward compatible microcomputer, the existing software may be diverted to the next model, so the user needs to confirm that the function to be canceled is not used before the next model is adopted. If you are using features that you plan to withdraw, you will need to modify the software. If some instructions are deleted from the instruction set of the existing model in the next model, an attempt to execute the deleted instruction in the next model is usually made an exception processing target as an “illegal instruction”. In addition, if access to some areas in the user mode is prohibited for the address space of the existing model in the next model, attempting to access the address will be subject to exception processing as "illegal access (address error)" . Since the occurrence of such an exception is not monitored for all operations, a runaway may occur depending on the setting for exception handling. From the viewpoint of the stable operation of the system, it is desirable to modify the program so as to suppress the occurrence of such exception processing as much as possible.

  However, the conventional microcomputer does not have a function for easily confirming whether a function scheduled to be deleted in the future (unsupported function) is used in existing software diverted from the lower side. The exception due to the above “illegal instruction” or “address error” can only be determined whether a function that is not supported is used. In short, by making it possible to identify whether or not the next model uses a function that is “unsupported”, there is no means for prompting software modification before it becomes unsupported.

  Further, the conventional microcomputer has a function whose specification is newly changed from an existing model (in other words, an additional function which is newly “supported” or a function whose support content is changed (hereinafter referred to as a changed function). ) Are not easily identified. The support content is determined by the specifications of the microcomputer. When diverting existing software, it is conceivable that a defect related to the additional function or the change function may occur. Therefore, it is important to identify whether an additional function or a change function is used.

  An object of the present invention is to provide a data processor capable of identifying whether or not a function scheduled to be deleted in the future is used.

  Another object of the present invention is to provide a data processor capable of prompting correction of functions scheduled to be deleted in the future for software diverted to an upward compatible microcomputer.

  Still another object of the present invention is to provide a data processor that can identify whether an additional function or a change function is used.

  Still another object of the present invention is to provide a data processor capable of easily verifying whether there is any influence or malfunction caused by an additional function or a change function when diverting existing software in a microcomputer having an additional function or a change function. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A data processor that supports a plurality of functions by executing an instruction has a control register and a decoder, and the control register uses a part of functions (supported functions) that can be realized by the data processor. The decoder is used to hold instruction information that selectively indicates disabling, and the decoder detects an operation that attempts to use a part of the function that is disabled by the support control register, and Hold the detection result.

  Some of the functions are functions that may be unsupported in the future. In this case, because it has hardware that detects the use of functions that will be unsupported in the future during software execution, it will prompt users to continually divert existing software or modify the software in the next model. It can be used to isolate problems when trouble occurs.

  The part of the functions is an additional function that is newly supported, or a function in which the support content is changed (change function). In this case as well, it is possible to detect the use of newly added or changed functions during software execution, so it is easy to verify whether there are any effects or defects caused by the added or changed functions. When a trouble occurs, it can be used to specify a debug part or a notice part.

  [2] << Unsupported for a specific instruction >> The data processor includes an instruction execution control unit and an exception control unit, and the exception control unit includes a first control register (24), and the first control register Is used to hold first information (SIFI) for selectively instructing that some instructions in the instruction set executable by the data processor are not executable, and the instruction execution control unit uses an instruction decoder. And the instruction decoder performs decoding that can be executed on the part of instructions when the first information is a first value, and the part when the first information is a second value. The instruction is decoded to generate an exception factor code that can be distinguished from other exception factors, and the instruction execution is shifted to the execution of a predetermined exception processing program.

  Assume that the part of the instructions are, for example, future unsupported instructions. If the first value is set in the first information before the part of the instruction becomes a non-support instruction, the part of the instruction is normally executed. When considering compatibility with the next model, if the second value is set in the first information, the use of some of the instructions that will be unsupported in the future during software execution is an exception. It can be detected by occurrence. Even when some of the instructions are instructions that have been added or changed this time, the execution of the instructions can be detected in the same manner.

  In one specific form of the present invention, the instruction execution control unit is a central processing unit, and the first control register is readable and writable by the central processing unit. Further, it may be set according to the state of the external terminal at the time of reset.

  In another specific form of the present invention, the exception control unit has an exception factor register that holds an exception factor code, and the instruction execution control unit receives an instruction address held by a program counter when an exception occurs. It has a stack register to hold.

  In still another specific form of the present invention, the instruction execution control unit controls to store the exception factor code and the instruction address that caused the exception by transitioning to execution of the predetermined exception handling program. Is possible. As described above, the data processor can store the history of exception factors in the exception processing program.

  In still another specific form of the present invention, the instruction execution control unit saves the exception factor code and the instruction address that caused the exception by transitioning to execution of the predetermined exception handling program. After that, it is possible to finish the execution of the predetermined exception handling program by executing the instruction that caused the exception. This not only detects that the specific instruction is about to be executed, but also ensures that the specific instruction is completely executed.

  [3] << No support for access to specific address area >> The data processor includes an instruction execution control unit, an exception control unit, and a bus control unit, and the exception control unit includes a first control register (24), The first control register is used for holding second information (SIFA) for selectively instructing to disable access to a part of addresses in the address space of the data processor, and the bus control unit has an address A decoder (32), wherein the address decoder permits an access request to the partial address when the second information is a first value, and when the second information is a second value. In response to an access request to the partial address, an address error signal (AERR) is generated, and the instruction execution control unit is responsive to the address error signal to distinguish from other exception factors. Generate exception code as possible to transition the instruction execution to the execution of the predetermined exception processing program.

  Assume that the access to the partial address is, for example, a future unsupported address. Before the access to the partial address is not supported, if the first value is set in the second information, the access to the partial address is permitted. When considering the compatibility with the next model, if the second value is set in the second information, access to the partial address that will be a non-support address in the future during software execution is used. Can be detected by the occurrence of an exception. Even when the partial address is made accessible this time or the access form is changed, access to the address can be detected in the same manner.

  In one specific form of the present invention, the address space that can be instructed to be selectively inaccessible by the first control register is both an internal address space and an external address space of the data processor. is there.

  In another specific form of the present invention, the exception control unit has an exception factor register that holds an exception factor code, and the instruction execution control unit receives an instruction address held by a program counter when an exception occurs. It has a stack register to hold.

  [4] << Not supported for specific function setting >> The data processor responds to the instruction execution control unit, the exception control unit, and the function designation information (FSIF) set in the function designation register (40) by the instruction execution control unit. Other function blocks for selecting a function are included, the exception control unit has a first control register (24), and the first control register is a part of predetermined function setting by the function control information. The other functional block has a decoder (41), and the decoder has the third information (SIFR) for selectively instructing to disable the third information. When the value is 1, the designation of the part of the predetermined function to the function designation register is allowed. When the third information is the second value, the part of the predetermined function to the function designation register is allowed. Against specification A register error signal (RERR) is generated, and the instruction execution control unit generates an exception factor code that can be distinguished from other exception factors in response to the register error signal to execute the instruction execution of a predetermined exception processing program Transition to.

  Assume that the predetermined functions are, for example, future unsupported functions. If the first value is set in the third information before the predetermined functions are not supported, the predetermined functions are also used. When considering support for the next model, if the second value is set in the third information, the use of some of the functions that will be unsupported in the future during software execution is an exception. It can be detected by occurrence. Even when some of the predetermined functions are functions added or changed this time, the use of the predetermined functions can be detected in the same manner.

  In one specific form of the present invention, the exception control unit has an exception factor register that holds an exception factor code, and the instruction execution control unit receives an instruction address held by a program counter when an exception occurs. It has a stack register to hold.

  [5] << Not supported for specific instructions >> The data processor has an instruction execution control unit and an exception control unit, the exception control unit has a support control register, and the support control register can be executed by the data processor. The instruction execution control unit includes a decoder, and the decoder is controlled by the support control register. When a part of instructions instructed to be inexecutable is decoded, a factor code unique to the predetermined instruction is generated and held.

  Based on the factor code, it is possible to detect the use of some of the instructions that will be unsupported in the future during software execution. The execution of the newly added or changed instruction can be detected in the same manner.

  [6] << Unsupported access to specific address area >> The data processor includes an instruction execution control unit, an exception control unit, and a bus control unit, the exception control unit includes a support control register, and the support control register includes: Used to hold instruction information for selectively instructing to disable access to a part of the address space of the data processor, the bus control unit has a decoder, and the decoder is instructed by the support control register In response to the detection of the access request, the instruction execution control unit generates and retains a factor code unique to the factor.

  Based on the factor code, it can be detected that the access to the partial address which is assumed to be a non-support address in the future is used during software execution. Access to addresses that have been made accessible this time for some addresses or whose access form has been changed can be similarly detected.

  [7] << Not supported for specific function setting >> The data processor has an instruction execution control unit, an exception control unit, and other functions for which a function corresponding to the control information set in the function control register is selected by the instruction execution control unit. The exception control unit has a support control register, and the support control register is an instruction information for selectively instructing that setting of some control information to the function control register is disabled. The other functional block has a decoder, and the decoder can detect a setting of a part of control information instructed to be not set by the support control register, and the instruction execution control unit In response to detection of the setting of some control information instructed that the setting is impossible, a factor code specific to the factor is generated and held.

  Based on the factor code, it is possible to detect the use of some of the functions that will be unsupported in the future during software execution. The use of the function added or changed this time can be detected in the same manner.

  [8] << Not supported for function setting of external terminal >> The data processor has an external terminal used for function setting according to the state. The partial function is a function set using the external terminal.

  From the above, it is possible to detect that an operation mode or the like that will be unsupported in the future has been set using an external terminal such as a mode terminal. Similarly, it can also be detected that an operation mode newly added or changed this time is set.

  [9] << Non-support for external interface function setting >> The data processor has an external interface circuit connectable to the outside. The partial function is a control function using the external interface circuit.

  From the above, it is possible to detect the use of a specific command interface function or the like that will be unsupported in the future during software execution based on the factor code. Similarly, it can be detected that a command interface function newly added or changed this time is used.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  It is possible to urge modification of functions that are scheduled to be deleted in the future for software diverted to an upward compatible microcomputer. That is, it is possible to identify whether or not a function scheduled to be deleted in the future is used.

  When diverting existing software with a microcomputer having an additional function or a change function, it is possible to easily verify whether the additional function or the change function is operating normally. That is, it is possible to identify whether the additional function or the change function is used.

<Microcomputer>
FIG. 1 illustrates a microcomputer (MCU) 1. The microcomputer 1 shown in the figure is not particularly limited, but is formed as a semiconductor integrated circuit on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

  The microcomputer 1 performs a data transfer process, a central processing unit (CPU) 2 as an instruction execution control unit, a cache memory (CACH_MRY) 3, a bus state controller (BSC) 7 for performing bus control such as a data bus / address bus, etc. A direct memory access controller (DMAC) 8 and an external bus interface circuit (EXBIF) 9 for controlling transfer between the internal circuit and the external circuit are included. The central processing unit 2 and the cache memory 3 are connected by a first internal bus 16 including an address bus (ABUS1) and a data bus (DBUS1). The bus state controller 7 is connected to the cache memory 3, the direct memory access controller (DMAC) 8, and the external bus interface circuit 9 via a second internal bus 17 including an address bus (ABUS2) and a data bus (DBUS2). Connected. Further, the bus state controller 7 is coupled to various peripheral circuits via a peripheral bus 18 including an address bus (ABUS3) and a data bus (DBUS3). An external bus 19 connected to the outside and the inside of the microcomputer 1 is connected to the external bus interface circuit 9. Although not shown, the second internal bus has a read-only memory (ROM) that can store a program that can be executed by the central processing unit 2, and a random access memory that can be used as a work area of the central processing unit 2. Various memories such as (RAM) may be connected.

  Further, the microcomputer 1 has a power supply terminal Vcc and a ground terminal (circuit ground potential terminal) GND, and the power supply terminal Vcc supplies operating power to each circuit module in the microcomputer 1. When the operation power supply from the power supply terminal Vcc is stopped, the operation power supply to the circuit modules in the microcomputer 1 such as the central processing unit 2 and the cache memory 3 is cut off.

  The cache memory 3 includes an instruction cache (ICACH) 5 for storing instructions processed by the central processing unit 2, a data cache (DCACH) 6 for storing data to be operated, and a cache controller for controlling the cache memory (CACH_CNT) 4 is included.

  Peripheral circuits included in the microcomputer 1 include, for example, a clock pulse generator (CPG) 11, an interrupt controller (INTC) 12 as an exception control unit, a serial communication interface (SCI) 13, and a real time clock (RTC). 14, timer unit (TMU) 15 and the like. Although not shown, a random access memory (RAM) or a nonvolatile memory (ROM, flash memory, etc.) may be incorporated.

  An external bus 19 including an address bus (ABUS4) and a data bus (DBUS4) includes an external memory (EXMRY) such as a random access memory (RAM), a read only memory (ROM), and a flash memory (Flash). 10) Further, although not particularly shown, peripheral circuits such as a data input / output device and a display device are connected.

  The address of the instruction executed by the central processing unit 2 is taken into the instruction cache 5 in the cache memory 3 via the first internal bus 16. When an instruction corresponding to the address is stored in the instruction cache 5, the instruction corresponding to the address is transferred to the central processing unit 2, and the transferred instruction is fetched to the central processing unit 2. In the central processing unit 2, the fetched instruction is decoded and data operation processing is performed in accordance with the instruction. Further, the data address used for the data operation processing in the central processing unit 2 is taken into the data cache 6 in the cache memory 3 via the first internal bus 16. When data corresponding to the address is stored in the data cache 6, the data corresponding to the address is transferred to the central processing unit 2, and the transferred data is fetched to the central processing unit 2. The central processing unit 2 uses the fetched data for data calculation processing and the like. When the instruction or data corresponding to the address supplied from the central processing unit 2 is not stored in the cache memory 3, the bus state controller 7 accesses the memory 10 according to the instruction of the cache controller 4, and the instruction obtained thereby And the data are stored in the cache memory 3 and fetched by the central processing unit 2. Further, when the Mikoro computer has a memory inside, it is possible to read or write instructions or data corresponding to addresses from the built-in memory.

  The microcomputer 1 includes those that are scheduled to cease upward compatibility for some functions from the next model. For example, (1) non-support for specific instructions, (2) non-support for access to specific address areas, (3) non-support for specific function settings, (4) There are five types: non-support for setting functions set using external terminals, and (5) non-support for use of control functions using an external interface circuit. The microcomputer 1 has hardware for detecting the use of the above function that will be unsupported in the future during software execution. The hardware will be described in detail below.

<Not supported for specific instructions>
FIG. 2 illustrates a configuration in which specific instructions are selectively unsupported. Here, CPU2 and INTC12 are illustrated. The CPU 2 includes an instruction execution unit (IEXEC) 21, an instruction decoder (IDEC) 22, and a stack register (STCREG) 23 that are representatively shown. The instruction execution unit 21 includes a plurality of general-purpose registers, an instruction register, a program counter, a computing unit, a sequence control unit, and the like, although not particularly illustrated. The sequence control unit responds to an interrupt request, an exception request, etc., and controls the instruction execution procedure in response to a branch instruction. The instruction decoder 22 decodes the instruction fetched into the instruction register and generates a control signal. The stack register 23 holds the value of the program counter when an interrupt or exception occurs. The INTC 12 gives an interrupt request or an exception request to the CPU 2 in accordance with a predetermined priority for the occurrence of an interrupt or an exception. The INTC 12 includes a support control register (SCREG) 24 and an exception factor register (ECFREG) 25, which are representatively shown as control registers. The support control register 24 is used to hold instruction support control information SIFI that selectively instructs the execution of a part of the instruction set of the microcomputer 1 to be disabled. The instruction support control information SIFI can be written to the support control register 24 by register access by the CPU 2. The instruction decoder 22 performs executable decoding on the part of instructions when the instruction support control information SIFI is a first value, and the part when the instruction support control information SIFI is a second value. The instruction execution procedure is shifted to the execution of a predetermined exception processing program by the control signal ECPI while performing decoding capable of generating an exception factor code ECCI that can be distinguished from other exception factors. An exception handling program means an exception handling routine or exception handler. When the exception factor code ECCI is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the program counter at that time. For example, the exception processing program reads the value of the exception factor register 25 and displays the read exception factor code ECCI on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. The process of accumulating the exception cause code ECCI to be stored in the external memory 10 or the like is controlled.

  Here, it is assumed that the some instructions are future non-support instructions. If the first value is set in the instruction support control information SIFI before the part of the instruction becomes a non-support instruction, the part of the instruction is normally executed. When considering support for the next model, if the second value is set in the instruction support control information SIFI, the use of some of the instructions that will be unsupported in the future during software execution is an exception. Can be detected by the occurrence of. The exception factor register 25 may be configured to store a plurality of exception factor codes ECCI.

《Access not supported for specific address area》
FIG. 3 illustrates a configuration in which access is not supported for a specific address area. Here, CPU2, INTC12, and BSC7 are illustrated. The CPU 2 includes an instruction execution unit (IEXEC) 21, an instruction decoder (IDEC) 22, and a stack register (STCREG) 23, which are representatively shown in FIG. The INTC 12 includes a support control register (SCREG) 24 and an exception factor register (ECFREG) 25, which are representatively shown as control registers, as in FIG. In FIG. 3, an exception request control unit (ECCNT) 31 is shown for the purpose of explaining an exception event occurring in the BSC 7 outside the CPU 2.

  Here, the support control register 24 is used to hold address support control information SIFA that selectively instructs to disable access to some addresses in the address space of the microcomputer 1. The address support control information SIFA can be written to the support control register 24 by register access by the CPU 2. The BSC 7 has an address decoder (ADEC) 32. The address decoder (ADEC) 32 receives and decodes the access address AADR, the access strobe signal ASRB, etc. output from the CPU 2. The address decoder (ADEC) 32 permits an access request to the partial address when the address support control information SIFA is a first value. When the address support control information SIFA is a second value, an address error signal AERR is supplied to the exception request control unit 31 in response to an access request to the partial address. In response to the address error signal AERR, the exception request control unit 31 requests the CPU 2 for exception processing by the exception request signal EXREQ. In response to this, the CPU 2 shifts the instruction execution procedure to the execution of a predetermined exception processing program, generates an exception factor code ECCA that can be distinguished from other exception factors, and sets it in the exception factor register 25. When the exception factor code ECCA is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the program counter at that time. For example, the exception processing program reads the value of the exception factor register 25 and displays the read exception factor code ECCA on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. The process of accumulating the exception factor code ECCA in the external memory 10 or the like is controlled.

  Here, it is assumed that the access to the partial address is a future unsupported address. Before the access to the partial address becomes unsupported, if the first value is set in the address support control information SIFA, the access to the partial address is permitted. When considering the support for the next model, if the second value is set in the address support control information SIFA, access to the partial address that will be a non-support address in the future during software execution Use can be detected by the occurrence of an exception.

<Not supported for specific function settings>
FIG. 4 illustrates a configuration that is not supported for a specific function setting. Here, CPU2, INTC12, BSC7, and TMU15 are typically exemplified. The CPU 2 includes an instruction execution unit (IEXEC) 21, an instruction decoder (IDEC) 22, and a stack register (STCREG) 23, which are representatively shown in FIG. The INTC 12 includes a support control register (SCREG) 24, an exception factor register (ECFREG) 25, and an exception request control unit (ECCNT) 31, which are representatively shown as control registers, as in FIG. The TMU 15 selects a function corresponding to the function specifying information FSIF set in the function specifying register (FREG) 40. For example, timer count up or interrupt generation condition selection is performed.

  Here, the support control register 24 is used for holding the function support control information SIFR that selectively instructs the setting of a part of the functions that can be set by the function specifying information FSIF to be disabled. The The function support control information SIFR can be written to the support control register 24 by register access by the CPU 2. The TMU 15 has a decoder (DEC) 41. When the function support control information SIFR has a first value, the decoder 41 allows the predetermined function to be specified for the function specifying register 40, and when the function support control information SIFR has a second value. A register error signal RERR is supplied to the exception request control unit 31 in response to the designation of some of the predetermined functions to the function designation register 40. In response to the register error signal RERR, the exception request control unit 31 requests the CPU 2 for exception processing by the exception request signal EXREQ. In response to this, the CPU 2 shifts the instruction execution procedure to the execution of a predetermined exception processing program, generates an exception factor code ECCR distinguishable from other exception factors, and sets it in the exception factor register 25. When the exception factor code ECCR is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the program counter at that time. For example, the exception processing program reads the value of the exception factor register 25 and displays the read exception factor code ECCR on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. The process of accumulating the exception factor code ECCR to be stored in the external memory 10 or the like is controlled.

  Here, it is assumed that some of the predetermined functions, for example, some timer count-up conditions are future non-support functions. If the first value is set in the function support control information SIFR before the predetermined functions are not supported, the predetermined functions are also used. When considering support for the next model, if the second value is set in the function support control information SIFR, the use of some of the functions that will be unsupported in the future during software execution is an exception. Can be detected by the occurrence of.

  When the exception cause code ECCR is set in the exception cause register 25, the stack register 23 holds the instruction address FADR of the program counter at that time, thereby storing an instruction or function that is not supported. It is possible to specify the function, and by using the instruction by the user, it is possible to avoid the use of a function that will not be supported in the future.

<Not supported for functions set using external terminals>
FIG. 5 illustrates a configuration in which setting of functions set using a specific external terminal is selectively unsupported. Here, the CPU 2, the INTC 12, and the system control unit (SYSCNT) 45 that controls the function settings of the entire microcomputer 1 are exemplified. The CPU 2 includes an instruction execution unit (IEXEC) 21, an instruction decoder (IDEC) 22, and a stack register (STCREG) 23, which are representatively shown in FIG. The INTC 12 includes a support control register (SCREG) 24, an exception factor register (ECFREG) 25, and an exception request control unit (ECCNT) 31, which are representatively shown as control registers, as in FIG. The system control unit 45 has a mode decoder (MDEC) 46. The mode decoder 46 receives a control signal for setting the function via mode terminals MD0 to MD3 used for setting the function according to the state.

  Here, the support control register 24 holds the external terminal support control information SIFE that selectively indicates that some of the predetermined functions among the functions set using the mode terminals MD0 to MD3 cannot be set. Used for The external terminal support control information SIFE can be written to the support control register 24 by register access by the CPU 2.

  A mode decoder 46 included in the system control unit 45 decodes the control signal input from the mode terminals MD0 to MD3, and outputs the decoded result to a peripheral circuit or the like as a mode setting signal 48, for example. Instruct mode setting. The mode decoder 46 allows the setting request for the part of predetermined functions when the external terminal support control information SIFE is a first value. When the external terminal support control information SIFE is a second value, an external terminal error signal EERR is supplied to the exception request control unit 31 in response to the setting request for some of the predetermined functions.

  In response to the external terminal error signal EERR, the exception request control unit 31 requests the CPU 2 for exception processing by the exception request signal EXREQ. In response to this, the CPU 2 shifts the instruction execution procedure to the execution of a predetermined exception processing program, generates an exception factor code ECCE that can be distinguished from other exception factors, and sets it in the exception factor register 25. When the exception factor code ECCE is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the program counter at that time. For example, the exception handling program reads the value of the exception factor register 25 and displays the read exception factor code ECCE on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. The processing for accumulating the exception factor code ECCE to be stored in the external memory 10 or the like is controlled.

  Here, it is assumed that some of the predetermined functions, for example, some of the operation modes are future unsupported functions. If the first value is set in the function support control information SIFE before the predetermined functions are not supported, the setting of the predetermined functions is allowed. When considering the compatibility with the next model, if the second value is set in the function support control information SIFE, it will be unsupported in the future using external terminals such as mode terminals MD0 to MD3. It can be detected by the occurrence of an exception that the operation mode has been set.

《Non-support for control function using external interface circuit》
FIG. 6 illustrates a configuration in which use of a control function using an external interface circuit is selectively unsupported. Here, the CPU 2, the INTC 12, the interface control unit (IFCNT) 50, and the external device (EXDVC) 60 are exemplified. The CPU 2 includes an instruction execution unit (IEXEC) 21, an instruction decoder (IDEC) 22, and a stack register (STCREG) 23, which are representatively shown in FIG. The INTC 12 includes a support control register (SCREG) 24, an exception factor register (ECFREG) 25, and an exception request control unit (ECCNT) 31, which are representatively shown as control registers, as in FIG. The interface control unit 50 corresponds to the external bus interface circuit 9 of FIG. The interface control unit 50 is connected to the external device 60 via the external bus 19. The interface control unit 50 controls the start of the external bus cycle according to the external bus access control by the bus state controller 7. In addition, when the interface control unit 50 accepts a specific access command from the outside, the interface control unit 50 permits access to the on-chip RAM (not shown) from the outside. An on-chip RAM (not shown) is connected to, for example, internal buses DBUS3 and ABUS3.

  Here, the support control register 24 is external device support control information for selectively instructing to disable a part of predetermined functions among the control functions using the interface circuit, for example, a response function to the specific access command. Used to hold SIFD. The external device support control information SIFD can be written to the support control register 24 by register access by the CPU 2.

  The interface control unit 50 allows a request to use a response function for the specific access command when the external device support control information SIFD is a first value. When the external device support control information SIFD is the second value, an external device error signal DERR is supplied to the exception request control unit 31 in response to a request for using a response function for the specific access command.

  In response to the external device error signal DERR, the exception request control unit 31 requests the CPU 2 for exception processing by the exception request signal EXREQ. In response to this, the CPU 2 shifts the instruction execution procedure to execution of a predetermined exception processing program, generates an exception factor code ECCD that can be distinguished from other exception factors, and sets it in the exception factor register 25. When the exception factor code ECCD is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the program counter at that time. For example, the exception processing program reads the value of the exception factor register 25 and displays the read exception factor code ECCDD on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. The process of accumulating the exception factor code ECCD to be stored in the external memory 10 or the like is controlled.

  Here, it is assumed that some of the predetermined functions, for example, some specific command interface functions are future unsupported functions. If the first value is set in the function support control information SIFD before the predetermined functions are not supported, the use of the predetermined functions is permitted. When considering compatibility with the next model, if the second value is set in the function support control information SIFD, a specific command interface function that will be unsupported in the future during software execution is used. Can be detected by the occurrence of an exception. The predetermined functions are not limited to specific command interface functions, but may be a response function to specific operation instruction commands given from the master processor when the microcomputer 1 is a slave processor, for example.

  According to the microcomputer 1, since it has hardware for detecting the use and setting of functions that will be unsupported in the future during software execution, it prompts the user who continuously diverts the existing software to modify the software. Can be used to isolate problems when trouble occurs in the next model. As a result, the microcomputer user can be provided with a means for easily detecting functions that will not be supported in the future by means of the hardware. Can be changed to unsupported, and design bottlenecks such as stopping the installation of excessive control logic just to maintain compatibility can be removed.

《Not supported for specific instruction by superscalar》
FIG. 7 illustrates a configuration in which specific instructions are selectively unsupported when the CPU is a superscalar. Here, CPU 2A and INTC 12 are exemplified. Unlike the CPU 2 shown in FIG. 2, the CPU 2A has two pipeline control systems 33A and 33B inside, and has a superscalar configuration. That is, the CPU 2A includes a pipeline control system 33A including an instruction decoder (IDEC) 22A and an instruction execution unit (IEXEC) 21A, a pipeline control system 33B including an instruction decoder 22B and an instruction execution unit 21B, and CPU resources ( CPURESC) 34, pipeline control unit (PIPCNT) 37, and instruction sequence control unit (ISQCNT) 70. The CPURESC 34 includes an arithmetic unit (ALU) 35, a general-purpose register (GREG) 36, and an instruction stack register (STCREG) 23. The instruction sequence control unit 70 includes an instruction issue control unit (IFCNT) 71 and an instruction buffer (IBUF) 72.

  The INTC 12 includes a support control register (SCREG) 24 and an exception factor register (ECFREG) 25, which are representatively shown as control registers, as in FIG. The instruction sequence control unit 70 controls instruction prefetching. Instruction fetch is performed from the cache array 3 via the instruction fetch bus 38. The instruction sequence control unit 70 sequentially stores the prefetched instructions in the instruction buffer 72. The CPU resource 34 uses the operand fetch bus 39 when performing operand fetch and operation result writing as required. The instruction fetch bus 38 and the operand fetch bus 39 are collectively referred to as the internal bus 16 in FIG. The instruction issuance control unit 71 supplies the instruction (INST) and the instruction address (IA) stored in the instruction buffer 72 to the instruction decoders 22A and 22B in parallel. The decoding results by the instruction decoders 22A and 22B are given to the pipeline control unit 37, and the dependency of instruction execution in both pipelines is determined. The decoding results and the like by the instruction decoders 22A and 22B are also given to the instruction execution units 21A and 21B. The instruction execution units 21 </ b> A and 21 </ b> B control parallel instruction execution or serial instruction execution using the CPU resource 34 according to the determination result by the pipeline control unit 37.

  Here, the support control register 24 is used for holding the instruction support control information SIFI shown representatively as in FIG. The instruction support control information SIFI can be written to the support control register 24 by register access by the CPU 2A. The instruction decoders 22A and 22B perform decoding that can be executed on the part of instructions when the instruction support control information SIFI is a first value. The instruction decoders 22A and 22B generate an exception factor code ECCI that can be distinguished from other exception factors for the part of instructions when the instruction support control information SIFI is a second value, and determine an instruction execution procedure. Transition to the execution of the exception handling program. The exception factor code ECCI is set in the exception factor register 25.

  Further, when the exception factor code ECCI is set in the exception factor register 25, the stack register 23 holds the instruction address FADR of the instruction that caused the exception first. The pipeline control unit 37 performs the control. The exception processing program reads the value of the exception factor register 25 and displays the read exception factor code ECCI on a display (not shown), or the exception factor register 25 holds the instruction address FADR held by the stack register 23. Controls the processing of accumulating the exception factor code ECCI in the external memory 10 or the like.

  Here, it is assumed that the some instructions are future non-support instructions. If the first value is set in the instruction support control information SIFI before the part of the instruction becomes a non-support instruction, the part of the instruction is normally executed. When considering support for the next model, if the second value is set in the instruction support control information SIFI, the use of some of the instructions that will be unsupported in the future during software execution is an exception. Can be detected by the occurrence of. It should be noted that the exception factor register 25 includes both the pipeline control systems 33A and 33B so as to cope with the case where both instructions supplied to the two systems of the pipeline control systems 33A and 33B are future unsupported instructions. The cause code from can be saved. In this case, the instruction address stored in the stack register 23 is the instruction address of the instruction that caused the exception first.

  As described above, even when a superscalar is applied to the microcomputer 1, it is possible to detect the use of a function that will not be supported in the future during software execution.

<< History saving and execution in exception handling program >>
FIG. 8 illustrates a procedure for extracting non-support target usage information including an exception handling program. First, the CPU 2 starts a startup routine when the microcomputer 1 is powered on (powered on) (S1). In this startup routine, the CPU 2 performs its own initial settings and initial settings of the peripheral modules 11 to 15 (S2), and sets the support control register 24 to non-support, for example (S3). Next, the CPU 2 executes an application program (S4). In this application program, when the CPU 2 fetches and decodes the unsupported instruction (S5), an exception handling request is generated by the hardware configuration described above (S6).

  When an exception handling request is generated, the CPU 2 refers to the vector table in which the branch destination corresponding to the exception is written based on the exception cause code notified together with the exception handling request (S7). If the exception factor is based on the decoding of the unsupported instruction, the process proceeds to the execution of the exception processing program corresponding to the reference in the vector table. If it is another factor, a transition is made to another exception process corresponding to the factor (S8).

  Exception processing for an unsupported instruction is broadly divided into a recording process (S9) regarding the occurrence of the factor and a confirming execution process (S13) for the unsupported instruction. In the processing of step S9, the CPU 2 displays the value of the program counter (not shown) stored in the stack register 23 on a display device such as an LED (S10), and further displays the exception factor code stored in the exception factor register 25. Is displayed on the LED (S11). Next, the CPU 2 stores the stack register 23 and the exception factor register 25 in the external memory 10 as a work area of the microcomputer 1 (S12). As described above, the CPU 2 shifts to the execution of a predetermined exception processing program and executes the process of step S9, thereby enabling control to save the exception factor code and the instruction address that caused the exception factor. Therefore, the microcomputer 1 can store a history of exception factors using the exception processing program.

  Further, after step S9, the CPU 2 executes an exception factor instruction (S13). In the process of step S13, the CPU 2 first sets the support control register 24 set to unsupported in the process of step S3 to support (S14). Next, the CPU 2 executes the exception factor instruction using, for example, the external memory 10 (S15), and updates the value (stack) held in the stack register 23 to the instruction next to the exception factor instruction (S16). Thereafter, the CPU 2 sets the support control register 24 to non-support (S17), terminates the exception handling program described above, returns to the application program, and performs normal processing such as the next instruction. As described above, after the CPU 2 saves the exception factor code and the instruction address that has caused the exception in the process of step S9, the CPU 2 executes the instruction that has caused the exception by executing the process of step S13. Thus, the execution of a predetermined exception handling program can be ended. Therefore, the microcomputer 1 not only detects that an exception factor instruction that is a specific instruction is to be executed, but also can guarantee that the exception factor instruction is completely executed.

  Here, the microcomputer 1 uses the method of referring to the vector table in the process of step S7. However, the microcomputer 1 is not limited to this, and after jumping to a certain address regardless of the cause of the exception, the microcomputer 1 A method of analyzing the exception processing factor code and jumping to the corresponding routine may be applied. Further, the stack register 23 may apply a method of storing the value of the program counter at the address indicated by the stack pointer. Furthermore, the microcomputer 1 can display the contents stored in the stack register 23 and the exception factor register 25 with an LED or the like, and can eliminate the processing in step S12 when the history is not saved.

  In addition, the microcomputer 1 transitions to the execution of the exception processing program before executing the unsupported instruction as a procedure for extracting the unsupported usage information. However, the microcomputer 1 is not limited to this and is not supported. After executing this instruction, the process may be shifted to the execution of the exception handling program. Further, the program execution may be stopped by exception processing. In this case, the CPU 2 may end the exception processing program immediately after performing the process of step S9.

《Additional function or change function that is newly `` supported '' in existing models》
In the above description, it is possible to detect use of a future unsupported function. If future unsupported functions are grasped as additional functions or changed functions from now on, it can be applied to detection of use of additional or changed functions supported from now on in data processors, etc., as described above. Become. An application example from this viewpoint will be described below. The functions considered here are the same as in the case of non-support, for example: (1) support for specific instructions, (2) access support for specific address areas, (3) support for specific function settings, (4) external terminals There are five types of support: support for setting functions set by using (5) support for using control functions using an external interface circuit. The microcomputer 1 has hardware for detecting the use of the function newly added or changed from an existing model during software execution. For these hardware, the definition of various support control information held in the support control register 24 may be changed as compared with the above hardware that realizes the extraction of usage information to be unsupported. The logical implementation is almost the same.

<< Support for specific instructions >>
In the case where some instructions are newly added or changed instructions this time and the execution of these instructions is supported, the instruction support control information held in the support control register 24 shown in FIG. SIFI may be defined as information indicating support for added or changed instructions. Thereby, the microcomputer 1 can detect the execution of the instruction in the same manner as when executing the future non-support instruction even when the partial instruction is an instruction that has been added or changed this time. it can. Even when the CPU 2A, which is a superscalar typically shown in FIG. 7, is applied to the microcomputer 1, the instruction support control information SIFI is defined as described above to execute the instruction added or changed this time. Can be detected in the same manner.

<< Access support for specific address areas >>
In the case where access is made for some addresses this time or the access form is changed and access to the address related to the addition or change is supported, the microcomputer 1 uses the address support control information SIFA shown in FIG. What is necessary is just to define with the information which shows the support of the area address which concerns on the said addition or change. Thereby, even when the partial address is an address related to the addition or change, the microcomputer 1 detects the access to the address in the same manner as when accessing the future non-support address described above. Can do.

<Support for specific function settings>
When some of the predetermined functions are added or changed this time, and this additional or changed function is supported, in the microcomputer 1, the function support control information SIFR shown in FIG. What is necessary is just to define as the information which shows the support of the place which added or changed the function which can be set newly. Thereby, even when the predetermined function is a function that has been added or changed this time, the microcomputer 1 detects the use of the predetermined function in the same manner as when using the future non-support function described above. be able to.

<Support for functions set using external terminals>
Some functions such as an operation mode set using a mode terminal or the like are functions added or changed this time. When the function is supported, the microcomputer 1 has an external terminal function shown in FIG. The support control information SIFE may be defined as information indicating support at a location where a function set using an external terminal is newly added or changed. Thereby, the microcomputer 1 can detect the setting of this operation mode similarly to the case of setting the future non-support function described above even when the operation mode is a function added or changed this time, for example. .

《Support for control function using external interface circuit》
Some functions, such as a specific command interface function using an external interface circuit, are functions that have been added or changed this time. When this function is supported, the microcomputer 1 uses the external device support control shown in FIG. The information SIFD may be defined as information indicating support of a place where a control function using an external interface circuit is newly added or changed. Thereby, even when the command interface function is a control function that has been added or changed this time, for example, the microcomputer 1 detects the use of this command interface function in the same manner as when using the above-mentioned future non-support function. be able to.

  That is, according to the microcomputer 1, the use or setting of the newly added or changed function can be detected during software execution. Therefore, the microcomputer 1 can easily verify whether there is an influence or failure due to the additional function or the change function, or can be used for specifying a debug location or a notice location when a trouble occurs.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

  For example, in the above description, some commands, specific address access, control register settings, external terminal control functions, non-support targets, or newly added support functions or functions whose support contents have been changed, Although the bus interface control function has been described, the present invention is not limited thereto and can be changed as appropriate. In non-supporting control of specific address access, the cache entries constituting the instruction cache (ICACH) 5 and data cache (DCACH) 6 of the cache memory 3 are mapped to the address space of the CPU 2 to purge or invalidate cache entries. It may be an associative access using a memory allocation access or an associative search result using a cache tag.

  In addition, exception processing is used to detect functions that will not be supported in the future, but a break interrupt may be generated in the emulator mode. In short, the functions that will not be supported in the future are set as break conditions. In addition, in order to detect functions that will not be supported in the future, special unsupported exceptions are not prepared, notifications are made using output terminals, illegal instruction exceptions and address exceptions are analyzed, and the cause is analyzed and understood from the stack. You may do it. The present invention can be widely applied not only to microcomputers but also to data processors called microprocessors, accelerators, system LSIs, and the like.

It is a block diagram of a microcomputer. FIG. 2 is a block diagram illustrating a configuration in which specific instructions are selectively unsupported in the microcomputer of FIG. 1. FIG. 2 is a block diagram illustrating a configuration in which access to a specific address area is not supported in the microcomputer of FIG. 1. FIG. 2 is a block diagram illustrating a configuration that does not support a specific function setting in the microcomputer of FIG. 1. FIG. 2 is a block diagram illustrating a configuration in which setting of a function set by using a specific external terminal in the microcomputer of FIG. 1 is selectively unsupported. FIG. 2 is a block diagram illustrating a configuration in which use of a control function using an external interface circuit is selectively unsupported in the microcomputer of FIG. 1. FIG. 2 is a block diagram illustrating a configuration in which specific instructions are selectively unsupported when the CPU is a superscalar in the microcomputer of FIG. 1. It is a flowchart which shows an example of the procedure which extracts the usage information of the non-support object containing the exception processing program run by a microcomputer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microcomputer 2 Central processing unit 3 Cache memory 6 Data cache memory 7 Bus state controller 21 Instruction execution part (IEXEC)
22 Instruction decoder (IDEC)
23 Stack register (STCREG)
24 Support control register (SCREG)
25 Exception factor register (ECFREG)
SIFI instruction support control information ECCI Exception cause code ECPI control signal 31 Exception request control unit (ECCNT)
SIFA address support control information 32 Address decoder (ADEC)
33A, 33B Pipeline control system 34 CPU resources (CPURESC)
35 Arithmetic Unit (ALU)
36 General-purpose register (GREG)
37 Pipeline Control Unit (PIPCNT)
AADR access address ASRB access strobe signal AERR address error signal ECCA Exception cause code 40 Function designation register (FREG)
FSIF function designation information SIFR function support control information 41 Decoder (DEC)
45 System control unit (SYSCNT)
46 Mode decoder (MDEC)
MD0 to MD3 Mode terminal RERR Register error signal 50 Interface controller (IFCNT)
60 External device (EXDVC)
70 Instruction sequence controller (ISQCNT)
71 Instruction issue control unit (IFCNT)
72 Instruction buffer (IBUF)

Claims (19)

A data processor that supports a plurality of functions by executing an instruction, having a control register and a decoder,
The control register is used for holding instruction information for selectively instructing to disable some of the functions supported by the data processor;
The decoder is a data processor that detects an operation to use a part of functions that are disabled by the control register and holds the detection result. A data processor having an instruction execution control unit and an exception control unit,
The exception control unit has a first control register, and the first control register selectively instructs a part of an instruction set executable by the data processor to be non-executable. Used to hold information about
The instruction execution control unit includes an instruction decoder, and the instruction decoder performs decoding that can be executed on the part of instructions when the first information is a first value, and the first information is A data processor that performs decoding capable of generating an exception factor code that can be distinguished from other exception factors when the second value is set, and causes instruction execution to transition to execution of a predetermined exception processing program.   3. The data processor according to claim 2, wherein the instruction execution control unit is a central processing unit, and the first control register is readable and writable by the central processing unit. The exception control unit has an exception factor register that holds an exception factor code;
4. The data processor according to claim 3, wherein the instruction execution control unit includes a stack register that holds an instruction address held by a program counter when an exception occurs. A data processor having an instruction execution control unit, an exception control unit, and a bus control unit,
The exception control unit has a first control register, and the first control register selectively instructs to disable access to a partial address in the address space of the data processor. Used to hold
The bus control unit includes an address decoder, and the address decoder permits an access request to the partial address when the second information is a first value, and the second information is a second value. An address error signal is generated in response to an access request to the partial address when
In response to the address error signal, the instruction execution control unit generates an exception factor code that can be distinguished from other exception factors, and transitions the instruction execution to the execution of a predetermined exception processing program.   6. The data processor according to claim 5, wherein the address space that can be instructed to be selectively inaccessible by the first control register is both an internal address space and an external address space of the data processor. The exception control unit has an exception factor register that holds an exception factor code;
The data processor according to claim 6, wherein the instruction execution control unit has a stack register that holds an instruction address held by a program counter when an exception occurs. A data processor having an instruction execution control unit, an exception control unit, and other functional blocks for selecting a function corresponding to the function designation information set in the function designation register by the instruction execution control unit;
The exception control unit includes a first control register, and the first control register selectively instructs to disable setting of some predetermined functions by the function designation information. Used to hold
The other functional block includes a decoder, and the decoder allows the predetermined function to be specified in the function specifying register when the third information is a first value, and the third information When the information is a second value, a register error signal is generated for the designation of the predetermined function to the function designation register;
In response to the register error signal, the instruction execution control unit generates an exception factor code that can be distinguished from other exception factors, and causes the instruction execution to transition to execution of a predetermined exception processing program. The exception control unit has an exception factor register that holds an exception factor code;
9. The data processor according to claim 8, wherein the instruction execution control unit has a stack register that holds an instruction address held by a program counter when an exception occurs. A data processor having an instruction execution control unit and an exception control unit,
The exception control unit has a support control register, and the support control register holds instruction information for selectively instructing that some instructions in the instruction set executable by the data processor are not executable. Used,
The instruction execution control unit includes a decoder, and when the decoder decodes a part of the instructions instructed to be impossible by the support control register, the decoder generates and holds a factor code specific to the factor. Data processor. A data processor having an instruction execution control unit, an exception control unit, and a bus control unit,
The exception control unit has a support control register, and the support control register is used for holding instruction information for selectively instructing to disable access to a part of the address space of the data processor;
The bus control unit includes a decoder, and the decoder can detect an access request for an inaccessible address designated by the support control register;
In response to detection of the access request, the instruction execution control unit generates and holds a factor code specific to the factor. A data processor having an instruction execution control unit, an exception control unit, and other functional blocks in which a function corresponding to control information set in a function control register is selected by the instruction execution control unit;
The exception control unit has a support control register, and the support control register is used for holding instruction information for selectively instructing that setting of some control information to the function control register is impossible,
The other functional block includes a decoder, and the decoder is capable of detecting a setting of a part of control information instructed to be not set by the support control register,
The instruction execution control unit generates and holds a factor code specific to the factor in response to detection of the setting of a part of the control information instructed that the setting is impossible.   The data processor according to claim 1, further comprising an external terminal used for setting a function according to a state, wherein the part of the function is a function set using the external terminal.   The data processor according to claim 1, further comprising an external interface circuit connectable to the outside, wherein the partial function is a control function using the external interface circuit.   3. The data processor according to claim 2, wherein the instruction execution control unit is capable of controlling the exception factor code and the instruction address that caused the exception cause by transitioning to execution of the predetermined exception handling program.   The instruction execution control section executes the predetermined exception processing program, saves the exception cause code and the instruction address that caused the exception, and then executes the exception cause instruction. The data processor according to claim 15, wherein the execution of the predetermined exception handling program can be terminated.   The data processor according to claim 1, wherein the some functions are functions that may be unsupported in the future.   The data processor according to claim 1, wherein the partial function is an additional function newly supported.   The data processor according to claim 1, wherein the partial function is a function whose support content is changed.

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