JPH11203174A - State supervisory information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely and also accurately perform cause analysis after an abnormal operation during program execution by supervisory control in a device and to improve its maintainability. SOLUTION: This processor has a CPU 10, a memory 12, an I/O circuit 13, a ring buffer output I/F part 14, a ring buffer 15, a counter 17, a CPU bus supervising part 16, a map information storing part 18, a resetting circuit 19 and a data/control bus line 20. The processor stores an address in access to the memory or the I/O, data and information of a bus cycle in addition to an instruction fetch cycle. Also, it supervises write to an unwritable area and also supervises write to a dedicated read-out area in a write cycle to the memory. Further, it supervises read-out from an area other than a code area in the instruction fetch cycle, also supervises the access of read and write from/to non-definition areas of the memory 12 or the circuit 13 and starts write to the buffer 15 only one time by the control from the CPU 10 after a power supply or a system reset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state monitoring information processing apparatus such as a microprocessor in which a central processing unit performs map information and CPU bus monitoring control to process information, and more particularly to a state monitoring information processing apparatus having a static memory map. The present invention relates to a state monitoring information processing apparatus that monitors abnormalities in the execution of a program.

[0002]

2. Description of the Related Art Conventionally, as a state monitoring information processing apparatus such as a microprocessor in which a central processing unit (CPU) performs map information and CPU bus monitoring control to process information, for example, JP-A-63-21545. Examples are known. In this conventional example, an execution address and data are extracted from a program counter of a CPU and stored in a ring buffer.

FIG. 7 is a block diagram showing a configuration of a conventional state monitoring information processing apparatus. In this example, when an address to be executed next is generated by the program counter 1a of the CPU 1, a signal for counting up the counter 2 is output. Thus, the address in the ring buffer 3 is determined, and the address and the data are stored in the ring buffer 3 at the instruction fetch timing from the memory 5.

In order to read the data stored in the ring buffer 3, the output of the counter 2 is invalidated and the address is specified from the CPU 1, or the address is specified by sequentially incrementing the counter 2 At the same time, the data is output to the CPU 1 through the data bus 6 and further transmitted to an external device through the input / output (I / O) circuit 7.

In such a state monitoring information processing apparatus, since only address information in an instruction fetch cycle is stored, data cannot be obtained when a bus master (not shown) performs direct memory access (DMA) transfer. Also, since writing to the code area is not monitored, the program may be rewritten due to careless writing to the code area, and the CPU 1 may become incapable of data processing (runaway). In addition, since monitoring of writing to the read-only area is not performed in the memory write cycle, writing to the read-only area is performed carelessly, and the abnormal operation of the CPU 1 cannot be determined.

Further, since reading and writing to the non-defined area of the memory 4 and the I / O circuit 7 are not monitored, runaway of the CPU 1 is not determined by careless writing to the non-defined area. Further, there is no means for stopping the storage of the monitoring information for these malfunctions, so that the monitoring information of the runaway of the CPU 1 is overwritten, and the cause cannot be found thereafter.

[0007]

As described above, in the above conventional example, data cannot be obtained when a bus master (not shown) performs DMA transfer, and a program is rewritten due to careless writing in the code area, causing the CPU to run away. There was something to do. In addition, careless writing to the read-only area makes it impossible to determine the abnormal operation of the CPU.
Also, careless writing to the non-defined area causes the CP
There is a disadvantage that U's runaway cannot be determined. Furthermore, CP
There is a drawback that the monitoring information of U's runaway is overwritten, and the cause cannot be searched for later.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems in the prior art. By monitoring and controlling the inside of the apparatus, the cause of the abnormal operation can be reliably and accurately analyzed after an abnormal operation during program execution. It is an object of the present invention to provide a state monitoring information processing apparatus in which the information is improved.

[0009]

In order to achieve the above object, a state monitoring information processing apparatus according to the present invention comprises an instruction fetch cycle and information on an address, data and a bus cycle in accessing a memory or an I / O circuit. Is monitored, a write to a non-writable area is monitored, a write to a read-only area is monitored in a write cycle to the memory, a read from an area other than the code area is monitored in an instruction fetch cycle, and memory, I / O A map information unit and a CPU bus monitoring control unit that monitor read and write access to the non-defined area of the CPU and control to start writing to the ring buffer under control of the CPU only once after power-on or system reset. It is provided as a configuration.

Further, the state monitoring information processing apparatus of the present invention
Setting information storing means for storing setting information of a code area for monitoring map information in a program process as a map information storing section; writing permission information storing means for storing writing permission information for a specified area; Data area setting information storage means for storing area setting information;
An I / O area setting information storage unit for storing O area setting information is provided. A CPU bus monitoring unit configured to perform CPU bus monitoring based on the setting information in the map information storage unit; an abnormality detection unit configured to detect an abnormality when the designated area is not the write permission information; An abnormality monitoring means for monitoring an abnormality in reading and an abnormality detecting means for detecting an abnormality in reading from outside the code area in an instruction fetch cycle are provided.

[0011] Further, the state monitoring information processing apparatus of the present invention comprises:
Storage means for storing address, data, and bus cycle status in a ring buffer in synchronization with the cause information of the abnormality detected by monitoring by the CPU bus monitoring unit and writing and reading of the bus line; and after power-on or system reset. Writing start means for starting writing to the ring buffer only once under the control of the CPU, write inhibiting means for inhibiting writing to the ring buffer when an abnormality is detected, and information sending means for sending ring buffer information to the outside. Is further provided.

Further, the state monitoring information processing apparatus of the present invention
A CPU, a memory, a ring buffer for storing address, data, state of bus cycle and cause information of detected abnormality, an input / output circuit, a ring buffer output interface unit, and a counter for specifying an address of the ring buffer; The configuration includes a CPU bus monitoring unit, a map information storage unit, and a reset circuit. Further, the configuration is such that the CPU processes bus cycle information indicating the bus cycle information, and the nonvolatile buffer or the FIFO memory is used as the ring buffer.

Further, the state monitoring information processing apparatus of the present invention
A monitoring start information storing information indicating a start of monitoring on the data / control bus line, a monitoring stop information storing information indicating a stop of monitoring on the data / control bus line, a data / control bus; Monitoring result information that stores information indicating the result of monitoring on the line, write monitoring information that stores monitoring information for writing on the data / control bus line, and code area reading monitoring that stores monitoring information for reading the code area. It is configured to perform processing of non-defined area access monitoring information that stores information and monitoring information of access to the non-defined area.

Further, the status monitoring information processing apparatus of the present invention
The map information storage unit includes address upper limit information and address lower limit information storing the address of the designated area, write permission information for storing information as to whether the designated area is writable, and setting information of the code area, and the designated area is written. Code information for storing information on whether or not possible, setting information of the data area,
Data information for storing information as to whether or not the designated area stores data, setting information of the I / O area, and the designated area is
The configuration is such that processing of I / O information for storing information as to whether or not the area is an O area is performed.

The state monitoring information processing apparatus of the present invention having the above-described configuration can store the memory / I / O in addition to the instruction fetch cycle.
Since the information of the address, data, and bus cycle in the access to the circuit is stored, data when the bus master performs the DMA transfer can be obtained. Further, since the writing to the non-writable area is monitored, the runaway of the CPU when the program is rewritten due to the careless writing to the code area can be prevented.

Further, the status monitoring information processing apparatus of the present invention
Since the writing to the read-only area is monitored in the write cycle to the memory, an abnormal operation of the CPU due to the careless writing to the read-only area can be determined. In addition, since reading from outside the code area is monitored in the instruction fetch cycle, abnormal operation of the CPU due to careless reading from outside the code area can be determined.

Further, the state monitoring information processing apparatus of the present invention
Since the reading and writing accesses to the non-defined area of the memory or the I / O circuit are monitored, the abnormal operation of the CPU due to the careless writing to the non-defined area of the memory or the I / O circuit can be determined. become. Furthermore, since writing to the ring buffer is started only once after power-on or system reset under the control of the CPU, the monitoring information is not overwritten during abnormal operation of the CPU, and the cause analysis can be easily performed thereafter. Become.

Further, the state monitoring information processing apparatus of the present invention
By replacing the ring buffer with a non-volatile memory, the stored information can be read by an external device, and the cause information of the detected abnormality can be used at a later date, thereby improving maintainability. Further, by using a FIFO memory instead of the ring buffer, a counter becomes unnecessary and the configuration of the ring buffer output interface can be simplified.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a state monitoring information processing apparatus according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a state monitoring information processing apparatus according to an embodiment of the present invention. This state monitoring information processing apparatus is provided with a CPU 10 for controlling the data processing here.
And a memory 12 for storing data, an input / output (I / O) circuit 13 for inputting and outputting information to and from an external device, and information of a ring buffer 15 storing factors (information) of detected abnormalities to the outside. And a ring buffer output interface (I / F) unit 14 for transmitting.

The state monitoring information processing apparatus includes a ring buffer 15 for storing an address, data, a state of a bus cycle and cause information of a detected abnormality, a counter 17 for specifying an address of the ring buffer 15,
A CPU bus monitoring unit 16 for monitoring the operation of the PU 10 on the data / control bus line 20, a map information storage unit 18 for storing map information in the program processing,
It has a reset circuit 19 for performing a reset process at the time of power-on or system reset, and a data / control data / control bus line 20 for connecting these components.

The CPU 10 has a data / control bus line 2
Bus cycle information 111 indicating bus cycle information at 0
Process.

FIG. 2 is a block diagram showing the processing contents of the CPU bus monitoring unit 16. In this example, monitoring start information 161 storing information indicating the start of monitoring on the data / control bus line 20, monitoring stop information 162 storing information indicating stopping of monitoring on the data / control bus line 20,
Processes monitoring result information 163 that stores information indicating the result of monitoring on the data / control bus line 20, further writes write monitoring information 164 that stores monitoring information for writing on the data / control bus line 20, and code It processes code area read monitoring information 165 that stores information on monitoring of area reading, and non-defined area access monitoring information 166 that stores monitoring information on access of non-defined areas.

FIG. 3 is a block diagram showing the processing contents of the map information storage unit 18. In this example, address upper limit information 181 and address lower limit information 182 storing the address of the designated area, write permission information 183 storing information as to whether the designated area is writable, and setting information of the code area, Respectively process the code information 184 that stores information as to whether or not it is writable. Further, the setting information of the data area includes data information 185 storing information as to whether or not the designated area stores data, and setting information of the I / O area, and whether or not the designated area is an I / O area. , Respectively.

Next, the operation of this embodiment will be described. In FIG. 1, the CPU bus monitoring unit 16
The count value of the counter 17 is updated in synchronization with writing and reading on the data / control bus line 20 with reference to the bus cycle information 111 at 0. The counter 17
The address to the ring buffer 15 is specified. The ring buffer 15 stores address, data, and bus cycle information 11.
1 and the monitoring result information 163 in the CPU bus monitoring unit 16 are stored. The reset circuit 19 of the CPU bus monitoring unit 16 performs resetting after power-on or system reset. Thereafter, writing to the ring buffer 15 is started only once under the control of the CPU 10, and writing to the ring buffer 15 is prohibited by detecting an abnormality.

In FIGS. 1 to 3, the CPU bus monitor 16 includes an address upper limit information 181, an address lower limit information 182, and a write permission information 1 of an area in the set map information.
83, address bus, data bus, bus cycle information 1
Referring to FIG. 11, if the designated area is not the write permission information and an error is detected when writing is performed. Also, the address upper limit information 1 in the map information set by these operations
81, the address lower limit information 182, the address bus, and the state of the bus cycle information 111 are referred to, and an abnormality is detected by writing to or reading from an undefined area.
Further, the CPU bus monitoring unit 16 stores the address upper limit information 181 and the address lower limit information 1 in the map information set as described above.
82, the state of the address bus and the bus cycle information 111 is referred to, and an abnormality is detected by reading from outside the codec area in the instruction fetch cycle.

Hereinafter, this operation will be described in detail. FIG.
9 is a flowchart showing a processing procedure of an initialization operation at the time of starting a program in the CPU 10. 1 and 4, the CPU 10 performs an initialization operation at the time of starting the program, as shown in FIG. 4, in the map information storage unit 18, the address upper limit information 181, the address lower limit information 182,
Code information 184 of the code area, write permission information 183 for the specified area, data information 185 of the data area, and I / O
The area I / O information 186 is set. Next, a start trigger is sent from the CPU 10 to the monitoring start information 161 (step S1).

In the instruction fetch cycle, the CPU bus monitoring unit 16 refers to the address upper limit information 181 and the address lower limit information 182 of the area in the map information storage unit 18 and the code information 184 of the address bus and the code area, and reads out the code area. Is checked, and the result is stored in the monitoring result information 163. In the memory write cycle, the CPU bus monitoring unit 16 stores the address upper limit information 181 and the address lower limit information 18 of the area in the map information storage unit 18.
2. Referring to the address bus and the write permission information 183,
It is checked whether the area is a writable area, and the result is stored in the monitoring result information 163 (step S1).

FIG. 5 is a diagram showing an example of the monitoring result information 163. In this example, the count value of the counter 17 is “1,
Addresses “1234,” respectively corresponding to “2, 3, 4”
8FFF, 1236, 9000 ”and data“ 1234,
55FF, 1234, 55FF ", bus cycle" instruction fetch, memory read, instruction fetch, memory read ", and monitoring result" none, none, none, undefined area read "are stored.

FIG. 6 is a flowchart showing a processing procedure for writing in an area where writing is not permitted. In FIG. 1 to FIG. 6, when it is necessary to write in an area where writing is not permitted, the writing permission information 183 of the area is set to off once. That is, arbitrary data is written after changing to the permission state. Then, finally, the write permission information 183 of the area is turned on again to return to the unusable state. In addition,
It is determined that the writing to the non-defined area is also abnormal (steps S10, S11, S12).

In the memory read cycle, the CPU bus monitoring unit 16 can read the defined area by referring to the address upper limit information 181, the address lower limit information 182, and the address bus of the area in the map information storage unit 18. It is checked whether the area is an appropriate area, and the result is stored as monitoring result information 163 shown in FIG. In the I / O write cycle, the CPU bus monitoring unit 16 sets the address upper limit information 181 and the address lower limit information 1 of the area in the map information storage unit 18.
82, it is checked whether or not the area is a writable area with reference to the address bus and the write permission information 183. This check result is stored as monitoring result information 163 shown in FIG.

Here, when it is necessary to write in an area where writing is not permitted, the writing permission information 183 of the corresponding area is turned off once as shown in FIG. That is, arbitrary data is written after changing to the permission state. Then, finally, the write permission information 183 of the corresponding area is set to ON again to return to the disabled state. Note that writing to a non-defined area is also regarded as abnormal. In the I / O read cycle, the CPU bus monitoring unit 16 can read the defined area by referring to the address upper limit information 181, the address lower limit information 182, and the address bus of the area in the map information storage unit 18. Check whether it is an area. This check result is stored as monitoring result information 163 shown in FIG.

The ring buffer 15 is connected to a counter 17 and takes in the count value generated by the counter 17 as an address. The count value is sequentially increased or reduced (gradually reduced) at the timing generated by the CPU bus monitoring unit 16, and is reset to an initial value when the count value becomes a constant value. The timing generated by the CPU bus monitoring unit 16 is determined by writing data to the memory 12 via the data / control bus line 20 or setting the I / O circuit 1
This is a time immediately after the reading through No. 3 is performed.

The ring buffer 15 is connected to the CPU 10 via a data / control bus line 20. The bus cycle information 111 and the monitoring result information 163 in the CPU bus monitor 16 are processed and the respective states are stored. . When an abnormality is detected in any of the processing of the write monitoring information 164 of the CPU bus monitoring unit 16, the code area read monitoring information 165, or the undefined area access monitoring information 166, the writing to the ring buffer 15 is performed by the processing of the monitoring stop information 162. To stop.

The ring buffer output I / F unit 14 serves as a bus master and changes the count value of the counter 17 through the CPU bus monitoring unit 16 to change the ring buffer 15.
And sends out all the data stored therein, in particular, the cause information of the detected abnormality to an external device (not shown).

In this embodiment, the ring buffer output I / F unit 14 sends out the abnormality information stored in the ring buffer 15 to the external device by parallel data or serial data. By replacing it with a memory, the stored information can be read by an external device. In this case, in particular,
Information on the cause of the detected anomaly will be available at a later date,
Its maintainability is improved.

In this embodiment, the ring buffer 15 which stores the cause information of the abnormality by the operation of the CPU bus monitoring unit 16 and the counter 17 and reads it out by the ring buffer output I / F unit 14 is used. May be. In this case, the counter 17 becomes unnecessary, and the configuration of the ring buffer output I / F unit 14 can be simplified. Further, although the map processing for the I / O circuit is performed in this embodiment, the map processing for the memory 12 can be applied as it is.

[0037]

As is apparent from the above description, according to the state monitoring information processing apparatus of the present invention, the information of the address, data and bus cycle in accessing the memory / I / O circuit besides the instruction fetch cycle is stored. Since the data is stored and monitored for writing to a non-writable area, data can be obtained when the bus master performs a DMA transfer. CPU runaway can be prevented.

Further, according to the state monitoring information processing apparatus of the present invention, the writing to the read-only area is monitored in the writing cycle to the memory, and the reading from the area other than the code area is monitored in the instruction fetch cycle. For this reason, the CP caused by careless writing to the read-only area
The abnormal operation of the U can be determined, and the abnormal operation of the CPU due to careless reading from outside the code area can be determined.

According to the status monitoring information processing apparatus of the present invention, the read and write accesses to the undefined area of the memory or the I / O circuit are monitored, and the CPU is provided only once after the power is turned on or after the system is reset. Since writing to the ring buffer has been started under the control of
An abnormal operation of the CPU due to careless writing to a non-defined area of the memory or the I / O circuit can be determined, and
The monitoring information is not overwritten at the time of the abnormal operation, and the cause analysis can be easily performed thereafter.

Further, according to the status monitoring information processing apparatus of the present invention, by replacing the ring buffer with a non-volatile memory, the stored information can be read by an external device, and the detected cause information of the abnormality can be obtained at a later date. It can be used, and maintainability is improved. Further, by using a FIFO memory instead of the ring buffer, a counter becomes unnecessary and the configuration of the ring buffer output interface can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a state monitoring information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing processing contents of a CPU bus monitoring unit shown in FIG. 1;

FIG. 3 is a block diagram showing processing contents of a map information storage unit shown in FIG. 1;

FIG. 4 is a flowchart showing a processing procedure in an initialization operation at the time of startup in the embodiment.

FIG. 5 is a diagram illustrating an example of a monitoring result in the embodiment.

FIG. 6 is a flowchart showing a processing procedure for writing to a write-protected area in the embodiment.

FIG. 7 is a block diagram illustrating a configuration of a conventional state monitoring information processing apparatus.

[Explanation of symbols]

 Reference Signs List 10 CPU 12 Memory 13 Input / output (I / O) circuit 14 Ring buffer output I / F unit 15 Ring buffer 16 CPU bus monitoring unit 17 Counter 18 Map information storage unit 19 Reset circuit 20 Data / control bus line

Claims (9)

[Claims] 1. A central processing unit comprising: map information;
In a state monitoring information processing apparatus that processes information by performing U bus monitoring control, information on an address, data, and a bus cycle in accessing a memory or an I / O circuit is stored together with an instruction fetch cycle. Monitor writing to the area, monitor writing to the read-only area in a write cycle to the memory, monitor reading from outside the code area in the instruction fetch cycle,
A map information unit and a CPU bus monitoring control unit that monitor read and write access to the undefined area of O, and control to start writing to the ring buffer under control of the CPU only once after power-on or system reset. A condition monitoring information processing apparatus comprising: 2. A setting information storing means for storing setting information of a code area for monitoring map information in a program process as the map information storing section, and a write permission for storing write permission information for a specified area. An information storage means, a data area setting information storage means for storing data area setting information, and an I / O area setting information storage means for storing I / O area setting information. 2. The state monitoring information processing apparatus according to 1. 3. An abnormality detecting means for monitoring the CPU bus based on the setting information in the map information storage unit and detecting an abnormality when the designated area is not the write permission information. 2. The state monitor according to claim 1, further comprising: abnormality monitoring means for monitoring an abnormality in writing or reading to the definition area; and abnormality detection means for detecting an abnormality in reading from outside the code area in an instruction fetch cycle. Information processing device. 4. A storage means for storing address, data, and bus cycle states in a ring buffer in synchronization with information on a cause of an abnormality detected by monitoring by the CPU bus monitoring unit and writing and reading of a bus line. Writing start means for starting writing to the ring buffer under the control of the CPU only once after power-on or system reset; write inhibiting means for inhibiting writing to the ring buffer when an abnormality is detected; information on the ring buffer 2. The state monitoring information processing apparatus according to claim 1, further comprising: an information sending unit that sends the information to the outside. 5. A CPU for executing control of data processing, a memory for storing data, a ring buffer for storing address, data, a state of a bus cycle and cause information of a detected abnormality, and an external device. An input / output circuit for performing input / output processing of the information of the above, a ring buffer output interface unit for sending out the cause information of the abnormality stored in the ring buffer to the outside, a counter for specifying an address of the ring buffer, and the CPU A CPU bus monitoring unit that performs bus monitoring in the operation of (1), a map information storage unit that stores map information in executing a program in the CPU, and a reset circuit that processes a reset at power-on or system reset. A condition monitoring information processing apparatus characterized by the following. 6. The state monitoring information processing apparatus according to claim 5, wherein said CPU processes bus cycle information indicating bus cycle information. 7. A monitoring start information storing information indicating a start of monitoring on a data / control bus line and a monitoring stop information storing information indicating a stop of monitoring on a data / control bus line. , Monitoring result information for storing information indicating the result of monitoring on the data / control bus line, write monitoring information for storing writing monitoring information for the data / control bus line, and reading monitoring information for the code area. 6. The status monitoring information processing apparatus according to claim 5, wherein the status monitoring information processing apparatus performs processing of non-defined area access monitoring information for storing code area read monitoring information and non-defined area access monitoring information. 8. A map information storage unit comprising: address upper limit information and address lower limit information storing an address of a designated area; write permission information for storing information as to whether the designated area is writable; and code area setting information. The code information for storing information on whether or not the designated area is writable, and the data area setting information are data information for storing information on whether or not the designated area stores data, and I / O area setting information. 6. The state monitoring information processing apparatus according to claim 5, wherein processing of I / O information for storing information as to whether or not the designated area is an I / O area is performed. 9. The state monitoring information processing apparatus according to claim 1, wherein a nonvolatile memory or a FIFO memory is used as the ring buffer.