JPH04338842A - Information processor with error detecting function - Google Patents

Abstract

PURPOSE:To obtain an information processor containing an error detecting function which can analyze the factor of a system down in an accurate and extremely simple way. CONSTITUTION:A CPU 1 is connected to a memory 2 via the buses 3-5. The CPU 1 outputs the address information and a control. signal to the memory 2 and carries out the reading/writing operations of the memory 2. Then the system down processing is carried out with occurrence of an error. In such a constitution of an information processor containing an error detecting function, the signal states are traced on the buses 3-5 and the data on the processing contents of the CPU 1 are stored in an operation monitoring circuit 10. Thus it is possible to prevent the data stored in the circuit 10 from being reset in a starting state set after the error is detected.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus with an error detection function that detects errors occurring in software or hardware and stops the operation of a CPU.

0002

[Prior Art] Generally used information processing devices are
As shown in FIG. 3, a CPU 1 and a memory 2 are connected via a control bus 3, an address bus 4, and a data bus 5. For example, the CPU 1 outputs various control signals such as write/read signals together with address information to the control bus 3 and address bus 4, and outputs various control signals such as write/read signals to the memory 2.
It calls and executes instructions from a predetermined area of the computer, or writes data to a predetermined area.

[0003] In such an information processing apparatus, various error detections are performed using software. For example, the read instructions may be incorrect due to hardware failure or software abnormality (Invalid).
Opcode), attempting to access an inaccessible area (General Protection)
If an error such as that occurs, the error is detected and the system is brought down.

[0004] However, in the above-mentioned software processing, if the system goes down due to error detection, it is difficult to find out what process the CPU 1 was specifically executing and what process it was trying to execute that caused an error. Because there is not enough information left to know what happened, analyzing errors required a great deal of time and effort.

[0005]

SUMMARY OF THE INVENTION As described above, the conventional information processing apparatus with an error detection function has a problem in that it is extremely difficult to analyze errors because almost no information remains when an error occurs.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to memorize the operating state of the CPU at the time of a system down, save error information, and to analyze the cause of a system down extremely easily and accurately. An object of the present invention is to provide an information processing device with an error detection function that can be used to detect errors.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention connects a CPU and a memory via a bus, and outputs a control signal together with address information from the CPU to the memory, In an information processing device with an error detection function that reads/writes data to/from the memory and executes system down processing when an error occurs, the signal states on the bus are sequentially captured based on the control signal. an operation monitoring means for storing data regarding processing contents of the CPU; and means for preventing the data stored in the operation monitoring means from being reset when restarting after an error is detected. did.

[0008]

According to the present invention, in which the above measures are taken, the signals on the bus indicating the operation of the CPU are sequentially stored in the operation monitoring means based on the control signal indicating the operation timing of the CPU. When an error occurs and the system goes down, the operating state of the CPU at the time of the system down is stored in the operation monitoring means. At startup, the memory is generally reset, but since the operation monitoring means is prevented from being reset, the stored data is saved. Therefore, at the time of restart, the operation monitoring means stores the operating state of the CPU at the time of the system down, and by reading this data, it is possible to analyze the cause of the system down.

[0009]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a schematic functional block diagram of an information processing apparatus having an error detection function according to an embodiment. In this embodiment, a control bus 3, an address bus 4, and a data bus 5 that connect the CPU 1 and the memory 2 are further connected to an operation monitoring circuit 1 that monitors the operation of the CPU 1.
The configuration is connected to 0. FIG. 2 shows the configuration of the operation monitoring circuit 10.

The operation monitoring circuit 10 has a control bus 3
is the latch timing control section 11 and the memory control section 12
The address bus 4 and the data bus 5 are connected to a data latch unit 13, and the data latch unit 13 is further connected to an error trace memory 14.

The latch timing control section 11 outputs a latch timing signal to the data latch section 13 based on a group of control signals from the CPU 1. The data latch unit 13 has a function of latching signals on the address bus 4 and data bus 5 according to a latch timing signal, and outputting data read from the error trace memory 14 onto the system buses 4 and 5. The memory control unit 12 has a function of controlling writing/reading of the error trace memory 14.

In this embodiment configured as above, C
The control signal group, address information, and data output from the PU 1 to the memory 2 are also input to the operation monitoring circuit 10 at the same time. The latch timing control unit 11 of the operation monitoring circuit 10 monitors a group of control signals, detects the start or end of access by the CPU 1, and latches the signals on the address bus 4 and data bus 5 based on the timing. A timing signal is output to the data latch unit 13. The data latch section 13 latches the signals on the address bus 4 and data bus 5 according to the latch timing signal and temporarily stores them internally.

On the other hand, by outputting a write command from the memory control section 12 to the error trace memory 14, the address bus 4 stored in the data latch section 13 is
and the signal on the data bus 5 is the error trace memory 1
Written to 4.

Note that the capacity of the error trace memory 14 is actually limited by the system configuration, so that it is not possible to trace and store all data from startup. For this reason, in this embodiment, the memory area is divided into a plurality of areas and used, and the memory controller 12 writes newly imported data over the oldest data so that the memory is used cyclically. Control.

When the CPU 1 detects an error using software, the CPU 1 uses software to stop the operation of the operation monitoring circuit 10 and restart the CPU 1 while storing the previous operation state in the error trace memory 14. Performs shutdown processing that sometimes becomes inoperable.

Next, when the system is started up again, the operation monitoring circuit 10 does not operate, so the contents of the error trace memory 14 are not reset, and the operating state of the CPU 1 before the occurrence of the error is preserved. Therefore, the CPU 1 releases the shutdown state of the operation monitoring circuit 10, puts the error trace memory 14 in a read-enabled state, and outputs trace data onto the system buses 4 and 5 in order, for example, starting from the latest trace data. This allows the operator to know the operating state of the CPU 1 retroactively for a certain period of time from the time the error occurred.

As described above, according to this embodiment, the control bus 3, address bus 4, and data bus 5 are monitored and the CP
The operating state of U1 is sequentially stored in the error trace memory 14, and when the system goes down, the operation monitoring circuit 10 is shut down, and when the system is restarted, the operating state of the CPU 1 is stored in the error trace memory 14 for a certain period of time from when the error occurred. Since the information is saved retroactively in the past, it is possible to analyze the cause of a system failure extremely easily and accurately.

[0019]

Effects of the Invention As detailed above, according to the present invention, the operating state of the CPU at the time of system down can be memorized and error information can be saved, and the cause of system down can be analyzed extremely easily and accurately. An information processing device with a detection function can be provided.

[Brief explanation of the drawing]

FIG. 1 is a schematic functional block diagram of an information processing device with an error detection function according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of an operation monitoring circuit of an information processing device with an error detection function according to an embodiment.

FIG. 3 is a schematic functional block diagram of a conventional information processing device with an error detection function.

[Explanation of symbols]

1...CPU, 2...Memory, 3...Control bus, 4...
address bus, 5...data bus, 10...operation monitoring circuit,
11...Latch timing control section, 12...Memory control section,
13...Data latch unit, 14...Error trace memory.

Claims (1)

[Claims] 1. A CPU and a memory are connected via a bus, and the CPU outputs a control signal together with address information to the memory to read/write data to the memory, and also to prevent errors. In an information processing device with an error detection function that executes system down processing when a system down process occurs, an operation monitoring unit that sequentially captures signal states on the bus based on the control signal and stores the data as data related to the processing content of the CPU; An information processing device with an error detection function, comprising: means for preventing data stored in the operation monitoring means from being reset when restarting after error detection.