JPH10228395A - Abnormality diagnostic device for controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller abnormality diagnostic device capable of surely analyzing the cause of hard or soft abnormality generated once several months. SOLUTION: The controller utilizing a microcomputer is provided with respective trace memories 10 to 12 for always storing program execution states such as an operation mode, addresses and data for fixed steps from an execution step back to a step corresponding to memory capacity and with a trace control circuit 14 for controlling the writing of the program execution states in the memories 10 to 12 and the reading of the execution state from the memories 10 to 12, and when program abnormality is detected by the self-detection function of the microcomputer, the circuit 14 stores the current contents of respective trace memories 10 to 12 based on its abnormality detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality diagnosis apparatus for a control controller using a microcomputer.

[0002]

2. Description of the Related Art On a production line of a factory, a controller using a microcomputer is widely used. However, this controller is abnormal due to runaway due to electromagnetic noise at the site or a bug in control programming. Operation may occur.

[0003] If the phenomenon is reproducible, the cause of the abnormal operation can often be specified. However, the phenomenon is not reproducible and can occur once every few hours to several months.
If the phenomenon occurs frequently, it is difficult not only to identify the cause, but also to determine whether the cause is due to hardware or software. Therefore, in the case of an abnormal operation in which the phenomenon is not reproducible, it is a fact that effective measures cannot be taken.

Therefore, a device that monitors the execution state of a program and can analyze the state when an abnormality occurs later can be analyzed. As an apparatus for monitoring the program execution state of such a microcomputer, for example, Japanese Patent Laid-Open No.
There is a microcomputer system described in Japanese Patent Application Laid-Open No. 217526 (hereinafter referred to as prior art 1).

[0005] The system of the prior art 1 uses an in-circuit emulator, which is used to transfer a part of the functions of the CPU and the memory of the control controller to the inside of the in-circuit emulator through a cable or the like during program development. It takes in and analyzes.

Further, as a program abnormality diagnosis apparatus for embedded equipment, there is one described in Japanese Patent Application Laid-Open No. 4-294432 (this is referred to as prior art 2). Prior to starting the execution of each of the modularized programs according to a predetermined procedure, the device of the prior art 2 sequentially stores the start addresses of the modules in a predetermined memory area, and stores the start addresses of the modules in a memory area by a remote control signal or key input of a predetermined code. Are sequentially read from the address following the last stored address.

[0007]

However, the system of the prior art 1 incorporates a part of the functions of the CPU and the memory into the inside of the in-circuit emulator through a cable or the like. There was a problem that it could not be used in a field where the temperature environment was poor.

The device of the prior art 2 can trace only the execution history of a program in module units.
There has been a problem that it is not possible to analyze specific abnormal contents, and it is also not possible to investigate abnormalities when hardware runs away due to noise or the like.

The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a hardware or software abnormality which occurs about once every several months while control is being performed on site. An object of the present invention is to provide an abnormality diagnosis device for a control controller capable of reliably analyzing the cause.

[0010]

According to a first aspect of the present invention, there is provided an abnormality diagnosis apparatus for a control controller, comprising: Trace memory that always keeps the execution state of data etc. for a certain number of steps from the execution step to the point of the memory capacity, and controls the writing of the program execution state to this trace memory and the reading of the execution state from the trace memory A trace control circuit that, when a program abnormality is detected by the self-detection function of the microcomputer, retains the contents of the trace memory at that time based on the abnormality detection signal. Read from the microcomputer It is to transfer the contents of the trace memory to the outside based on the request signal.

According to a second aspect of the present invention, there is provided an abnormality diagnosis apparatus for a controller according to the first aspect, wherein a buffer is interposed between the microcomputer and the trace memory.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an electrical configuration of a normal real-time control controller equipped with the abnormality diagnosis device of the present invention.

This real-time control controller comprises:
CPU 1, interrupt controller 2, memory 3 such as ROM or RAM, timer 4, I / O interface 5,
A control bus 6 for exchanging signals between them;
A control mode trace memory 10 for writing signals on the control bus 6, an address trace memory 11 for writing signals on the address bus 7, and data for writing signals on the data bus 8, comprising an address bus 7 and a data bus 8. A trace memory 12, a ring counter 13 for controlling the addresses of the trace memories 10, 11, 12, and a buffer control for controlling the buffer 9, the control mode trace memory 10, the address trace memory 11, the data trace memory 12, and the ring counter 13; The circuit 14 is provided.

The real-time control controller normally executes a necessary processing program based on a periodic timer interrupt or an interrupt signal from various I / O devices (not shown) connected to the I / O interface 5. At this time, a signal indicating an operation state (read / write, interrupt, etc.) is output from the CPU 1 to the control bus 6, and
The corresponding addresses and data of the memory 3 and the I / O interface 5 are output to the address bus 7 and the data bus 8, respectively. The signals on these buses 6, 7, 8 are written into the trace memories 10, 11, 12 in accordance with the instruction of the trace control circuit 14.

The CPU 1 has a 16-bit CP.
In the case of U, there are about 10 signal lines on the control bus 6, about 20 signal lines on the address bus 7, and about 16 signal lines on the data bus 8, so that these signals are stored in each of the trace memories 10, 11, and 12. The data width must be large enough to record all.

FIG. 2 is a flowchart showing the operation of the trace control circuit 14 at the time of tracing. That is,
When the reset state is released after the power is turned on, the trace control circuit 14 first sets the direction of the buffer 9 to each of the buses 6 and 6.
Signals 7 and 8 are set in a direction to be read into each of the trace memories 10, 11 and 12 so that the control operation by the trace control circuit 14 does not affect the CPU 1, the interrupt controller 2 and the like. At the same time, each trace memory 1
Ring counter 1 for controlling addresses 0, 11, and 12
The value of 3 is reset to "0" (step S1).

In this state, when the operation of the CPU 1 starts, the trace control circuit 14 monitors the control bus 6 to indicate the state of instruction code fetch, reading, writing, interruption, etc. of the memory 3 and the I / O interface 5. It is checked whether the signals on the buses 6, 7, 8 are valid (step S2). Each time it is confirmed that the signals on the buses 6, 7, 8 are valid, the signals (data) on the respective buses 6, 7, 8 are transferred via the buffer 9 to the respective trace memories 10, 11 , 12 (step S3).

When the writing to the trace memories 10, 11, and 12 is completed, the trace control circuit 14 updates the address by incrementing the value of the ring counter 13 by 1 (step S4).

The trace control circuit 14 repeats the processing of steps S2 to S4. As a result, the value of the ring counter 13 is
If the capacity exceeds the upper limit of the capacity of 11 or 12 (for example, 1024 steps for 1 Kbyte), the operation proceeds from step S5 to step S6, and the ring counter 13
Is reset to "0", and the process returns to step S2 to repeat the operation.

By such a processing operation, the history of instructions and data from the execution step of the program to the time point up to the memory capacity is always stored in each of the trace memories 10, 11, and 12.

Incidentally, in the case of a general real-time control controller, the bus 6, bus 6
When the signals on 7 and 8 become abnormal, the CPU 1 detects an invalid instruction not in its own instruction set by the self-detection function,
For example, a halt signal or an external bus reset signal is issued. Also, when an incorrect instruction (for example, division by zero) is executed due to a bug in the program, the self-detection function operates similarly. If the program goes out of control, an interrupt is sent to the CPU 1 from the watchdog circuit, etc.
It can be forcibly returned to the initial state.

Therefore, when these abnormalities are detected,
An abnormality detection signal output from the CPU 1 is supplied to the trace control circuit 14 as a trigger signal to control the operation of each of the trace memories 10, 11, and 12 when an abnormality occurs.

FIG. 3 is a flowchart showing the operation of the trace control circuit 14 when an error occurs. That is,
When the trace control circuit 14 recognizes the abnormality detection signal,
First, the trace memories 10, 11, and 12 are write-protected to protect the memory contents (step S11), and at the same time, the ring counter 13 is stopped (step S12).

On the other hand, the CPU 1 executes a process for returning to the normal state when an abnormality occurs, and starts the reading process of the contents of the trace memories 10, 11, and 12 after the normal recovery. When this processing is started, the trace control circuit 14
Sets the orientation of the buffer 9 so that the CPU 1 can read the contents of each of the trace memories 10, 11, and 12 (steps S13 and S14).
2 is transferred to the memory 3 (steps S15 and S1).
6). The transferred data is output to, for example, a screen of a control controller or a printer. Alternatively, the data is re-transferred from the control controller to a higher-level host computer (not shown) by communication.

This makes it possible to analyze the execution history from the point of occurrence of the abnormality up to a point several K steps back, making it easier to identify the cause of the abnormality. If a real-time operating system is installed, these analysis processes can be performed while the control operation is continued.

[0026]

According to a first aspect of the present invention, there is provided an abnormality diagnosis apparatus for a control controller, comprising: a control controller using a microcomputer; A trace memory that always holds a fixed step up to a point in time traced back by a capacity; and a trace control circuit that controls writing of a program execution state to the trace memory and reading of an execution state from the trace memory. When a program abnormality is detected by the microcomputer's self-detection function, the contents of the trace memory at that time are held based on the abnormality detection signal, and the trace memory is stored based on a read request signal from the microcomputer. Out of the contents It is configured to transfer to. That is, by storing the state immediately before the occurrence of the abnormality in the trace memory and analyzing the contents thereof, the state at the moment when the abnormality occurs can be recorded even if the abnormality has a low occurrence frequency, such as occurs once every few months at the site. In addition, by analyzing the contents of the control bus, address bus, and data bus, it is possible to determine whether the cause of the abnormality is caused by hardware or by software. You can also estimate if it is a bug.

According to a second aspect of the present invention, there is provided an abnormality diagnosis apparatus for a control controller, wherein a buffer is interposed between a microcomputer and a trace memory. The trace control by the trace control circuit 14 can be performed without affecting the operation of the computer at all.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a normal real-time control controller equipped with an abnormality diagnosis device of the present invention.

FIG. 2 is an operation flowchart at the time of tracing by a trace control circuit.

FIG. 3 is an operation flowchart of the trace control circuit when an abnormality occurs.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Interrupt controller 3 Memory 4 Timer 5 I / O interface 6 Control bus 7 Address bus 8 Data bus 9 Buffer 10 Control mode trace memory 11 Address trace memory 12 Data trace memory 13 Ring counter 14 Trace control circuit

Claims (2)

[Claims] 1. A control controller using a microcomputer, comprising: a trace memory for constantly retaining an operation state of a program, such as an operation mode, an address, and data, for a certain number of steps from an execution step to a time point up to a memory capacity; A trace control circuit that controls writing of a program execution state to the trace memory and reading of an execution state from the trace memory, wherein the trace control circuit detects a program abnormality by a self-detection function of the microcomputer. The content of the trace memory at that time is held based on the abnormality detection signal, and the content of the trace memory is transferred to the outside based on a read request signal from the microcomputer. Controller Abnormal diagnostic device. 2. The abnormality diagnosis device for a control controller according to claim 1, wherein a buffer is interposed between said microcomputer and said trace memory.