JP2000330878A - Communication controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To gather data of an input/output common control part and to analyze hardware by reading out or dumping held information when the input/output common control part is stopped owing to an input/output-relative software error. SOLUTION: If a monitor timer 31 overflows when an input/output instruction is executed, a monitor timer overflow display circuit 32 is set and a monitor timer overflow information is displayed in an interruption cause display register 33. With mask data, an interruption generating circuit 35 generates a signal BR and the input/output instruction informs software that the monitor timer overflows. The output of the interruption signal BR activates a read control line 28, a read instruction signal CL is inputted to the input/output common control part to stop the operation, and the contents of a readable register and a control memory are read out and sent to a host device. Consequently, when the system stops, the information held in the input/output common control part is read out or dumped to analyze the hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device mounted on a communication device or the like, and more particularly to a communication control device with improved error processing.

[0002]

2. Description of the Related Art In general, a communication control device of this type has a line controller for controlling line connection and a device controller for controlling various devices connected to a common bus. CP that performs data communication control by procedure
U, etc .; an input / output control unit for performing data transfer control and input / output control between the common bus and the main control unit; And a monitoring timer for counting the time. Then, when the monitoring timer times out, predetermined error processing is performed. Conventionally, in error processing of such a communication control device, when a software monitoring timer times out (soft time over), the system goes down only by tracing information on software, and hardware information cannot be collected. Was common.

On the other hand, when an error occurs in a computer system, the contents of hardware registers at that time (information on hardware) are stored in a main storage device, and then dumped to an external storage device.
A technique for easily analyzing the cause of an error is disclosed in
No. 3046 is disclosed.

FIG. 3 is a block diagram showing a main configuration of the computer system disclosed in the above publication. The system monitoring processing module 122 of the operating system 121 first sets a system error monitoring time, and thereafter continuously issues a clock reset request to the external timer 200 at regular time intervals. The timeout detection processing module 202 of the external timer 200
When a reset request is received from the system monitoring processing module 122, the clock is reset and counting is restarted. If a request for a reset instruction from the system monitoring processing module 122 is not issued after the system error monitoring time, the external timer 200 detects a timeout and regards the computer 100 as being in an error state. Then, the register save processing module 20
2 is the hardware register 1 at the time of timeout detection
01 (for example, an instruction register, a cache directory, an interrupt register, etc.) is stored in a predetermined register save area 123 on the main storage device 120. Thereafter, the external timer 200 starts the operation of the arithmetic processing unit 11.
A restart interrupt is issued for 0.

[0005] As described above, according to the prior art disclosed in the above publication, information on hardware is collected, and the cause of the error is easily analyzed. Therefore, it is conceivable to apply the technique of the above publication in order to improve the error processing of the communication control device described above.

[0006]

However, when the prior art disclosed in the above publication is applied to error processing of a communication control device, there are the following problems. For example, an abnormal operation of a line control unit or a device control unit connected to the common bus causes an increase in processing time or inconsistency in processing, and a software monitoring timer times out (soft time / time) without causing a hardware error. Over). In such a case, it is impossible to analyze the hardware only by the contents of the hardware register in the prior art disclosed in the above publication. For this reason, it is difficult to distinguish between software and hardware failures, and it takes time to recover from errors.

The present invention has been made in view of the above-mentioned conventional problems, and enables analysis of hardware even if the system is stopped due to soft time over of input / output, and software / software.
An object of the present invention is to provide a communication control device that can easily identify a hardware failure.

[0008]

According to a first aspect of the present invention, there is provided a communication control apparatus connected to a common bus and controlling a connection of a line. A device control unit that controls various devices, a main control unit that performs data communication control according to a predetermined communication control procedure, and a data transfer control and an input / output control between the common bus and the main control unit. An input / output control unit to perform;
Fires when an I / O instruction is executed by software,
An input / output monitoring timer that counts a predetermined time,
When the input / output monitoring timer times out, in the communication control device that performs predetermined error processing when the monitoring timer times out, at least the input / output related software related to the line control unit and the device control unit is used. Identification means for identifying whether or not an error is indicated; stopping means for stopping the operation of the input / output common control unit when the input / output-related software error is detected; and Means for reading or dumping the information held in the input / output common control unit when the common control unit is stopped. The communication control device according to the second aspect of the present invention is further characterized by further comprising means for displaying that the input / output command has been monitored.
Further, the communication control apparatus according to the third aspect of the present invention is characterized in that a means for setting when the monitoring timer has timed out and displaying the fact is further provided.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a communication control device according to one embodiment of the present invention.
In the figure, reference numeral 21 denotes a CPU for controlling data communication according to a predetermined communication control procedure, and reference numeral 22 denotes a memory for storing a control program including the predetermined communication control procedure and various data. Reference numeral 23 denotes a service processor.
Reference numeral 4 denotes an input / output common control unit. These CPU 21, memory 22, service processor 23, input / output common control unit 2
4 are interconnected via a CPU / memory bus 20. Further, the line control unit 25 and the device control unit 2
6 and 27 through the common bus 29.
4 is connected. Here, the line control unit 25 is a circuit that is activated by an input / output command in the memory 22 and controls connection of the line, and the device control units 26 and 27 are circuits that control various devices. The input / output common control unit 24 performs bus control of the common bus 29 to which the device control units 26 and 27 are connected and the CPU / memory bus 20, and controls the CPU 21 or the memory 22 and the line control unit 2.
5 is a circuit for performing data transfer between the device control units 26 and 27 and input / output control. The input / output common control unit 24 is connected to the CPU 2 via a read instruction control line 28.
1, a reading instruction signal CL (described later) is applied, which forms a part of the feature of the present invention.

FIG. 2 is a block diagram showing a configuration of a processing circuit including a reading instruction signal CL generating unit and an interrupt signal BR generating unit which characterize the present invention.
It is built into the CPU 21. In the figure, reference numeral 31 denotes a monitoring timer. The monitoring timer 31 has a function of setting a timer value according to a monitored factor and counting up or down for a certain period of time. Reference numeral 32 denotes a monitor timer overflow display circuit, which is set when the monitor timer 31 overflows. 33 is an interrupt cause display register,
The overflow interrupt factor of the monitoring timer 31 is displayed. 3
Reference numeral 4 denotes a mask register, which is a register capable of controlling the enable / disable of the interrupt by setting mask data indicating the enable / disable of the interrupt. An interrupt generating circuit 35 generates an interrupt signal BR. In contrast to the interrupt generation unit, a read instruction signal generation unit which is a feature of the present invention includes a soft time over monitoring processing display circuit 36 and a read instruction generation circuit 37. Then, the respective output signals of the soft time over monitoring processing display circuit 36, the monitoring timer overflow display circuit 32, and the interrupt generation circuit 35 are supplied to the read instruction generation circuit 37, and the reading output from the read instruction generation circuit 37 is performed. The input / output common control unit 24 is stopped by the instruction signal CL. At this time, information readable by the input / output common control unit 24 is read out, or the contents of the input / output common control unit 24 are dumped.

Next, the operation of this embodiment will be described. Line control unit 25 or device control units 26 and 27
For example, various monitoring functions are loaded on the memory 22 as software programs. The input / output common control unit 24 uses the CPU 2
1 to monitor the operating time from the reception of the start request until the end of use of the common bus 29 is reported, the monitoring of the use of the common bus 29, and the line after the input / output common control unit 24 receives the start request. The control unit 25 monitors the operation time of the device until the end of the device control units 26 and 27 is reported. There is time monitoring of the event when the time until the 24 receives the activation is held in response to the input / output request event.

When an input / output instruction is executed by software, a monitoring timer 31 is started. If the monitoring timer 31
Overflows, the monitoring timer overflow display circuit 32 is set, and the interrupt cause display register 33 is set.
Indicates that it is a monitoring timer overflow interrupt. Then, the interrupt signal B is generated by the interrupt generation circuit 35 according to the mask data stored in the mask register 34 in advance.
R is generated to notify software that the input / output instruction has overflowed the monitoring timer.

Since the interrupt cause display register 33 displays other interrupt factors such as hardware errors and software errors in addition to the input / output monitoring time overflow, the soft timer over monitoring processing display circuit 36
Indicates that monitoring of input / output instructions has been performed. At the same time that the interrupt signal BR is output from the interrupt generation circuit 35, the read control line 28 is activated in the read instruction generation circuit 37 by the output of the monitoring timer overflow display circuit 32, and the read instruction signal CL is controlled by the input / output common control. Output to the unit 24.

As a result, the operation of the input / output common control unit 24 stops, and at this time, the contents of the readable register and control memory of the input / output common control unit 24 are read and sent to the host device.

As described above, in this embodiment, even if the system is stopped due to the soft time over of the input / output, the information stored in the input / output common control unit 24 is read (or dumped) to analyze the hardware. It is possible to easily perform software / hardware failure isolation.

[0016]

As described in detail above, according to the present invention,
Even if a software error occurs, data can be collected by the input / output common control unit, so that hardware analysis can be performed. This makes it easy to isolate software and hardware failures, and shortens error recovery time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a communication control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reading instruction signal generating unit which is a feature of the present invention.

FIG. 3 is a diagram for explaining conventional error processing.

[Explanation of symbols]

 Reference Signs List 20 CPU / memory bus 21 CPU 22 memory 23 service processor 24 input / output common control unit 25 line control unit 26, 27 device control unit 28 read instruction control line 29 common bus 31 monitoring timer 32 monitoring timer overflow display circuit 33 interrupt cause display Register 34 Mask register 35 Interrupt generation circuit 36 Soft time over monitoring processing display circuit 37 Read instruction generation circuit CL Read instruction signal

Claims (3)

[Claims] 1. A line controller connected to a common bus and controlling a line, a device controller connected to the common bus and controlling various devices, and a main controller for controlling data communication in a predetermined communication control procedure Unit, an input / output control unit that performs data transfer control and input / output control between the common bus and the main control unit, and is activated when an input / output instruction is executed by software, and counts a predetermined time. An input / output monitoring timer, wherein the communication control device performs predetermined error processing when the monitoring timer has timed out. When the input / output monitoring timer has timed out, at least the line control unit and the device Identification means for identifying whether or not the input / output-related software error relating to the control unit is indicated; and the input / output-related software A stop unit for stopping the operation of the input / output common control unit when the input / output common control unit is stopped. Means for reading or dumping. 2. The communication control device according to claim 1, further comprising means for displaying that the input / output command has been monitored. 3. The communication control device according to claim 1, further comprising means for setting when the monitoring timer has timed out and displaying the fact.