JPH1115661A - Self-diagnosis method for cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To immediately and precisely detect abnormality in CPU when abnor mality occurs. SOLUTION: The method has a plurality of computing elements 14a and 14b having the same operation functions, and it diagnosis the operation of CPU which sequentially executes a plurality of operation instructions constituted of at least a reading stage, an execution stage and a writing stage in a pipeline system in synchronism with a system clock. The same operation processing is executed on the respective computing elements, operated results obtained in the respective computing elements are compared by self-diagnosis instructions at every prescribed number of operation instructions in an operation instruction string constituted of the plurality of operation instructions. Only when the compared results are not matched, abnormality warning is outputted by using the write stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis method for a CPU in which a self-diagnosis is performed by a CPU incorporated in a computer.

[0002]

2. Description of the Related Art Generally, in a computer, FIG.
As shown in FIG.
Auxiliary storage devices such as M3, RAM 4, display device 5, and HDD 6 are connected.

In order to ensure the reliability of such a computer, a self-diagnosis function for detecting an abnormality of the computer itself may be incorporated in the computer. Computer abnormalities are roughly divided into ROM3, RAM4,
There are abnormalities in the display device 5, the HDD 6, etc., and abnormalities in the CPU itself. The abnormality in the ROM 3, the RAM 4, the display device 5, the HDD 6, and the like can be determined by writing a self-diagnosis program in a main storage device such as the ROM 3 or the RAM 4 and executing the self-diagnosis program in the CPU 2, thereby causing a failure in each element. Diagnosis of abnormalities can be made.

However, if the CPU 2 itself becomes abnormal, a self-diagnosis program cannot be executed.
It is not possible to diagnose whether or not all the elements including U2 are abnormal. In order to solve such inconvenience, a self-diagnosis device 7 shown in FIG. 6 is incorporated in the computer.

In this self-diagnosis device 7, a watchdog timer is incorporated, and a predetermined grace time T
If a signal (data) is not output from the CPU 2 even after a elapses, it is determined that some abnormality has occurred in the CPU 2 and an abnormality warning is output.

[0006]

However, as shown in FIG. 6, a computer incorporating a self-diagnosis device 7 using a watchdog timer still has the following problems to be solved.

That is, the grace period Ta of the watchdog timer is fixed at a constant value. If this delay time Ta is shortened, if an abnormality occurs in the CPU 2, the abnormality can be found in a short time. However, if the delay time Ta is excessively short, there is a problem that the CPU 2 is determined to be abnormal even when the CPU 2 is not abnormal. Conversely, if the delay time Ta is excessively long, a problem arises in that the abnormal state of the CPU 2 is not detected for a long time.

The CPU 2 continuously outputs a signal (data)
However, if an erroneous signal (data) is output continuously, no abnormality of the CPU 2 can be detected. Therefore, there is a concern that a serious trouble may occur in the information processing apparatus in which the computer is incorporated.

The present invention has been made in view of such circumstances, and by providing a self-diagnosis function inside a CPU, it is possible to periodically and more reliably perform self-diagnosis in a short cycle, and to perform an abnormality only when an abnormality occurs. An object of the present invention is to provide a CPU self-diagnosis method capable of greatly improving the reliability of the entire computer while outputting an alarm and minimizing the influence on normal processing.

[0010]

SUMMARY OF THE INVENTION The present invention has a plurality of operation units having the same operation function, and synchronizes a plurality of operation instructions composed of at least a read stage, an execution stage, and a write stage with a system clock. Then, the present invention is applied to a CPU that sequentially executes in a pipeline manner.

In order to solve the above-mentioned problem, in the self-diagnosis method of the CPU according to the present invention, the self-diagnosis of the following a, b, and c is performed for each predetermined number of operation instructions in an operation instruction sequence including a plurality of operation instructions. Instructions for execution.

A. Causing each arithmetic unit to execute the same arithmetic processing; b. Comparing the operation results obtained by each operation unit; c. Only when the comparison result does not match, an abnormal alarm is output using the writing stage.

The principle of operation of the self-diagnosis method for a CPU having the above-described structure will be described. In a CPU that sequentially executes a plurality of operation instructions in a pipeline manner, a plurality of operation units having the same operation function are generally incorporated. Then, a plurality of calculations are performed simultaneously. When the same arithmetic processing is performed on the arithmetic units having the same function, naturally, the same arithmetic result should be obtained.

Therefore, by writing the arithmetic instructions for executing the above-mentioned a and b at a predetermined interval in the arithmetic instruction sequence for executing the ordinary business processing, the same arithmetic and the result of the arithmetic operation described above are obtained. Comparison can be easily performed. In this case, as shown in c, an abnormal alarm is output using the writing stage only when the comparison results do not match.

That is, when no abnormality is detected, nothing is written in the writing stage of the reading stage, the execution stage, and the writing stage constituting the operation instruction. Does not leave any self-diagnosis results,
The processing load on the CPU is minimized.

Another invention provides at least a register,
A data path, a computing unit, and a data read / write unit are incorporated, and the present invention is applied to a CPU that diagnoses an operation of a CPU that computes input data using a computing unit.

According to the CPU self-diagnosis method of the present invention, a scan path for returning data to a plurality of functional blocks relating to data transfer and temporary storage such as a register, a data path, and a data read / write unit. Is formed, the test data is returned to the scan path, the test data returned to the scan path is compared with the test data before the return, and an abnormal alarm is output only when the comparison result is inconsistent.

In the self-diagnosis method of the CPU configured as described above, when each data passes through each functional block relating to data transfer and temporary storage such as a register, a data path, and a data read / write unit in the CPU, If these functional blocks are normal, the name data itself does not change.

Therefore, a scan path that loops through each functional block is formed, test data is returned to the scan path, and the test data before return and the test data after return are compared. It can be determined that an abnormality has occurred in any of the functional blocks that constitute the scan path. Therefore, self-diagnosis can be performed by the CPU itself.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a schematic diagram showing a schematic configuration of a CPU to which a self-diagnosis method according to a first embodiment of the present invention is applied.

The data d ₁ , d ₂ , d ₃ , and d ₄ output from the register file 11 are stored in the registers 12a, 12
b, 12c, and 12d. Each data d _{1 to} d ₄ stored and held in each of the registers 12a to 12d
Are output according to the operation command, and the gates 13a, 13
b, 13c, 13d, an arithmetic unit (ALU) 14a,
14b. These computing units 14a and 14b have the same computing function. For example, in this embodiment, each of the arithmetic units 14a and 14b is connected to each of the registers 12a to 12a.
The sum of the outputs of 12d is calculated. Each computing unit 14a, 14
The respective data d ₅ and d ₆ of the operation result output from b are written into the original register file 11 and the comparator 16
Is input to The comparator 16 outputs the data d ₅ and d ₆ of the operation results of the operation units 14 a and 14 b in accordance with the self-diagnosis instruction.
Compare the outputs only abnormality detection alarm e ₁ not matched.

The CPU having such a hardware configuration is as follows.
A plurality of operation instructions are sequentially executed in synchronization with a system clock by a pipeline method. FIG. 2 is a schematic diagram showing the relationship between each operation instruction sequentially executed by the pipeline method, the execution timing of the operation instruction, and the count value PC of the program counter. The horizontal axis indicates the elapsed time t corresponding to the system clock, and the vertical axis indicates the count value PC of the program counter.

As shown in the figure, each operation instruction in this embodiment stores data to be operated on in a register file 11.
Alternatively, a reading stage (stage) D for reading from each of the registers 12a to 12d and two execution stages (stages) E ₁ and E for actually executing the corresponding operation in each of the arithmetic units 14a and 14b.
₂ and a writing stage (stage) W for writing the operation result into the register file 11, for example, in a total of four stages. Then, each stage is executed in synchronization with the rise of the system clock in the period T ₀ in the CPU. Therefore, one operation instruction is executed in four cycles (4T ₀ ).

The program composed of a plurality of operation instructions configured as described above is stored and held in a program or memory of a main storage device other than the CPU, such as a ROM or a RAM. Each operation instruction 1 stored at the address designated by the count value PC of the program counter driven at a cycle (2T ₀ ) twice the cycle T ₀ of the system clock
7 are sequentially read and temporarily stored in a queue in the CPU, and then the four stages of each operation instruction 17 are executed in synchronization with the above-described system clock.

[0025] If multiple arithmetic units 14a having the same function as in CPU embodiment, 14b are incorporated, two operation instruction in synchronization with each rising edge of the system clock period T ₀ simultaneously executed Be started.

[0026] Thus, in FIG. 2, the count value PC = n of the program counter, (n + 1) of two operation instructions are started at the same time, processing is terminated by the appropriate two operation instructions later 4T ₀ hours after the start of I do.

As described above, the operation (normal) instructions 17 included in the program for executing the ordinary business processing in this computer are sequentially executed while shifting the start time by one period T ₀ every two. Go. Then, the operation result of each operation (normal) instruction 17 is sequentially written to the register file 11.

In this embodiment, an unusual operation sequence (program) consisting of a plurality of operation normal) instructions 17
, A self-diagnosis instruction 18 is inserted for each predetermined number of operation instructions.

The self-diagnosis instruction 18 is composed of one or more lines. Then, a. b. This is an instruction for executing the process (operation) of c. a. The same arithmetic processing is performed on each of the arithmetic units 14a and 14b.

B. The operation results d ₅ and d ₆ obtained by the operation units 14a and 14b are compared. c. Only when the comparison results d ₅ and d ₆ do not match, the writing stage W
To output an abnormal alarm.

As shown in the figure, the instruction of each line formed of one or more lines for executing the processes (operations) a to c reads the same test data to be operated from a register file or each register as shown in the figure. A reading stage (stage) D;
It is composed of only two execution stages (stages) E ₁ and E ₂ for executing the corresponding operation in each of the arithmetic units 14a and 14b.
Another instruction is the operation result d ₅ , d obtained by each operation unit.
_{It comprises only a} reading stage (stage) D for reading ₆ and two execution stages (stages) E ₁ and E ₂ for comparing the read operation results d ₅ and d ₆ . Further, another instruction is to output an abnormality alarm to the register file 11 only when the comparison result does not match the reading stage (stage) D for reading the comparison result.
A writing stage (stage) W for writing data to Therefore, if the comparison results match, the writing stage (stage) W is not executed.

Therefore, the self-diagnosis instruction 18 automatically executes the processing of a, b, and c described above, and automatically determines whether each of the arithmetic units 14a and 14b is normal or abnormal. The self-diagnosis result is stored and output to the outside. On the other hand, if normal, the self-diagnosis result, which is the comparison result, is not stored or output.

As described above, the self-diagnostic instruction 1
By inserting 8, the self-diagnosis for the arithmetic units 14a and 14b incorporated in the CPU at a fixed period is automatically performed. In addition, by changing the interval at which the self-diagnosis command 18 is inserted, the execution cycle of the self-diagnosis can be arbitrarily adjusted.

Therefore, even if the execution cycle of the self-diagnosis is set short, the normal state is not determined to be abnormal as in the self-diagnosis apparatus 7 employing the conventional watchdog timer.

As a result, by setting the execution cycle of the self-diagnosis to be short, the occurrence of an abnormality in the CPU can be accurately detected in a short time, and the reliability of the computer in which the CPU is incorporated can be greatly improved.

When the diagnostic result is normal,
No self-diagnosis result remains, and the processing load on the CPU is minimized. Further, since there is no technical meaning for the operator to confirm the normal self-diagnosis result, the trouble of confirming the normal self-diagnosis result is relieved.

In the first embodiment described above,
It has been described that the self-diagnosis command 18 is written in the main storage device other than the CPU while being inserted between the operation (normal) commands 17 of the normal business program.

However, the self-diagnosis instruction 18 is stored and held in another dedicated register in the CPU, and each operation (normal) instruction 17 of the ordinary business program is sequentially read out by the program counter and written into a queue in the CPU. At the time
It is also possible to insert the self-diagnosis command 18 for every predetermined number of calculation (normal) commands.

In this case, as shown in FIG. 2, the self-diagnosis instruction 18 does not affect the count value PC of the program counter. (Second Embodiment) FIG. 3 is a schematic diagram showing a schematic configuration of a CPU to which a self-diagnosis method according to a second embodiment of the present invention is applied.

In the CPU, the register file 11, the registers 12a to 12d, and the arithmetic units 14a and 14 shown in FIG.
4b, hardware components such as registers 15a and 15b are housed.

However, from the viewpoint of data flow, this CPU can be regarded as being composed of a plurality of functional blocks such as a register, a data path, an arithmetic unit, a data read / write unit, and a cache memory. .

The self-diagnosis method of the CPU according to the second embodiment has a characteristic that data does not change even when the data passes through a corresponding function block such as data transfer and temporary storage among the plurality of function blocks. A self-diagnosis is made as to whether each functional block operates normally.

That is, as shown in FIG. 3, the data in the register file 21 does not change even through the corresponding function blocks such as data transfer and temporary storage.
A data path 22 controlled by the data path control unit 22a;
The read / write unit 23, the cache memory 24, and the self-diagnosis control unit 25 form a scan path 26 in software. Therefore, an arithmetic unit whose data value basically changes by passing through is not included in the scan path 26.

In the self-diagnosis control unit 25, an execution unit 27 for actually executing a self-diagnosis instruction, an expected value memory 28,
It comprises a processing result memory 29 and a comparing unit 30. The external memory 31 stores a self-diagnosis command and test data used for the self-diagnosis.

The expected value memory 28 stores the test data d _S read from the external memory 31 and returned to the scan path 26 as an expected value until the end of the test. Processing result memory 29 temporarily stores the test data d _Q that round the scan path 26. Comparing unit 30 compares the test data d _Q test data d _S and the processing result memory 29 of the expected value memory 28, if both do not match only, and outputs an abnormality detection alarm e _2.

This CPU incorporates, for example, one arithmetic unit. Like the CPU shown in FIG. 1, a plurality of arithmetic (normal) instructions 17 constituting a business program are transmitted in a pipeline manner at a period T ₀ . It is executed sequentially in synchronization with the rise of the system clock.

Then, when a self-diagnosis interrupt signal is input from the outside, the self-diagnosis control unit 24 executes the interrupt processing shown in FIG. That is, when an interrupt signal is input, the operation (normal) instruction 1 whose execution stage (stage) is currently being executed is
7, the corresponding operation (normal) instruction 17 is written to the last register file in the writing stage (stage) W
(S1).

Next, for the operation (normal) instruction 17 in which the reading (stage) stage D is being executed or completed and the execution stage (stage) has not yet started, the corresponding operation (normal) instruction 17 The address value (count value PC of the program counter) is read out (S2), and the address value (count value PC of the program counter) is stored and held (S3). Thereafter, the operation instruction (normal instruction) 17 whose execution stage (stage) has not yet started is cleared (S4).

When the above preparation processing is completed, the self-diagnosis command is read from the external memory 31 and executed by the execution unit 27. First, the test data d _S is read from the external memory 31 and written into the expected value memory 28 as an expected value (S
5). Then, sends the test data d _S from the execution unit 27 to the scan path 26 (S6), to execute the self-diagnosis command (S7). That is, an operation command is sent to each of the function blocks 21, 22, 23.24 of the scan path 26, and the test data d _S sent to the scan path 26 is returned.

[0050] Then, the final read test data d _Q read from the cache memory 24 (S8), writes the processing result memory 29 (S9). Next, the processing result memory 2
Comparing the previous test data d _S passing through the scan path 26 as the expected value stored in the test data d _Q and the expected value memory 28 via a scan path 26 which is stored in the 9 (S10).

If they match (S11), it is determined that the function blocks of the register file 21, data path 22, read / write unit 23, and cache memory 24 forming the scan path 26 are normal. In this case, no processing is performed.

If there is a mismatch (S11), one or more of the function blocks of the register file 21, data path 22, read / write unit 23, and cache memory 24 forming the scan path 26 are abnormal. it can be determined that there is, outputs an abnormality detection alarm e ₂ (S
12).

When this interrupt processing shown in FIG. 5 is completed, each operation (normal) instruction 17 of the normal business program is stored at the address position (program count value PC).
To resume from.

The CP of the second embodiment configured as described above
In the self-diagnosis method U, as shown in FIG. 4, when an operation (normal) instruction 17 in a normal business program is executed in a pipeline manner, an external self-diagnosis interrupt signal is input. , Operation (normal) instruction 1
7 is temporarily stopped, and the self-diagnosis instruction 18a is executed. Only when an abnormality is detected, an abnormality detection alarm e ₂
Is output, and nothing is output during normal operation.

The interrupt signal for executing the self-diagnosis is automatically generated at fixed time intervals using, for example, a timer. In the CPU self-diagnosis method configured as described above, each functional block for data transfer and data temporary storage constituting the CPU is automatically self-diagnosed at a constant cycle. Therefore, substantially the same effects as those of the self-diagnosis method of the first embodiment shown in FIG. 1 can be obtained.

Further, in a redundant computer system in which a plurality of CPUs to which the above-described self-diagnosis method is applied is incorporated to improve reliability, a CP on a side designated as a standby system is provided.
U can be configured to perform the self-diagnosis described above. In this case, the active CPU does not perform the self-diagnosis. Therefore, the reliability of the entire redundant computer system can be further improved without lowering the efficiency of the educational processing at the festival.

[0057]

As described above, in the CPU self-diagnosis method of the present invention, a self-diagnosis function which is automatically executed at a constant period is provided inside the CPU. Therefore, a more reliable self-diagnosis can be periodically performed in a short cycle, and an abnormality alarm is output only when an abnormality occurs, so that the reliability of the entire computer can be significantly improved while the influence on normal processing is minimized.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a CPU employing a self-diagnosis method according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram showing pipeline processing of each operation instruction in the CPU according to the first embodiment;

FIG. 3 is a schematic diagram illustrating a schematic configuration of a CPU employing a self-diagnosis method according to a second embodiment of the present invention;

FIG. 4 is a schematic diagram showing pipeline processing of each operation instruction in the CPU according to the second embodiment;

FIG. 5 is a flowchart showing the operation of the self-diagnosis method according to the second embodiment.

FIG. 6 is a schematic configuration diagram of a computer in which a conventional self-diagnosis device is incorporated.

[Explanation of symbols]

 11, 21 ... register file 12a to 12d, 15a, 15b ... register 14a, 14b ... arithmetic unit 16 ... comparator 17 ... operation (normal) instruction 18, 18a ... self-diagnosis instruction 22 ... data path 23 ... read / write unit 24 ... Cache memory 25 ... Self-diagnosis control unit 26 ... Scan path 27 ... Execution unit 28 ... Expected value memory 29 ... Processing result memory 30 ... Comparison unit 31 ... External memory

Claims (2)

[Claims] 1. A plurality of operation units having the same operation function, and sequentially execute a plurality of operation instructions composed of at least a read stage, an execution stage, and a write stage in a pipeline system in synchronization with a system clock. A self-diagnosis method of a CPU for diagnosing the operation of a CPU that performs a self-diagnosis instruction of the following a, b, and c for each predetermined number of operation instructions in an operation instruction sequence including the plurality of operation instructions. Self-diagnosis method. a. Causing each of the arithmetic units to execute the same arithmetic processing; b. Comparing the operation results obtained by each operation unit; c. Only when the comparison result is inconsistent, an abnormal alarm is output using the writing step. 2. A self-diagnosis method for a CPU in which at least a register, a data path, a computing unit, and a data read / write unit are incorporated and which diagnoses an operation of the CPU which performs an operation on inputted data by using the computing unit. Forming a scan path for returning data to a plurality of functional blocks relating to data transfer and temporary storage of the register, data path, data read / write unit, etc., and returning test data to the scan path; A self-diagnosis method for a CPU that compares test data returned through the scan path with test data before the return, and outputs an abnormal alarm only when the comparison result does not match.