JPH0769846B2 - Error processing circuit verification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a verification device of an error processing circuit for inspecting the function of an error processing circuit of a central processing unit, a plurality of types of retry methods are selected at a point where a retry start of a test program is possible. Timing detection that sequentially checks the processing status of the test program being executed by the central processing unit and notifies the error processing verification means of the retry method that can be executed at that processing timing for the purpose of enabling retry execution Means and a retry method to be executed from the executable retry methods notified from the timing detecting means, the forced error generating means is activated, and the supply of the processing clock of the central processing unit is stopped to execute the central processing. The central processing unit was stopped by the forced error generating means and the central processing unit started The clock supply to the central processing unit is restarted after being set to, the processing using the error data is performed, and further, the data of the processing result obtained from the central processing unit by this processing is obtained in advance. Error processing verification means for verifying the error processing circuit by comparison with expected data, and error data according to the retry method selected by the error processing verification means are supplied to the central processing unit to set the retry start state. An error processing circuit verification device is configured by the forced error generating means.

[Industrial application field]

The present invention relates to an error processing circuit verification device for inspecting the function of an error processing circuit of a central processing unit.

[Conventional technology]

In the computer system, an error processing circuit is provided for correcting an error or stopping the process when an error occurs in the process in the central processing unit in order to ensure the reliability of the operation.

Conventionally, in order to verify the function of such an error processing circuit, the central processing unit intentionally generates an error to operate the error processing circuit, and the result obtained from the central processing unit is expected by a service processor or the like. Is being compared with.

As a method for generating an error in the central processing unit for such a purpose, the clock of the central processing unit is stopped at random timing while running the test program, and the retry condition is set after the error condition is set by the service processor. Or a retry is performed under the condition that an error is generated by the service processor by designating the address of the storage device storing the control microprogram of the central processing unit.

The types of retries described above include machine retries, checkpoint retries, and micro retries, and the concept of these retries is shown in FIG.

This machine retry is a retry related to normal instruction processing shown as a machine instruction in FIG. 5, and data such as an operand in a register or memory depending on the execution result of this machine instruction from the time when the processing of the machine instruction is started. Will be done until just before is updated,
During this period, even if a retry is performed, the contents of the register that temporarily stores the data being processed inside the CPU are destroyed, so that the retry can be started from the refetch of this machine instruction.

In addition, for example, when a long-length data operation such as a double-precision operation is performed, the long-length operand stored in the memory is divided into, for example, 8 bytes,
It is executed by repeating a microroutine that repeats three operations of "fetch 8-byte data from memory-operation-store 8-byte data in memory". Such a microroutine is shown in FIG. Indicated.

When an error occurs in the middle of a micro routine that processes these divided operands, it is possible to retry by returning to the data fetch immediately before this error occurrence point. This retry is called the checkpoint retry described above. It is a thing.

Furthermore, when a microinstruction such as an interrupt process is processed by the microprogram, when the microprogram is executed to continuously store temporary data or continuously update one internal register, a large amount of data is frequently stored. May be updated to.

Therefore, as shown as a microinstruction in FIG. 5, when a microinstruction is retried, storing of the processing result by the microinstruction in which the error occurred is suppressed, and this microprogram is re-executed. This re-execution is called the above-mentioned micro-retry.

[Problems to be Solved by the Invention]

However, if the clock is stopped regardless of the operation of the central processing unit described above, an error may occur at a timing when the retry cannot be performed by the planned retry method.

On the other hand, if the error handling circuit is set to perform a machine retry for an error, when an error occurs once and the machine retry is executed, this error will occur at the same point at the same point, such as a microprogram defect. If it is a fixed one, it will end up in an infinite loop of machine retry → error occurrence → machine retry → error occurrence → ……, so normally machine retry is prohibited during machine retry. .

Therefore, for example, if the error processing circuit is set to perform machine retry by specifying the storage address of the micro program that allows retries other than machine retry, when an error occurs again due to the machine retry for the error occurrence, Since the error processing circuit is prohibited from performing the machine retry again, there are cases in which the microretry and the checkpoint retry which can be executed by the microprogram storage address are performed.

Even if the central processing unit performs normal processing by such micro-retry or checkpoint retry, the result obtained by this processing is different from the result of machine retry held as an expected value by the error processing circuit. Therefore, the error processing circuit determines that the central processing unit is abnormal.

That is, even though both the central processing unit and the error processing circuit are operating normally, they are detected as an error. Therefore, as described above, a microprogram capable of multiple retries is used as a retry start point. When the storage address is specified, it is necessary to limit the one storage address, which is the retry start point, so that the retry can be performed by only one kind of retry method.

The present invention enables a retry to be automatically executed at a point where a retry can be started in a test program, and a retry starting point to which a plurality of kinds of retry methods can be applied is selected to execute the retry. It is an object of the present invention to obtain a verification device for an error processing circuit that is designed to be obtained.

[Means for Solving the Problem] As shown in the principle diagram of FIG. 1, an error processing circuit verification device for verifying an error processing circuit (15) provided in a central processing unit (1) is provided. Timing detection means (2) for sequentially checking the processing state of the test program being executed by the central processing unit (1) and notifying the error processing verification means (3) of a retry method that can be executed at the processing timing; The retry method to be executed is selected from the executable retry methods notified from the detection means (2), the forced error generation means (4) is activated, and the supply of the processing clock of the central processing unit (1) is stopped. Then, the central processing unit is stopped, and after the central processing unit (1) is set to the retry start state by the forced error generating means (4), the central processing unit (1) is set. The above-mentioned error processing is performed by restarting the supply of the clock for the error processing and performing the processing using the error data, and further comparing the data of the processing result obtained from the central processing unit by this processing with the expected data obtained in advance. The error processing verification means (3) for verifying the circuit (15) and the error data according to the retry method selected by the error processing verification means (3) are supplied to the central processing unit to set the retry start state. And a compulsory error generating means (4).

[Operation] As described above, there are machine retries, checkpoint retries, micro retries, etc. as the types of retries, and the retryable period varies depending on the type of retries.

That is, in the machine retry, from the time when the processing of the machine instruction is started to the time immediately before the data such as the operand in the register or memory is updated by the execution result of this machine instruction, in the checkpoint retry, the operant In the middle of processing, and in micro-retry, the micro-instruction execution period is the period during which retries are possible.

Then, in machine retry, it returns to the point where the processing of the machine instruction in which the error occurred is started, and in checkpoint retry, it returns to the point where the data obtained by dividing the operand immediately before the time when the error occurred was fetched and the retry is performed. I. In the micro retry, the retry is performed from the start address of the micro program in the storage device in which the micro program in which the error has occurred is stored.

As described above, there are cases where a plurality of types of retry methods as described above can be performed from one retry start point.

Therefore, according to the present invention, as shown in the principle diagram of FIG. 1, the processing state of the test program being executed by the central processing unit (1) is sequentially inspected by the timing detection means (2), and the processing can be executed at this processing timing. The retry method is notified to the error processing verification means (3).

The error processing verification means (3), which has received the notification of the executable retry method from the timing detection means (2), selects the retry method to be executed from the retry methods and sets the forced error generation means (4). At the same time, the central processing unit (1) is stopped and the supply of the processing clock to the central processing unit (1) is stopped to stop the central processing unit.

Forced error generation means (4) activated according to the retry method selected by the error processing verification means (3)
Supplies the error data corresponding to the retry method to the central processing unit (1) and sets the central processing unit to the retry start state.

Then, the error processing verification means (3) restarts the supply of the clock to the central processing unit (1) after the central processing unit (1) is set to the retry start state by the forced error generating means (4), and The processing using the error data is performed, and the error processing circuit is verified by comparing the data of the processing result obtained from the central processing unit with the expected data obtained in advance by this processing.

According to the error processing circuit verification device of the present invention, the timing detection means sequentially notifies one or more retry methods according to the processing state of the test program being executed by the central processing unit. By executing the retry by the retry method selected from the retry methods, the error processing circuit can be properly verified.

〔Example〕

FIG. 2 shows an example in which the components of the verification method of the error processing circuit according to the present invention are configured by hardware. The blocks denoted by reference numerals 1 to 4 correspond to the central processing unit, the timing detection circuit, the error processing verification means and the forced error generation circuit, which are denoted by the same reference numerals in FIG.

Timing detector 21 of retry timing detection circuit 2
Monitors the control signals from the instruction processing control unit 11, the operation control unit 12, the memory access control unit 13 and the like in the central processing unit 1 to sequentially detect the processing timing of the central processing unit and execute at this processing timing. It sends to the gate 23 the possible retry method and the address of the memory in which the program step being processed at this timing is stored.

The gate 23 is turned on by a signal output from the interval control circuit 22 at a predetermined fixed interval, and the gate 23 performs a retry method and a process at this timing via a retry timing reporting circuit 24. The address of the memory storing the programmed program step is output at regular intervals.

The address of this memory is sent to the micro address matching circuit 31, and this address is sent to the error processing verification means 3
When it matches the address of the control storage for stopping the operation of the central processing unit from the error processing verification control unit 32, the clock of the central processing unit including the error processing circuit 15 to be verified is stopped and retry is possible. Keep the environment.

The error processing verification control unit 32 selects an executable retry method from the retry timing reporting circuit 24, and a retry condition according to this retry method is stored in advance in a mode register or the like in the error processing verification control unit 32. Error information such as pseudo error data for designating the content of the error to be generated according to the selected retry condition and supplied to the forced error generation circuit 4.

The error data including this pseudo error is stored in the register or memory of the arithmetic / memory unit 14 of the central processing unit 1 from the forced error generating circuit 4. The pseudo error generated by the compulsory error generating circuit 4 includes, for example, a parity error with respect to a register or the like in the central processing unit 1, a control error, or a RAM soft error with respect to a data RAM.

After the error data is stored in the central processing unit as described above, the error processing verification control unit 32 releases the clock stop of the central processing unit 1 by the micro address matching circuit 31, and the central processing including the error processing circuit 15 is performed. Device 1
The clock is supplied to and the retry is started.

As a result, the central processing unit performs the processing using the above-mentioned error data, so that an error based on the pseudo error occurs.

This error is processed by the error processing circuit 15 of the central processing unit. Depending on the content of the pseudo error, the error is corrected and correct data is output, erroneous data is output, or error processing is performed. The result is obtained such that the clock is stopped by the circuit 15 and the operation of the central processing unit 1 is stopped.

The processing result of the retry operation of the central processing unit 1 is monitored by the garbled data check mechanism 33 and the retry success check mechanism 34 in the data processing verification means 3, and an error of the central processing unit with respect to the pseudo error data is detected. It is verified whether the error processing by the processing circuit 15 has been normally executed.

According to this embodiment, as described above, one or a plurality of retry methods according to the processing timing of the central processing unit 1 is output from the timing detection circuit 2, and if there are a plurality of retry methods, the one retry method is output. The error processing verification means 3 selects a method, sets error data including a pseudo error in the central processing unit from the compulsory error generating circuit 4, and then the central processing unit is retried, and the obtained result is stored in the central processing unit 1. The response of the error processing circuit 15 to various retry methods can be automatically verified.

FIG. 3 shows a concrete circuit configuration example of the pseudo RAM error generation circuit 40 as an example of the forced error generation circuit 4 in FIG. 2 above. A pseudo error is generated in the data RAM 14 ₁ in the central processing unit 1. It is a circuit for storing error data including the data. In the figure, the components shown in the forties are the RAM
The constituent elements of the error generating circuit 40, which are designated by the reference numeral with the subscript of 14, are the components of the arithmetic unit of the central processing unit 1.
It is an element included in the memory unit 14.

This pseudo RAM error generating circuit 40, and a function of supplying data that includes a function and error supplies an address that contains the error in the data RAM 14 _1.

In normal operation, the arithmetic memory unit 14 of the address to access this data RAM 14 _1, for example a central processing unit 1
Stored in the address register 14 from _2, but via a multiplexer 42 which is controlled by a pseudo RAM error generation control section 41 of the pseudo RAM error generating circuit 40 is supplied as the address of the RAM 14 _1, to introduce a pseudo error address In this case, the multiplexer 42 is switched by the output of the pseudo RAM error occurrence control unit 41 to supply the address stored in the pseudo error address register 43 as the RAM access address.

The address stored in the pseudo error address register 43 is an address including a pseudo error supplied by the pseudo RAM error occurrence control unit 41 in accordance with switching of the multiplexer 44 controlled by the pseudo RAM error occurrence control unit 41 or This is the address from the adder 45 that adds n to the output address of the pseudo error address register 43.

Therefore, the pseudo error address register 43
An error in read data can be caused by writing an incorrect address from the RAM error occurrence control unit 41, and by storing data including a pseudo error described later in this address, the central processing unit 1 Can be made to process error data. The multiplexer 44 is switched to switch the pseudo error address register 43.
Since the data RAM 14 ₁ by storing the address obtained by adding n again this pseudo error address register 43 to the output address data from the address of every n are successively read, for example, as the data is a program In this case, consecutive program steps are not supplied, and the central processing unit 1 can be caused to perform erroneous processing.

Then, in the case of writing the wrong data to the data RAM14 ₁ is,
The multiplexer 46 is switched according to the output of the pseudo RAM error generation control unit 41 so that the error data from the pseudo error data register 47 or the 1-bit inversion circuit 48 is transferred to the RAM 1
Be sure to write to 4 ₁ .

By writing the error data from the pseudo RAM error occurrence control unit 41 to the pseudo error data register 47 and switching the multiplexer 49 so that the output of the register 47 is supplied to the RAM through the multiplexer 46, this error is generated. data is written to the data RAM 14 _1.

In addition, the multiplexer 49 is connected to the pseudo RAM error generation control unit 41.
1-bit inverting circuit 48 after switching by the output of
By inverting one bit of the correct data stored in the write data register 14 ₂ by, error data can be generated and written in this RAM 14 ₁ .

In this way, after writing the error data to RAM14 _1,
If the central processing unit 1 is caused to perform processing based on this error data, the error processing function of the error processing circuit 15 can be verified as described above.

FIG. 4 shows a second embodiment of the retry verification system configured by applying the present invention. In contrast to the hardware configuration of the above-described first embodiment, the second embodiment In the embodiment of FIG. 1, the main part of the timing detection circuit 2, the error processing verification means 3 and the forced error generation means 4 in FIG.
1 and 2 as a whole.
The operation is similar to that described with reference to the figure, and most of its functions are executed by the software of the error processing verification processor 50, so a detailed description of the operation will be omitted and only an outline will be given. explain.

The retryable timing of the central processing unit 1 is detected for each retry type by the timing detection unit 61 corresponding to the timing detection unit 21 in FIG. 2, and the information is given to the error processing verification processor 50.

The error processing verification processor 50 executes the various processes described above with reference to FIG. 1, but the error data necessary for executing the retry is the forced error generating means corresponding to the forced error generating means 4 of FIG. Given by 51.

The compulsory error generating means 51 causes an error by the software of the error processing verification processor 50. The register error generating means 51 ₁ and the RAM error generating means 51
_2. Various error generation functions such as control error generation means 51 ₃ are provided.
Corresponding pseudo error data is generated by selectively receiving activation from 50 and supplied to the central processing unit 1 to store the error data in a register, a storage device or the like.

The data processed using this error data is evaluated by the retry success check mechanism 62 and the garbled data check mechanism 63, and it is verified whether or not the error processing circuit of the central processing unit 1 is performing normal error processing.

〔The invention's effect〕

According to the present invention, the central processing unit can select the retry method that can be executed according to the processing state of the test program and automatically execute the retry, so that the error processing function of the error processing circuit can be verified reliably. And the special effect that it can be done quickly is achieved.

Further, according to the present invention, since it is possible to execute the retry by the planned retry method, the unscheduled retry method is executed even though both the central processing unit and the error processing circuit are operating normally. By doing so, the effect that the error processing circuit is not erroneously determined to have malfunctioned can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the first embodiment of the present invention, FIG. 3 is a diagram showing a concrete configuration example of a pseudo RAM error generating circuit, and FIG. Is a block diagram showing a second embodiment of the present invention, and FIG. 5 is an explanatory diagram of a retry function in the central processing unit. Reference numeral 1 is a central processing unit, 2 is a timing detection circuit, 3 is error processing verification means, and 4 is forced error generation means.

Claims (1)

[Claims] 1. A verification device of an error processing circuit for verifying an error processing circuit (15) provided in a central processing unit (1), the processing of a test program being executed by the central processing unit (1). Timing detection means (2) for sequentially checking the state and notifying the error processing verification means (3) of a retry method that can be executed at the processing timing, and an executable retry notified by the timing detection means (2). A retry method to be executed is selected from the methods, the forced error generating means (4) is activated, the supply of the processing clock of the central processing unit (1) is stopped to stop the central processing unit, and After the central processing unit (1) is set to the retry start state by the forced error generating means (4), the supply of the clock to the central processing unit (1) is restarted. The error processing circuit (15) is verified by comparing the data of the processing result obtained from the central processing unit by this processing with the expected data obtained in advance. Error processing verifying means (3), and forced error generating means (4) for supplying error data according to the retry method selected by the error processing verifying means (3) to the central processing unit to set the retry start state. An error processing circuit verification device comprising: