JPS55162159A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55162159A
JPS55162159A JP6909879A JP6909879A JPS55162159A JP S55162159 A JPS55162159 A JP S55162159A JP 6909879 A JP6909879 A JP 6909879A JP 6909879 A JP6909879 A JP 6909879A JP S55162159 A JPS55162159 A JP S55162159A
Authority
JP
Japan
Prior art keywords
signal
fault
address
circuit
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6909879A
Other languages
Japanese (ja)
Inventor
Hiroshi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6909879A priority Critical patent/JPS55162159A/en
Publication of JPS55162159A publication Critical patent/JPS55162159A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform dynamic fault processing by generating the read address of a control store and its corresponding address and then by comparing the both to each other before generating a corresponding false fault signal.
CONSTITUTION: In address register 4, address (d) corresponding to read address (b) of control store 1 is set externally and in artificial fault assignment register 5, information on what kind of an artificial fault should be generated is also set. Comparing circuit 6 compares the address of store 1 to the set address of register 4 and, when the both agree with each other, generates coincidence signal (f). Signal (f) is input to AND circuits 71W73; and the fault signal assigned by register 5 is passed through OR circuits 81W8n, and fault report signal h1Whn are sent to fault processing circuit 3. Circuit 3 informs instruction processing circuit 2 of the resalt and also sends signal C to circuit 6. Although circuit 2 takes a retry, circuit 6 stops the transmission of signal (f) by signal C and inhibits the artificial fault signal.
COPYRIGHT: (C)1980,JPO&Japio
JP6909879A 1979-06-01 1979-06-01 Information processor Pending JPS55162159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6909879A JPS55162159A (en) 1979-06-01 1979-06-01 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6909879A JPS55162159A (en) 1979-06-01 1979-06-01 Information processor

Publications (1)

Publication Number Publication Date
JPS55162159A true JPS55162159A (en) 1980-12-17

Family

ID=13392797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6909879A Pending JPS55162159A (en) 1979-06-01 1979-06-01 Information processor

Country Status (1)

Country Link
JP (1) JPS55162159A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428740A (en) * 1987-07-24 1989-01-31 Fujitsu Ltd Verification system for error processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428740A (en) * 1987-07-24 1989-01-31 Fujitsu Ltd Verification system for error processing circuit

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