JPH0392950A - Microprogram controller - Google Patents

Abstract

PURPOSE:To efficiently correct errors by providing a memory to store the error information of each microinstruction language, referring these error information when the microinstruction language is read out, and instructing the suppression of decoding to a decoder in advance. CONSTITUTION:A diagnosis control part 23 receives an error detection signal 210 from an error correction circuit 21, stops the operation of a computing element 7 and writes the error history information into the entry of an error history memory 22. Afterwards, the diagnosis control part 23 retests a software error instruction and when the address of the microinstruction language generating the error is set to a microaddress register 2, the microinstruction language including the error is read out from a control memory 1. Simultaneously, the error history information, which are written in advance, are outputted from the error history memory 22 to the diagnosis control part 23. The diagnosis control part 23 controls a switcher 11 so as to select an output 211 correcting the error of the microinstruction language and the output 211 after the correction is set to a control register 5. Thus, the decoding by the decoding can be suppressed in advance and efficiency for the error correction can be improved.

Description

TECHNICAL FIELD The present invention relates to microprogram controllers, and more particularly to microprogram controllers that include a control memory and execute microinstructions read from the control memory.

Prior art general 2, control notes MICRO PROGRA
MMING J(PRIENTICE-11ALL I
NG. It has been adopted in data processing devices as described in IIUssON ◎3970). Control memory accounts for a large portion of failures in this type of data processing apparatus, and error correction code technology has been adopted as a remedy for this problem (for example, there is Japanese Patent Publication No. 62-027417).

The conventional error correction operation was performed in the following steps.

■Read the microinstruction word from the control memory and set it in the control register.

■Check for errors using the well-known ECC method.

(2) If an error is detected, execution of the microinstruction word is inhibited and a syndrome is created.

■Errors are corrected based on the syndrome and re-execution is performed.

According to the conventional error correction techniques described above, the reliability of control storage can be significantly improved.

In addition, in realizing this technology, the use of the control memory output is inhibited upon detection of an error in the control memory output, error correction is performed in parallel with this inhibition, and the above-mentioned inhibition is performed when the error correction is completed. A procedure has been adopted to remove it. In this procedure, the delay time of the logic signal from the occurrence of an error in the control memory output to the inhibition of use is relatively long, and it is one of the critical paths that determines the machine cycle of the data processing device, and is one of the critical paths that determine the machine cycle of the data processing device. It has the disadvantage of hindering shortening.

Furthermore, if the above-mentioned suppression cannot be achieved in one machine cycle, a history of all operations within the range affected by the control memory output should be kept, and when an error occurs, the state immediately before the error occurs can be determined based on the history information. After the error correction occurs, the operation must be retried using the control memory output after error correction, making it impossible to implement an error correction function due to the amount of hardware required to retain the necessary history information and the complexity of retry control. Met.

Therefore, it has been desired to develop a more efficient error correction technique.

OBJECTS OF THE INVENTION The present invention has been made in order to solve the above-mentioned conventional drawbacks, and its purpose is to provide a microprogram control system that effectively corrects errors in the extremely short control memory of a machine cycle timer. The purpose is to provide equipment.

Structure of the Invention A microprogram control device according to the present invention is a microprogram control device that executes microinstructions read out from a control memory, and the microprogram control device executes microinstructions read out from a control memory, and the microprogram control device executes microinstructions read out from a control memory. an error history memory for storing error information indicating the presence or absence of an error; an error information reading means for reading the error information corresponding to the microinstruction from the error history memory when the microinstruction is read from the control memory; Suppression means for suppressing execution of the microinstruction when error information read by the information reading means indicates the presence of an error; and error correction for the error in the microinstruction when the suppression means suppresses the execution of the microinstruction. It is characterized by having a correction means.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of a microprogram control device according to the present invention.

In the figure, a microprogram control device according to an embodiment of the present invention includes a control memory 1, a switch 11, a control register 5, an error correction circuit 21, a decoder 6, and an arithmetic unit 7. It has been.

The microprogram control device according to this embodiment also includes a microaddress register 2, a switch 4, an adder 3, an address register 25, a switch 26, an error history memory 22, and a diagnostic control section 23. It consists of

The control memory 1 stores microinstructions, and the read address thereof is normally sent from the microaddress register 2 via the switch 4.

The micro address register 2 holds the output of the adder 3, which adds 1 to the output of the switch 4 which supplies the subsequent address of the control memory 1, as the next subsequent address.

The switch 4 selects the branch address field of the control register 5 instead of the output of the micro address register 2 in accordance with a branch instruction from the decoder 6.

Further, the output of the control memory 1 is sent to the control register 5 via the switch Y1. The output of this control register 5 is decoded by a decoder 6, thereby generating a control signal for controlling the above-mentioned switch 4 and arithmetic unit 7.

Furthermore, the output of the control register 5 is the error correction circuit 2.
1 is checked. The result of the check is reported to the diagnostic control section 23 as an error detection signal 210. Further, the error correction circuit 21 supplies output data after error correction to the switch 11.

The error history memory 22 stores the correctable error occurrence history of the control memory 1 in correspondence with the address of the control memory 1, and the address is normally stored in the switch 4 and the switch 2.
6. This writing operation to the error history memory 22 is performed by supplying the output of the address register 25 which receives the output of the cutting machine 4 as an address via the switch 26, and detecting the error sent from the error correction circuit 21 mentioned above. This is done by manually inputting the signal 210 via the diagnostic control unit 23. The diagnostic control unit 23 also controls writing to the error history memory 22 described above, as well as command retry control for all processors.

In the above groove, unlike the conventional control device, the output of the error correction circuit 21 does not suppress the output of the decoder 6. Therefore, with this configuration, if a microinstruction word containing an error is manually entered into the control register 5, the control signal from the decoder 6 will not be suppressed by the inspection result by the error correction circuit 21, and the error will remain in the arithmetic unit 7. will be used. Therefore, in this embodiment, as a countermeasure against this problem, the diagnostic control unit 23 performs error correction i11 and two circuits 2.
The error detection signal 210 from the processor 1 is received, and the operation of the arithmetic unit 7 in the processor is stopped.

Also, at this time, the control memory 1 supplied from the switch 4
The address register 25 that holds the subsequent address of the microinstruction word held in the control register 5, that is, the address of the microinstruction word containing an error in the control memory 1, remains.

Clinic 1, clinic N23 switches switch 26 to address register 2
5 side, and writes "1" as error history information to the entry in the error history memory 22 corresponding to the address to be held. In other words, if it is "1", it indicates that an error has occurred before, and if it is "0", it indicates that no error has occurred before.

Thereafter, the diagnostic control unit 23 retries the soft error instruction including the microinstruction word that caused the error. In this process, when the address of the microinstruction word in which the error occurred is set in the microaddress register 2, the microinstruction word containing the error is read out from the control memory 1 via the switch 4. At the same time, the error history memory 22 is accessed via the switch 26.

As a result of this access, previously written error history information is output from the error history memory 22 to the diagnostic control unit 23. The diagnostic control unit 23 determines that the received error history information is “1”.
”, therefore, it sends an instruction to the decoder 6 to suppress the decoding of the microinstruction word containing the error in the control register 5. In parallel, the diagnostic control unit 23 reads the control register 5 output from the error correction circuit 21. The switch 11 is controlled to select the output 211 in which the error in the microinstruction word within is corrected.The error correction is completed by setting the corrected output 211 to the control register 5.Subsequently, and cancels the above-mentioned decoding inhibition instruction to the decoder 6,
The control operation is continued using the microinstruction word in the control register 5, that is, the corrected microinstruction word.

In other words, the history of a microinstruction word that once caused an error is stored in memory, and by constantly referring to this history, it is possible to prevent the decoder from decoding the microinstruction words before they occur, thereby improving the efficiency of error correction.

Therefore, the error correction operation in this embodiment is performed in the following steps.

(2) Read the microinstruction word from the control memory and set it in the control register, and read error history information from the error history memory entry corresponding to the microinstruction word.

(2) If the error history information is "0", check for errors using a well-known ECC method or the like.

(2) If an error is detected, that fact is reported to the diagnostic control unit, the execution of the microinstruction word is inhibited, and a syndrome is created.

(2) After the syndrome is created, "1" is written as error history information to the entry in the error history memory corresponding to that Mark R instruction word.

(2) The diagnostic control unit determines whether the command can be retried, and if it is not possible, the operation is stopped.

(2) If retry is possible, read the same microinstruction word from the control memory again, set it in the control register, and read error history information from the error history memory entry corresponding to the microinstruction word.

(2) In this case, since the error history information is "1", execution is immediately inhibited and a syndrome is created.

(2) After the syndrome is created, the microinstruction word is error corrected in the error correction circuit and set in the control register.

(2) By canceling the execution inhibition here, the error correction operation is completed before the decoder performs decoding.

As described above, the present invention provides an error history memory, notifies the diagnostic control unit of the existence γF of a microinstruction word containing an error before its execution, and instructs the decoder to suppress decoding. This is what we are doing. Therefore,
Check the output of the control register for errors as before,
As a result, decoding is inhibited immediately upon detection of an error, without using a path with a large signal delay time to instruct the decoder to inhibit decoding. In other words, the present invention contributes to shortening the machine cycle.

Effects of the Invention As explained above, the present invention provides a memory for storing error information of each microinstruction word, and refers to this error information when reading a microinstruction word to instruct the decoder to suppress decoding in advance. This has the effect that errors can be corrected efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a macro program control device according to an embodiment of the present invention. Explanation of symbols of main parts] ... Control memory 5 ... Control register 2 2 2 6 ... Decoder 1 ... Error correction circuit 2 ... ...Error history memory 3...Diagnosis control section

Claims (1)

[Claims] (1) A microprogram control device that executes microinstructions read from a control memory, and an error history memory that stores error information indicating the presence or absence of an error when each microinstruction in the control memory was last read. and error information reading means for reading out the error information corresponding to the microinstruction from the error history memory when the microinstruction is read out from the control memory, and error information read out by the error information reading means is error information. A micro-instruction device characterized in that it has an inhibiting means for inhibiting the execution of the micro-instruction when the inhibition means inhibits the execution of the micro-instruction, and an error correction means for correcting an error in the micro-instruction when the inhibiting means inhibits the execution of the micro-instruction. Program control device.