JPH02204839A - Information processor - Google Patents

Abstract

PURPOSE:To easily execute the retry processing by inhibiting the execution of an instruction in which an output error is detected in response to an exception signal generated at the time when an output error of a memory decoder is detected, and executing the retry processing. CONSTITUTION:When an exception detecting and reporting circuit 13 knows a fact that an error is detected in an output of a RAM decoder 12 by a result of RAM output error check from an error detecting circuit 14, an exception code for showing a fact that the error is detected in the output of the RAM decoder 12 is given and informed to a control unit 4, and by the control unit 4, an exception control firmware corresponding to the exception code is started. That is, the control unit 4 controls a memory buffer unit 2 and an arithmetic unit 3 and inhibits the execution of an instruction in which an error is detected by the error detecting circuit 14. Thereafter, the control unit 4 reloads the contents of the RAM decoder 12 and executes a retry processing. In such a way, in the case when the output error is a software error, the retry can be executed 100%.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to retry processing in the event of a soft error in an instruction code memory decoder provided in the information processing device.

Conventionally, in information processing devices, RAM (Random) is indexed by instruction code and holds exception information and control information of the preceding control unit in the first step of each instruction in correspondence with each instruction. Access He-1
As soon as an error is detected in the output of the decoder (E I F
lag), the detection of the error is notified to the service processor (SVP) via the diagnostic processor (DGP), and error processing for the error is performed.

In general, there are two types of memory failures: soft errors that cause data corruption due to passage of alpha rays, etc., and hardware failures.In the case of soft errors, it is not the fault of the hardware itself. However, normal operation can be performed by writing data to the memory again.

In such conventional information processing devices, R is indexed by instruction code and holds exception information etc. corresponding to each instruction.
Even if the AM decoder output error is a soft error,
The EIF was immediately turned on and the error was processed by notifying the service processor via the diagnostic processor that the error had been detected, so while this error processing was in progress,
The instruction that caused the data error in the calculation system is executed,
The drawback is that there is a very high probability that retry processing will be impossible.

The present invention has been made to eliminate the drawbacks of the conventional methods as described above, and provides information processing that can easily perform retry processing when an output error of a memory decoder is a soft error. The purpose is to provide equipment.

An information processing device according to the present invention includes a memory decoder for decoding an input instruction, a detection means for detecting an output error of the memory decoder, and when the output error is detected by the detection means. The present invention is characterized by comprising a generating means for generating an exception signal, and a means for suppressing execution of the instruction in which the output error has been detected in response to the exception signal, and performing retry processing from the instruction.

x1■ Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG.
When an instruction word is supplied to the advance control unit 1, an execution address is generated using the instruction word held in the register 11, and an access request code to the memory 5 to be notified to the memory buffer unit 2 is generated. , an instruction code RAM in which an exception detection specification field, etc. corresponding to each instruction is stored at the same time according to the instruction code of the instruction word.
A decoder (hereinafter referred to as a RAM decoder) 12 is indexed.

The RAM decoder 12 uses the instruction code as an index.
Necessary information regarding exception detection corresponding to the instruction word (such as information instructing to detect an exception by checking whether a specific bit of the instruction word is "0" or not) is notified to the exception detection reporting circuit 13.

At this time, the output from the RAM decoder 12 is checked by a parity check or the like in the error detection circuit 14, and the result of this check (hereinafter referred to as the RAM output error check result) is notified to the exception detection reporting circuit 13.

When the exception detection reporting circuit 13 receives necessary information regarding exception detection from the RAM decoder 12, it detects whether an exception has occurred based on the instruction word and each mode.

In addition, the exception detection report port F#113 is connected to the error detection circuit 14.
When it learns that no error has been detected in the output of the RAM decoder 12 from the RAM output error check result from the RAM decoder 12, if no exception has occurred in the instruction word, it notifies the control unit 4 that no exception has occurred. However, if an exception has occurred in the instruction word, an exception code indicating the type of exception is given to the exception with the highest priority, and the control unit 4 is notified.

When the control unit 4 learns of the occurrence of an exception from the notification from the exception detection reporting circuit 13, the exception control firmware corresponding to the exception code is activated.

Furthermore, when the exception detection reporting circuit 13 learns that an error has been detected in the output of the RAM decoder 12 from the RAM output error check result from the error detection circuit 14, the exception detection reporting circuit 13
An exception code indicating that an error has been detected is added to the output of the M decoder 12 and notified to the control unit 4, and the exception control firmware corresponding to the exception code is activated in the control unit 4.

That is, the control unit 4 controls the memory buffer unit 2 and the arithmetic unit 3 by activating the exception control firmware corresponding to the exception code, and suppresses execution of the instruction in which the error detection circuit 14 detects an error.

After this, the control unit 4 reloads the contents of the RAM decoder 12 and performs a retry process, since this is an exception notified by detecting an error in the output of the RAM decoder 12.

At this time, if the output error of the RAM decoder 12 is a soft error, 100% retry is possible for this output error of the RAM decoder 12.

In this way, when an error is detected in the output of the RAM decoder 12 in the error detection circuit 14, the exception detection reporting circuit 13 notifies the control unit 4 of the error as if it were an exception with the highest priority. By inhibiting the execution of the instruction in which the error occurred by the control unit 4, and reloading the contents of the RAM decoder 12 to perform retry processing, a RAM decoder caused by a soft error can be fixed with a simple addition of hardware. 12
Even if an error is detected due to garbled data in the contents of R.
By reloading the contents of the AM decoder 12, garbled data can be corrected and retry processing can be easily performed.

In one embodiment of the present invention, the RAM decoder 12 has been described in which an exception detection specification field corresponding to each instruction is stored, but the present invention may also be applied to a RAM decoder that controls address generation in a preceding control unit, etc. but is not limited to this.

As explained above, according to the present invention, an exception signal is generated when an output error of a memory decoder is detected, and in response to the exception signal, execution of the instruction for which the output error has been detected is executed. By suppressing the instruction and performing retry processing from the instruction, there is an effect that retry processing can be easily performed when the output error of the memory decoder is a soft error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1... Advance control unit 4... Control unit 12... Instruction code RAM decoder 13...
... Exception detection reporting circuit 14 ... Error detection circuit

Claims (1)

[Claims] (1) a memory decoder that decodes input instructions; a detection means that detects an output error of the memory decoder;
generating means for generating an exception signal when the output error is detected by the detection means; and suppressing execution of the instruction in which the output error has been detected in response to the exception signal, and performing retry processing from the instruction. An information processing device comprising: means.