JPH04184550A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate abnormal operations of an information processor and to prevent the destruction of a memory by making a processor to fetch an object code for stopping the instruction of the processor when an uncorrectable error occurs. CONSTITUTION:In the case an error detection/correction circuit 22 detects an uncorrectable error when a processor 11 reads out data from a main storage device 14, a buffer controller 23 sets a buffer 31 to a disabled state so that the buffer 31 cannot drive data to a data bus 114 and sets another buffer 33 so that the buffer 33 can drive the data on a data bus 118 to a data bus 115. Since an object code generation circuit 24 generates object codes which stops the instructions of processors 11-13, the processor 11 fetches the object code which stops its instruction through data buses 114, 1, and 11 and stops the operations of the processor 11. Therefore, abnormal operations, such as destruction of a memory can be prevented and normal processing operations can be secured after the error occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a fault notification system when a fault occurs in the information processing device.

[Conventional technology]

In the conventional system, an error detection and correction circuit exists in the main memory, and when a correctable error occurs, the error detection and correction circuit invalidates the output data of the memory module and converts the corrected data into data. However, if an uncorrectable error occurs, it will only notify the system bus that an uncorrectable error has occurred, and will not send the error output from the memory module to the data bus. The included data was output.

[Problem that the invention seeks to determine]

In the conventional error notification method described above, when an uncorrectable error occurs, the output of the memory module containing the error is output to the data bus as is, so the error is detected when the processor code fetches. If this occurs, abnormal operations may occur while the error-containing data is fetched and the occurrence of the error is recognized, potentially causing memory corruption. Therefore, there is a drawback that normal operation cannot be expected after recognition of the occurrence of an error, usually after recognition of an interrupt.

[Means for solving problems]

The information processing device of the present invention suspends execution of instructions for a processor in a multiprocessor system in which a plurality of processors and a main storage device whose object codes are compatible are connected to one system bus. When an uncorrectable error is detected in the means for generating object code and the main memory, the drive to the data bus from the memory module in the main memory or the error detection and correction circuit is disabled, and the execution of instructions is disabled. and means for enabling driving of the object code to be stopped onto the data bus.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Processor 11, Processor 12 and Processor 13
via data buses 111, 112 and 113 and control signals 121, 122 and 123, respectively.
It is connected to a system bus having a data bus 1 and a control signal group 2, and a main storage device 14 is also connected to the system bus. Inside the main memory bag W14, there are a memory module 21 that holds data and a memory module 2.
an error detection and correction circuit 22 (hereinafter referred to as EDCC 22) that detects errors in data output from 1; and a circuit 24 that generates an object code that stops execution of instructions of the processor 11, processor 12, or processor 13;
, the data bus 116 of the memory module 21, and the ED
Data buses 114 and 1 are connected to the data bus 117 of the CC 22, the data bus 118 of the object code generation circuit 24, and the data bus 1 of the system bus.
15, each data hash buffer 31, 32 between
33 using control signals 125, 124, and 126.

Further, the EDCC 22 and the memory module 21 are connected via a checkerboard 119.

When EDCC22 detects an error, error signal 1
27 to the buffer control 23, and the buffer control 23 detects the error (No. 8 1) as necessary.
28 to the control signals of the system bus.

The operation of this embodiment will be explained using FIG. 1.

When the processor 11 writes data to the main memory 14, the write data is transferred to the data bus 111 of the processor 11.
The data is output to data bus 1 on the system bus through the bus, and taken into data bus 114 in main memory 14 . At this time, the buffer control 23 sets the data bus buffer 31 using the control signal 125 to drive data from the data bus 114 to the data bus 116, and sets the data bus buffer 32 using the control signal 125. using the data bus 114
The data bus 117 is sent to the data bus 117 to drive data. The data bus buffer 33 is disabled using the control signal 126 so that it is not driven onto the data bus 115. Now, data bus 114
The data taken in is transferred from the buffer 31 to the data bus 11.
6 and written to the memory module 21. At this time, the EDCC 22 uses data of the same value as the data on the data bus 116 driven from the buffer 32 to the data bus 117 to generate a check word, drives it to the check word bus 119, and writes it to the memory module 21. It's crowded.

Next, a case in which the processor 11 reads data from the main storage device 14 will be described.

Data is output from the memory module 21 to the data bus 116, and the check word is output to the check word bus 119.
is output to. At this time, the ``Sofa control'' sends the control signal 12 to the data bus buffer 31.
5 is used to drive data from the data bus 116 to the data bus 114, and for the data hash buffer 32, the control signal 124 is used to drive data from the data bus 114 to the data bus 117. For the data path buffer 33, the control signal 126 is used to control the data bus 115.
Disable it so that it does not drive data to it. Data on data bus 116 is driven to data bus 114 by buffer 31 and then driven to data bus 117 by buffer 32. In the EDCC 22, the data on the data bus 117 and the check word bus 11 are
Take in the first and second words above 9 and check whether there are any errors in the data.

The operation of Ijin will be explained in three cases.

First, if there is no error in the data as a result of checking the data in the EDCC 22, the buffer control 23 is notified that there is no error through the error signal 127, and the buffer control 23 receives the control signal 127. , 125°126 are left as they are. Therefore, the data on the data bus 114 is output to the data bus I of the system bus, and the processor 11 takes in the data through the data bus III.

Second, if the EI]CC 22 detects a correctable error in the data checking process, the EDCC 22 notifies the buffer control 23 through the error signal 127 that a correctable error has been detected; moreover,
Corrected data is driven onto the data bus 117. The buffer control 23 receives the control signal 12
5 is used to disable buffer 31 from driving data onto data bus 114, and control i is used to disable buffer 32 from driving corrected data on data bus 117 onto data bus 114. 124 to reverse the drive direction of the buffer 32. Note that the control signal 126 for the buffer 33 is currently disabled. Therefore, the corrected data driven onto data bus 114 is output to data bus 1 of the system bus and processor 1
1 will take in the corrected data through the data bus 111.

Third, if the EDCC detects an uncorrectable error in the data checking process, the EDCC 22 notifies the buffer control 23 through the error (No. 8 127) that an uncorrectable error has been detected. Buffer control 23 uses control signal 125 for buffer 31 to disable it from driving data onto data bus 114, and uses control signal 126 for buffer 33 to disable data on data bus 118 from driving data onto data bus 115. Cent like driving.

Note that the control signal 124 of the buffer 32 remains as it is, and continues to be driven to the data bus 117. At this time, in the object code generation circuit 24, the processor 11. It generates an object code that stops the instructions of the processors 12 and 13, and always drives it to the data bus 118. Therefore buffer 33
An object code for stopping commands to the data bus 115 is output to the data bus 1 of the system bus through the drive 1 data bus 114. Further, in the buffer control, the error signal 128 is activated to notify that an error has occurred in the system control signal 2. The processor 11 takes in an object code to stop the instruction through the data bus 111, and further recognizes through the control signal 121 that an error has occurred. (The processor recognizes the error through the il regular interrupt line.) The above operation is similar when the processor 12 or the processor 13 performs writing or reading.

Additionally, if an uncorrectable error occurs during a code fetch during a read operation, processors 11, 12, and 13 have compatible object codes, so no matter which processor performs the read, the instruction will continue to operate until the error is recognized by an interrupt. stops.

〔Effect of the invention〕

As explained above, the present invention enables the processor to incorporate an object code that stops processor instructions when an uncorrectable error occurs when the processor reads data from the main memory. When an error occurs during code fetching, the processor stops operating, so it has the effect of preventing abnormal operations such as memory corruption while recognizing the error, and allowing processing to operate normally after the error occurs. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the present invention. DESCRIPTION OF SYMBOLS 1... Data bus of system bus, 2... Control signal group of system bus, 11-13... Processor, 14... Main storage device, 21... Memory module, 22... EDCC ( error detection correction circuit), 23
...Buffer control, 24...Object code generation circuit, 31-33...Data hash buffer, 111-113...Data bus of processor, 11
4-118... Data bus of main storage device, 119...
- Check word bus, 121-123... Processor control signal, 124-126... Data hash buffer control signal, 127.128...
error signal. Agent Patent Attorney Yang Ping Yamashita

Claims (1)

[Claims] In a multiprocessor system in which a plurality of processors whose object codes are compatible and a main storage device are connected to one system bus, means for generating object code for stopping execution of instructions for the processors; , when an uncorrectable error is detected in the main memory, the drive to the data bus from the memory module or error detection and correction circuit in the main memory is disabled, and the object code stops execution of instructions. and means for enabling a drive to a data bus.