JP2559531B2 - Redundant system error check circuit - Google Patents

Description

The present invention relates to an error check circuit of a duplex system in which a memory and two processors are connected to each other, and an object thereof is to reliably detect a memory failure. In a redundant system composed of two connected processors, an error correction coding circuit for correcting an error of data read from a memory in each processor and an error flag for holding the error information when there is an error. And an AND circuit that ANDs the contents of its own error flag with the contents of the error flag from other system are provided. Only when all the error flags of own system and other system are "1", the error from the processor on the master side occurs. It is configured to output a notification signal.

[Field of Industrial Application] The present invention relates to an error check circuit of a duplex system in which a memory and two processors are connected.

In a computer system that requires reliability, a redundant system in which a memory and two processors are connected is often used. In this case, if one of the two processors is the master and the other is the slave, the master side performs the actual operation, and if a failure occurs on the master side,
It switches to the slave side and continues processing. In this type of duplex system (also called a dual system), both the processor side and the memory can fail, but if the memory fails in particular, the entire system will be down, so the duplex system is also meaningless. Disappear. Therefore, memory faults must be reliably detected.

[Prior Art] FIG. 4 is a conceptual diagram of a configuration of a conventional system. Memory 1
Two processors 2 are connected to. Of these two processors 2, one is a master and the other is a slave. These master processor and slave processor exchange data with the memory 1 and execute a predetermined job. 3 is a bus. Of these processors, the master processor is actually connected to the bus 3. Therefore, the slave processor is operating as a dummy during this period.

Reference numeral 4 is a comparator for comparing the output of the master processor 2 and the output of the slave processor 2. This comparator 4 is provided outside the system. If the two data do not match, the comparator 4 outputs a failure detection signal as if there is a failure in either the memory 1 or the processor 2.

FIG. 5 is a conceptual diagram of another configuration of the conventional system. In this system, two processors 2 each have a memory 1
It is the same as in FIG. 4 that is connected to and executes a predetermined job. The difference from the system of FIG. 4 is that both processors 2 are connected to a bus 3. The output of the master is read to the slave side via the bus 3 while both processors 2 are operating. The read data is compared with the output data on the slave side by the comparison unit 2a provided on the slave side. As a result, the comparing section 2a outputs an error signal when both data do not match.

FIG. 6 is a time chart showing the operation of the system shown in FIG. If a failure occurs on the master side (), an error interrupt signal is output by the error detection mechanism described above (). An interrupt signal enters the interrupt routine (), and the cause of the interrupt is read (). In this case, a comparison error is detected on the slave side.

Conventionally, in this type of system, only comparison of bus data was performed. In recent years, not only bus system data but also other control signals have been compared. As a result,
ECC error bits are also being compared. FIG. 7 is a diagram showing a method of detecting an ECC error. Memory 1
Is provided with a check bit adding section 1a, which is designed to be read in a state in which a check bit for error detection is added to data. The data read from the memory 1 is processed by the error correction coding circuit (EC
Enter C circuit) 21.

In the ECC circuit 21, when the input data has a 1-bit error, the error is corrected and output. The corrected data is used for data processing by the data processing unit 23 inside each processor.

Here, if error correction is performed in the ECC circuit 22, the ECC
The circuit 21 outputs an error correction bit (error bit).
This error bit is written in the error flag 22. The error flag may be output when there is a failure in the memory 1 or when there is a failure between the memory 1 and after and the ECC circuit 21.

A comparator 23 is provided on the slave side to compare the error bits. The comparing unit 23 compares the error bit on the master side and the error bit on the slave side, which are input via the bus 3, and outputs an error signal when both bits do not match.

[Problems to be Solved by the Invention] Since ECC check bit errors are also compared in the conventional method, the following problems occur.
As a case where 1 is set in the error bit by ECC, the following modes can be considered.

(1) When the ER flag is "0" on both the master side and the slave side In this case, no ECC check bit error has occurred on either the master side or the slave side. In other words, it is completely normal.

(2) When the ER flag on the master side is "1" and the ER flag on the slave side is "0" In this case, an ECC error has occurred on the master side and no ECC error has occurred on the slave side.

(3) When the ER flag on the master side is "0" and the ER flag on the slave side is "1" In this case, an ECC error has occurred on the slave side and no ECC error has occurred on the master side.

(4) When the ER flag is "1" on both the master side and the slave side In this case, an ECC error has occurred on both the master side and the slave side.

For example, if the circuit shown in FIG. 7 tries to detect this ECC error, something strange will occur. That is, even if an ECC error occurs, the correction data has a correct value and can be operated as it is. Nevertheless, the comparing unit 23 on the slave side generates an error signal if the values of both ER flags do not match. Furthermore, when an ER error occurs on both the master side and the slave side, the comparing unit 23 compares “1” to each other, so that the ECC error is recognized even though both processors have an ECC error. There is also the problem that it cannot be done. This is based on the fact that the comparison unit 23 can detect the failure only as a mismatch between the two values.

The most problematic case when an ECC error occurs is the case (4) in which both the master side and the slave side detect the ECC error. This is because, in this case, both of the processors 2 detect the ECC error, so that it is predicted that a failure has occurred on the memory 1 side. As described above, when a failure occurs in the memory 1, the device cannot function and the system goes down. Therefore, it is necessary to promptly detect such a case.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an error check circuit of a duplex system capable of surely detecting a memory failure.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 7 are designated by the same reference numerals. In the figure, 1 is a memory, and 2 is two processors connected to the memory 1. With one of these processors as the master,
Use the other as a slave. 21 is an error correction coding circuit (ECC circuit) that performs error correction coding on the data read from the memory 1, and 22 is an error flag that holds an error flag when there is a 1-bit error when performing error correction. (ER flag). An AND gate 24 receives the output of its own ER flag 21 at one input and the output of the ER flag 22 from the other processor at the other input. Although the AND gate 24 is shown only on the master side in the figure, the AND gate 24 is provided on the slave side as well.

[Operation] If an ECC error occurs in both the master and slave processors 2, the outputs of the ER flag 22 are all "1", and the output of the AND gate 24 is "1" and an error notification signal is output. . This error notification signal is given to the memory control unit (not shown) as an interrupt signal. As a result, abnormal processing is performed. Where both
When the ER flag 22 is "1", a failure of the memory 1 is predicted and it is an important failure. Therefore, error processing is performed. If the ER flags of both processors 2 are both "0" and only one of them is "1", it means that there is no 1-bit error or the error has been corrected, and the failure also occurs. Since it is predicted that the memory is not the memory 1, the error notification is not issued in these cases. As described above, according to the present invention, it is possible to provide the error check circuit of the duplex system capable of surely detecting the memory failure.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIGS. 1 and 7 are designated by the same reference numerals. In the figure, 1 is a memory, and 1 a is a check bit addition unit provided in the memory 1. 2 is the master,
Each slave is a processor. Due to the configuration of the duplex system, these processors 2 are configured to perform exactly the same operation.

Reference numeral 21 is an ECC circuit that performs error correction coding on the data read from the memory 1, and 22 is an ER flag that holds "1" when an error is detected as a result of the ECC check. An AND circuit 24 compares the ER flags of the own system and other systems. Of these AND circuits 24, the output of the AND circuit on the master side becomes an error notification signal, which is input as an interrupt signal to a memory control unit (not shown).

Reference numeral 25 is a tri-state buffer that outputs the data error-corrected by the ECC circuit 21 to the bus 3. Of these tri-state buffers 25, the master side inputs "1" and activates the buffer 25. On the other hand, on the slave side, "0" is entered to make the buffer 25 high impedance. As a result, the data on the slave side is not output to the bus 3.

Reference numeral 26 is an input buffer for fetching the data (data of another system processor) input via the bus 3 into each processor. Reference numeral 27 is a comparison unit that compares the captured data with its own data. In other words, this comparison unit 27 is the ECC circuit 21 of the processor 2 that constitutes the duplex system.
Output data will be compared with each other. When the data do not match, the comparing unit 27 on the slave side outputs an error signal. The operation of the circuit thus configured will be described below.

The processors 2 on the master and slave sides respectively read the data from the memory 1. Checked bits for error correction by the check bit adding circuit 1a are attached to the read data. The read data enters the ECC circuit 21 and undergoes error correction coding. If a 1-bit error is found here, each ER flag
“1” is written to 22. Where each ER flag
There are the following modes depending on the contents of 22.

(1) Both ER flags are both “0” In this case, there is no ECC error, which is a normal state. Therefore, the data processing unit (not shown) performs data processing on the data read from each ECC circuit 21. At this time, it goes without saying that the data processing unit connected to the bus 3 is on the master side. Dummy data processing will be performed on the slave side.

(2) Master side ER flag is “1”, slave side ER flag is “0” In this case, the master side has an ECC error and the slave side has no error. In this case, it is not considered that the memory 1 has a failure,
Moreover, since the correction data is normal, no error processing is performed. So in this case, both AND gates
All of 24 are "0" and no error notification signal is output. EC
Although the C error notification signal is not output, since the comparing unit 27 causes a mismatch in both data, the comparing unit 27 on the slave side outputs an error signal. Further, it goes without saying that an error signal is output even when data mismatch occurs. In that case, the error signal indicates a data mismatch, and does not indicate an ECC error.

(3) Master side ER flag is "0", slave side ER flag is "1" In this case, the slave side has an ECC error and the master side has no error. In this case as well, as in the case of (2), it is not considered that a failure has occurred in the memory 1, and since the correction data is normal,
No error processing is performed. That is, in this case, both AND gates 24 are both “0”, and no error notification signal is output. No ECC error notification signal, but comparison unit 2
In the case of 7, there is a discrepancy in both data, so that an error signal is output from the comparing section 27 on the slave side.
Further, it goes without saying that an error signal is output even when data mismatch occurs. In that case, the error signal indicates a data mismatch, and does not indicate an ECC error.

(4) Both ER flags are both "1" In this case, the ER flags 22 of both processors 2 are both "1", which is an important case where a failure of the memory 1 is suspected. As a result of both ER flags 22 being “1”, the outputs of both AND gates 24 are both “1”, and the error notification signal is output from the AND gate 24 on the master side. This error notification signal is given to a memory control unit (not shown) as an interrupt signal, and abnormal processing is performed. In this way, the failure of the memory 1, which is an important failure of the system, can be detected reliably and promptly.

FIG. 3 is a time chart showing the operation of the present invention.
When an ECC error occurs only on the master side (), the error signal is output as described above, but the interrupt notification signal (error notification signal) is not output (). On the other hand, when an ECC error occurs on both the master and slave sides (), both an error signal and an interrupt notification signal are output (). A memory control unit (not shown) enters an interrupt routine () in response to this error notification signal, and performs an abnormality process. The cause of the interrupt is read in the interrupt routine (). Unlike the conventional example shown in FIG. 6, no comparison error is detected on the slave side.

[Effects of the Invention] As described in detail above, according to the present invention, in a duplex system in which a memory is shared by two processors, it is possible to reliably detect a failure in the memory. An error check circuit can be provided.

[Brief description of drawings]

 FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a time chart showing the operation of the present invention, and FIG. 4 is a conceptual diagram showing the configuration of a conventional system. FIG. 5 is another conceptual diagram of the configuration of the conventional system, FIG. 6 is a time chart showing the operation of the conventional system, and FIG. 7 is a diagram showing the conventional ECC error detecting system. In FIG. 1, 1 is a memory, 2 is a processor, 21 is an ECC circuit, 22 is an ER flag, and 24 is an AND gate.

Claims (2)

(57) [Claims] 1. In a duplex system comprising a memory (1) and two processors (2) connected to the memory (1), data read from the memory (1) in each processor (2). Error correction coding circuit (21) that corrects the error, error flag (22) that holds the error information when there is an error, the content of own error flag (22) and the error flag from other system An AND circuit (24) for ANDing the contents of (22) is provided so that the error notification signal is output from the processor (2) on the master side only when all the error flags of its own system and other systems are "1". An error check circuit for a redundant system, which is characterized in that 2. The processor (2) on the slave side compares the data fetched from the master side with the data within itself, and outputs an error signal if a mismatch occurs. The error check circuit of the duplex system according to claim 1.