JPS6234436A - Data trouble detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the quantity of the hardware used in a data trouble detecting circuit so as to make maintenance of the circuit easier, by making the selecting designation of a selector the same as parity rule designating information. CONSTITUTION:Usually, command from a parity rule designating information line 70 is an odd parity rule and a 2-1 selector 9 selects an OR circuit 8a. If a trouble occurs on at least one side of memory circuits 41 and 42 under this condition, the output of the OR circuit 8a becomes to have a logic '1' and trouble information is outputted to the check result outputting information line 60 of the 2-1 selector 9. When the information from the information line 70 is changed to an even parity rule, the selector 9 selects an AND circuit 8b. The output of the AND circuit 8b becomes to have a logic '1' only when the trouble information is outputted to both check result outputting information lines 61 and 62 and trouble information indicating that normality of parity generating circuits 21 and 22 and parity checking circuits 51 and 52 is confirmed is outputted to the check result outputting information line 60 of the 2-1 selector 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data failure detection circuit using high IJT information.

[Conventional technology]

FIG. 2 is a block diagram of a conventional example of a data failure detection circuit using this type of parity information.

The parity generation circuit 21 (or 22, the same applies hereinafter) has n
The bit (n≧1) data line 11 (1, 2) is drawn in, and the parity rule specification information line 71 (72) generates parity information for n-bit data according to the odd parity rule specification of the color, and the parity information line 31 ( 8B). The memory circuit 41 (42) is connected to the data line 11 (12)
and parity information line 31 (82) are drawn in to accumulate data and parity information, and further output the accumulated data and parity information to data line 11 (12) and parity information line 581 (82), respectively. The parity check circuit 51 (52) checks whether the parity information from the memory circuit 41<42) is an odd parity with respect to the data from the memory circuit 41 (42), and outputs the check result only in case of error. Information 1a61 (62
) outputs failure information.

In other words, if the memory circuit 41 (42) is normal, the check result output information line 61 ((32) does not show fault information, and if the memory circuit 41 (42) has a fault such as bit stack, the check result is output. Information line 61 (62)
Since fault information is output to the parity generation circuit 21 (
22) and the parity check circuit 51 (52), the normality of the memory circuit 41 (4z) is being checked.

Furthermore, it is necessary to check whether the parity generation circuit 21 (22) and the parity check circuit 51 (52) are operating normally. In contrast, by switching the parity rule specification from the parity rule specification information line 71 (72) from the normal odd parity rule to the even parity rule, the parity information on the parity information line 81 (82) can be changed to n-bit data. Since the parity is even for the parity check circuit 51 (52),
Check result output information line 61 (62)
) failure information is output. This failure information when specifying the even parity rule indicates the normal operation of the parity generation circuit 21 (22) and the parity check circuit 51 (52), and conversely, if failure information is not output, it is an Fi failure.

The section from the parity generation circuit 21 (22) to the parity check circuit 51 (52)t is called a parity section, and FIG. 2 shows two parity sections.

[Problem that the invention seeks to solve]

The conventional data failure detection circuit using parity information described above requires m parity rule specification information lines and m check result output information lines when m (m≧2) parity sections exist. Therefore, m clips of 70 pieces are required to be installed before the parity rule specification information line and hold the parity rule instruction information from the test diagnosis program, and after the check result output information line, maintenance using an online program is required. m answer circuits are required for scanning reading orders.

Traditionally, there was only one parity section in the minimum maintenance unit in which equipment detects a failure and replaces it with maintenance supplies, but with recent high integration technology, there are now multiple parity sections. For this reason, conventional data failure detection circuits have increased costs due to the increase in flip 70 tubes that hold parity law instruction information and answer circuits for maintenance 9 scanning, and have become complicated to maintain due to an increase in the number of failure indication voices. It has the disadvantage of becoming

[Means for solving problems]

In the data fault detection circuit of the present invention, each parity rule designation information line is commonly connected to share parity law designation information, and the check results of m (m: 2 or more in a parity section) parity check circuits are output. A first gate circuit that outputs a predetermined logic value signal when at least one piece of information indicates that there is a fault, and a first gate circuit that outputs a predetermined logical value signal when at least one of the pieces of information indicates that there is a fault, and A second gate circuit that outputs a logical value signal and parity rule designation information on a parity law designation information line as an input selection signal, the output of the first gate circuit selects the output of the second gate circuit, It is characterized by having a 2i-1 selector that outputs as failure information.

That is, according to the present invention, since only one parity law designation information line and one check result output information line are required, the number of clip-flops and maintenance scanning answer circuits that hold parity law designation information is one each.

〔Example〕

An embodiment of the present invention will be described with reference to the i-plane.

FIG. 1 is a block diagram of an embodiment of a data failure detection circuit according to the present invention. This embodiment is similar to the conventional example shown in FIG.
Two parity sections are shown, from the parity generation circuit 21 to the parity check circuit 51 and from the parity check circuit 2z to the parity check circuit 52. 1st
In the figure, parts that are the same as the configuration of the conventional example shown in FIG. 2 are given the same reference numerals, and redundant explanation will be omitted.

The parity generation circuits 21 and 22 are connected to the parity rule specification information line 7.
0 are commonly connected. The logical sum circuit 3a and the logical product circuit 8b are the logical sum of the fault information of the check result output information lines 61 and 62 of the parity check circuits 51 and 52, respectively.
Take a logical product. 2-1 selector 9 outputs the output of the logical sum circuit 8al when the information on the parity rule specification information line 70 specifies the odd parity rule, and outputs the output of the AND circuit 8b when the information specifies the even parity rule as check result output information 1fJ60. Output.

Next, the operation of this embodiment will be explained.

(1) Normally, the instruction from the parity law specification information line 70 is the parity parity law, and the 2-1 selector 9 selects the OR circuit 8a. At this time, if there is a failure in at least one of the memory circuits 41 or 42, the OR circuit 8
The output of a becomes logic l, and failure information is output to the check result output information line 60 of the 2-l selector 9.

(2) Next, when checking the normal operation of the parity generation circuits 21 and 22 and the parity check circuits 51 and 52, the information @i from the parity rule designation information line 70 is changed to the even parity rule. As a result, 2-1 selector 9
selects the AND circuit 8b. Then, only when fault information is output to both the check result output information lines 61 and 62, the output of the AND circuit 8b becomes logic @1'', and 2-1
Fault information indicating that the normality of the parity generation circuits 21 and 22 and the parity check circuits 51 and 52 has been confirmed is output to the check result output information line 60 of the selector 9.

Note that a NOR circuit and an AND circuit 8 are used instead of the OR circuit 8a.
A NAND circuit may be used instead of b.

〔Effect of the invention〕

As explained above, the present invention makes the parity rule specification information common to m parity generation circuits, and furthermore, m
By making the output of a gate circuit that takes an OR or a NOR of failure information of m parity check circuits corresponding to m parity generation circuits on one side the same as the failure determination information, a flip-flop that holds parity rule instruction information can be used. This has the effect of reducing the amount of hardware required for the loops and answer circuits for maintenance scanning, and also simplifies maintenance by reducing the number of failure display points.

[Brief Description of the Drawings] Fig. 1 is a block diagram of an embodiment of a data failure detection circuit using parity information according to the present invention, and Fig. 2 is a block diagram of a conventional example of a data failure detection circuit using parity information. It is. 11.12...Data line, 21.22...Parity generation circuit, 81.82...Parity information line, 41.42...Memory circuit, 51.52...Parity check circuit, 60. 61.
(52... Check result output information line, 70... Parity rule specification information line, 8a... OR circuit, 8b... AND circuit, 9... 2-1 selector.

Claims (1)

[Scope of Claims] A parity generation circuit that generates parity information for n-bit (n≧1) data, and a parity check circuit that draws in the parity information and the n-bit data to check the normality, The parity generating circuit has m parity sections (m≧
In the data failure detection circuit of 2), each of the parity rule specification information lines is commonly connected to share the parity rule specification information, and at least one of the check result output information of the m parity check circuits indicates that there is a failure. a first gate circuit that outputs a predetermined logic value signal when the m parity check circuits indicate a failure; and a first gate circuit that outputs a predetermined logic value signal when the check result information of the m parity check circuits all indicate that there is a failure. a second gate circuit, and the first
A data failure detection circuit comprising a 2-1 selector that selects the output of the second gate circuit or the output of the second gate circuit and outputs it as failure information.