JPH0454643A - Parity generating and checking circuit - Google Patents

Abstract

PURPOSE:To execute the detection even with respect to a fault of a circuit and parts by providing a selector on inputs of both parity bit generating circuits, respectively, and changing a part of two input signals to each other at the time of generating a parity and at the time of checking it. CONSTITUTION:At the time of generating a parity, a direction control signal line 21 becomes '0'. In such a state, an S input of a selector 22 becomes '1', and a Y output becomes a value of an input B. An S input of a selector 23 becomes '0', and a Y output becomes a value of an input A. From parity outputs of parity bit generating circuits 14, 15, a coincidence is taken by an EX-NOR circuit 16, therefore, a composite parity value passes through a gate circuit 20 and is sent out to a parity signal line 13. At the time of checking the parity, Y outputs of the selectors 22, 23 become opposite to the foregoing. From parity outputs of the circuits 14, 15, a coincidence is taken by the circuit 16, therefore, a composite parity value passes through an AND circuit 19 and is sent out to a parity error output line 17. A parity error output of the AND circuit 19 is a parity value generated from signal lines 11, 12 and the signal line 13, and when they are all normal values, they become '0'.

Description

[Detailed Description of the Invention] [Summary] Regarding a circuit that performs parity generation and parity check, when the parity generation circuit and the parity check circuit are configured using the same nine circuit components, it is possible to prevent failure of one circuit component. For the purpose of making it possible to perform detection, a parity bit generation circuit is provided corresponding to the two input signals and generates an output by checking the even parity or odd parity of each input signal. and an EX-NOR circuit that detects a match between the outputs of the two parity bit generation circuits. When generating parity, the output of the EX-NOR circuit is sent out as parity generation, and when checking parity, the output of the EX-NOR circuit is sent out as parity generation. In the parity generation and check circuit which adds the output of the EX-NOR circuit to the input of the parity bit generation circuit and outputs the output of the EX-NOR circuit as a parity error, a selector is provided at the input of both the parity bit generation circuits, It is constructed by exchanging some parts at the time of parity generation and the time of parity check.

[Industrial application field]

The present invention relates to a circuit that performs parity generation and parity checking, and more particularly to a parity generation and check circuit in which the parity generation circuit and the parity check circuit share nine circuit components.

In devices configured using logic circuits such as computer devices and data communication devices, parity is used as a method for detecting data errors when writing and reading data to and from storage elements and storage media. Many checking methods are used.

The parity check method is also widely used as a method for detecting errors when transmitting or receiving data.

When such a parity check method is used, it is desired that the parity generation circuit and the parity check circuit can share nine circuit components.

[Conventional technology]

In the parity check method, a separate signal line is added to the values of the data bus, address bus, or signal lines in a certain range for which error detection is to be performed, and the value of that signal line is If the number of "1"s included in the line is an even number, it is set as 1, or if it is an odd number, it is set as 1. The former is called an odd parity method, and the latter is called an even parity method.

By reading and writing data that includes this parity value, if one bit of the data changes due to an element failure, the parity value will also change, so the parity values are compared before and after reading and writing the data. By doing so, you can confirm the normality of the data.

FIG. 3 shows an example of the configuration of a parity generation circuit. Reference numerals 11 and 12 are data buses, etc., which are signal lines from which parity is generated. 13 is a parity generation line. 14.15 shows a parity bit generation circuit,
The circuit 6 is an exclusive OR negative output (EX-NOR) circuit.

Further, FIG. 4 shows an example of the configuration of the parity bit generation circuit, and FIG. 5 shows the function of the parity bit generation circuit of FIG. 4.

As shown in FIG. 5, the parity bit generation circuit shown in FIG. ) becomes r□, and when the number of “1”s in input A-1 is odd, even parity bit (EV
) is "0".

The odd parity bit (OD) is "1".

In the parity generation circuit shown in FIG. 3, each signal line 1 is
1. Generate even parity (EV) of 12 data. Then, the EX-NOR circuit 6 detects whether the two match, and when they match, sends a parity generation signal of 1 to the parity generation line 13.

Further, FIG. 6 shows an example of the configuration of a parity check circuit. Reference numerals 11 and 12 are data buses and the like, which are signal lines from which parity is generated on the parity generation side. 13 is a parity generation line from the parity generation side. Reference numerals 14 and 15 indicate a parity bit generation circuit similar to that shown in FIG. 3, and 17 is a parity error output line.

In FIG. 6, a parity bit generation circuit 14 generates an even parity bit (EV) for the data on the signal line 11, and a parity bit generation circuit 15 generates an even parity bit (EV) for the data on the signal line 12 and the data on the parity generation line 13. Parity Pi)
(EV) is generated. And EX-NOR times! 16 detects whether they match, and generates a parity check result of 0 (no parity error) or 1 (with parity error) on the parity error output line 17 depending on the mismatch or match.

As shown in FIGS. 3 and 6, the parity generation circuit and the parity check circuit are constructed using the same parts. Therefore, it is conceivable to configure the parity generation circuit and the parity check circuit by sharing the same parts.

FIG. 7 shows a conventional parity generation and check circuit, in which the same parts as in FIGS. 3 and 6 are designated by the same numbers, 18 and 19 are AND circuits, 20 is a gate circuit, and 21 is a gate circuit. This is a direction control signal line that controls the direction of data, etc.

For example, O is applied to the direction control signal line 21 during parity generation, and 1 is applied during parity check. Therefore, when generating parity, the AND circuits 18 and 19 are turned off and the gate circuit 20 is turned on, so that the parity bit generation circuits 14 and 15 and the EX-NOR circuit 16 are connected in the same way as in the case of FIG. The parity bit is gate times! Parity generation line 13 through 20
sent to.

At the time of parity check, AND circuits 18.19 are turned on and gate circuits 20 are turned off, so that parity bit generation circuits 14.15 and EX-NOR circuits 16 are connected in the same way as in the case of FIG. The output of the check result is generated on the parity error output line 17 via the AND circuit 19.

[Problem to be solved by the invention]

The parity check method is a method for detecting changes in the value of data etc. due to element failures, disconnections in signal lines, etc., but as shown in Figure 7, parity generation and checking are performed in the same way. If nine parts of the circuit are used in common, it may not be possible to detect a failure.

For example, if the parity generation and check circuit malfunctions and writes an incorrect parity value when writing data to a storage element, when reading that data, the parity check circuit operates in the same state and generates an incorrect parity value. Since the check is performed, the read parity value and the checked parity value match. Therefore, in this case, there is a problem that an output indicating that there is no parity error is generated and error detection cannot be performed.

For example, if the parity value that is the output of the parity generation and check circuit becomes a fixed value and becomes stuck, that is, if it becomes a fixed value regardless of the value of the input data, the parity value occurs, and the parity values for writing and reading data always match,
Error detection becomes impossible.

The present invention aims to solve the problems of the prior art, and provides a parity generation and check circuit in which a parity generation circuit and a parity check circuit are configured using two identical circuit components. It is an object of the present invention to provide a parity generation and check circuit that can detect even component failures.

[Means to solve the problem]

FIG. 1 shows the basic configuration of the present invention.

In the present invention, a parity bit generation circuit 1.2 provided corresponding to two input signals checks the even parity or odd parity of each input signal and generates an output, and an EX-NOR circuit 3 generates an output for both parities. By detecting a match between the outputs of the bit generation circuits 1 and 2, the output of the EX-NOR circuit 3 is sent as parity generation when generating parity, and when checking parity, the output of the EX-NOR circuit 3 is sent to the input of one of the parity bit generation circuits. In addition, in the parity generation and check circuit that outputs the output of the EX-NOR circuit 3 as a parity error, selectors 4 and 5 provided at the inputs of both parity bit generation circuits select a part of the two human input signals. This is so that the parity generation time and the parity check time are exchanged with each other.

Further, in the present invention, in the above case, all of the two human input signals are exchanged between each other during parity generation and parity check using the selector 4.5.

Furthermore, the present invention inspects the even parity or odd parity of each input signal using parity bit generation circuits 1 and 2 provided corresponding to two input signals, and EX-
Both parity bit generation circuits 1 and 2 are generated by the NOR circuit 3.
Detects the coincidence of the outputs of both parity bit generation circuits 1,
A selector 4.5 provided at the input of the second input signal exchanges a part or all of the two human input signals with each other during parity generation and parity check. The output is sent as a parity bit generator, and when checking parity, the second gate circuit 7 adds the parity generator to the input of one of the parity bit generator circuits, and the third gate circuit 8 adds the parity generator to the input of one of the parity bit generators.
The output of the X-NOR circuit 3 is output as a parity error.

[Effect]

An output is generated by checking the even parity or odd parity of the two human input signals, and a match between the two outputs is detected, and when parity is generated, the output of the match detection result is sent as parity generation, and when parity is checked, Parity generation is added to the input of one of the parity bit generation circuits to perform parity check, and the output of the match detection result is output as a parity error, and part or all of the two human input signals are used for parity generation and parity check. The parity generation circuit and parity check circuit are the same circuit so that they can be swapped over time.

In a parity generation and check circuit configured using components, it is possible to detect even a failure in two circuit components.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and shows an example of the configuration of a parity generation and check circuit. In the figure, the same parts as in Figure 7 are indicated by the same numbers, and 22
．． 23 is a selector, 24 is an inverter, 25 is a signal line 1
26 represents two signal lines among signal lines 12, 27 represents six signal lines among signal lines 11, and 28 represents six signal lines among signal lines ll. There is.

The selectors 22 and 23 output Y according to the value of the control input S.
Outputs the value of input A or B to In the embodiment shown in FIG. 2, when S=O, Y=A, and when S=1, Y=B.

At the time of parity generation, the direction control signal line 21 becomes 0.

In this state, the S input of the selector 22 becomes 1, and the Y output becomes the value of the input B. The S input of the selector 23 becomes O, and the Y output becomes the value of the input A.

The parity bit generation circuit 14 generates parity bits from six of the signal lines 11 and two of the signal lines 12. The parity bit generation circuit 15 generates parity bits from two of the signal lines 11 and six of the signal lines 12.

The parity outputs of the parity bit generation circuits 14 and 15 are matched by the EX-NOR circuit 16, and the combined parity value is sent to the parity generation line 13 via the gate circuit 20.

At the time of parity check, the direction control signal line 21 becomes 1. In this state, the S input of the selector 22 becomes O, and the Y
The output becomes the value of input A. The S input of the selector 23 becomes 1, and the Y output becomes the value of the input B.

Parity bit generation circuit 14 generates parity bits from eight signal lines 11. Parity bit generation circuit 1
5 generates a parity bit from the eight signal lines 12 and the parity value of the parity generation line 13 inputted via the AND circuit 18.

The EX-NOR circuit 16 matches the parity outputs of the parity bit generation circuits 14 and 15, and the combined parity value is sent to the parity error output line 17 via the AND circuit 19.

The parity error output of the AND circuit 19 is connected to the signal line 11.
12 and the parity generation line 13, and if all values are normal, it will be 0.

Now, as an example of a malfunction in the parity generation and check circuit, for example, if the parity bit generation circuit 14 malfunctions,
Assume that the output is always 0. At this time, the value of the signal line 25 is (0,0), the value of the signal line 26 is (1,O), the value of the signal line 27 is (000000), and the value of the signal line 28 is (00
0000), consider the value of each signal.

When the direction control signal line 21 is O, the input of the parity bit generation circuit 14 is (10000000) and the output of the parity bit generation circuit 14 is EV=0, but since the parity bit generation circuit 14 is assumed to be faulty, , the output of the parity bit generation circuit 14 is originally EV=O.

The input of the parity bit generation circuit 15 is (0000000
0), the output of the parity bit generation circuit 15 becomes EV=1. Therefore, since the output of the EX-NOR circuit 17 becomes O, the value of the parity error output line 17 becomes O, and the value of the parity generation line 13 also becomes 0.

At this time, if the data and parity value are the same and the direction control signal line 21 is 1, the parity bit generation circuit 14
The input is (00000000), and the output of the parity bit generation circuit 14 is EV=1. However, since it is assumed that the parity bit generation circuit 14 is in failure, the output is EV=Q.

The input of the parity bit generation circuit 15 is (1000000
0) and the parity value is 0, and the output of the parity bit generation circuit 15 becomes EV=0.

Therefore, the output of the EX-NOR circuit 16 becomes 1, and the parity error output line 13 becomes 1, indicating that an error has occurred.

Applying the same data to the conventional circuit shown in FIG. 7, when the direction control signal line 21 is O in FIG.
), the output should be EV=1, but due to a failure of the parity bit generation circuit 14, the output becomes EV=0.

The input of the parity bit generation circuit 15 is (10°0000
0) and 0 from the AND circuit 18, and the output is EV=O
becomes. At this time, the output of the EX-NOR circuit 16 becomes 1, and the value of the parity generation line 13 becomes 1. When the direction control signal line 21 is 1, the input of the parity bit generation circuit 14 is (00000000), and the output becomes EV=0 due to a failure. Parity bit generation circuit 15
Since the input is (10000000) and the value of the parity generation line 13 is 1, EV=1.

Therefore, the input of the EX-NOR circuit 16 is (0°1), the output is 0, and the value of the parity error/output line 17 is O, meaning that no error is detected. This result occurs because the failed parity bit generation circuit 14 is used as a parity generation circuit and a parity check circuit with the same data input.

Note that although the above embodiments have been described in the case of even parity, the present invention is not limited thereto, and it goes without saying that it can also be applied to the case of odd parity.

〔Effect of the invention〕

As explained above, according to the present invention, in a parity generation and check circuit in which the same circuit component is used for the parity generation circuit and the parity check circuit, failures in nine circuit components can be detected. This makes it possible to improve the reliability of the parity generation and check circuit.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing an example of the configuration of a parity generation circuit, and Fig. 4 is a diagram showing a parity bit generation circuit. FIG. 5 is a diagram showing the function of the parity bit generation circuit in FIG. 4, FIG. 6 is a diagram showing an example of the configuration of the parity check circuit, and FIG. FIG. 3 is a diagram showing a check circuit. 1.2 is a parity bit generation circuit, 3 is an EX-NOR circuit, 4 and 5 are selectors, and 6 and 7.8 are gate circuits. Figure 4 Figure 5

Claims (3)

[Claims] (1) Parity bit generation circuits (1, 2) which are provided corresponding to two input signals and which check the even parity or odd parity of each input signal and generate an output, and both parity bit generation circuits ( It has an EX-NOR circuit (3) that detects the coincidence of the outputs of 1 and 2), and when generating parity,
The output of the EX-NOR circuit (3) is sent out as a parity signal, and when checking parity, the parity signal is added to the input of one of the parity bit generation circuits, and the output of the EX-NOR circuit (3) is added to the input of one of the parity bit generation circuits. In the parity generation and check circuit that outputs as a parity error, selectors (4, 5) are provided at the inputs of both of the parity bit generation circuits, and a part of the two input signals is used for parity generation and parity check. A parity generation and check circuit characterized in that they are mutually interchangeable. (2) The parity generation and check circuit according to claim 1, wherein the selector (4, 5) switches all of the two input signals between each other during parity generation and parity check. . (3) Parity bit generation circuits (1, 2) that are provided corresponding to two input signals and that check the even parity or odd parity of each input signal and generate an output, and both parity bit generation circuits ( An EX-NOR circuit (3) that detects the coincidence of the outputs of 1 and 2) is provided at the input of both parity bit generation circuits, and is used for parity generation and parity checking of part or all of the 2 input signals. selectors (4, 5) that are mutually switched at different times; a first gate circuit (6) that sends out the output of the EX-NOR circuit (3) as a parity signal when generating parity; and a parity signal when checking parity. a second gate circuit (7) that adds
and a third gate circuit (3) which outputs the output of the EX-NOR circuit (3) as a parity error during parity check.
8) A parity generation and check circuit comprising: