JPH0520219A - Input/output controller - Google Patents

Abstract

PURPOSE:To obtain high integrity by easily detecting also a fault such as data filling or shortage. CONSTITUTION:An I/O control circuit 11 in an I/O controller 3 executes the control of an I/O device 4. A bus control circuit 12 controls a common bus 2. A buffer circuit 13 is connected between the circuits 11, 12. A 1st parity forming/checking circuit 14 executes the parity formation of parity check of data outputted from the circuit 11. A 2nd parity forming/checking circuit 15 executes the parity formation and parity check of data outputted from the circuit 12. The parity formation and parity check are executed by alternately forming and checking odd parities and even parities.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device,
The present invention relates to an input / output control device that requires particularly high data integrity.

[0002]

2. Description of the Related Art A conventional input / output control device fixes a parity to be generated and checked to either odd parity or even parity, and does not have a function of switching between odd parity and even parity. It was

[0003]

The above-mentioned conventional input / output control device has a drawback in that it is not possible to detect a failure that does not change the individual data itself, such as the occurrence or loss of data in the input / output control device. is doing.

[0004]

An input / output control device according to a first aspect of the present invention includes a main storage device, a common bus, an input / output control device and an input / output device, and the main storage device and the input / output control device are the above-mentioned devices. A data processing system connected to a common bus, the input / output device being connected to the input / output control device,
The input / output control device includes an input / output control circuit that connects the input / output device to control the input / output device, a bus control circuit that connects to the common bus to control the common bus, and the input / output control device. A buffer circuit provided between the output control circuit and the bus control circuit; and a first parity generation / check circuit that is connected to the input / output control circuit and performs parity generation and parity check of data of the input / output control circuit. A second parity connected to the bus control circuit for parity generation and parity check of data of the bus control circuit;
And a function of alternately generating odd parity and even parity by the first parity generation / check circuit and the second parity generation / check circuit. It has a function of checking data as even parity.

In the input / output control device of the second invention, the first parity generation / check circuit and the second parity generation / check circuit of the input / output control device of the first invention are:
It has a function of generating parity by repeating odd parity, then odd parity, and then even parity, and a function of checking data as repetition of odd parity, then odd parity, and then even parity.

Further, the input / output control device of the third invention is
A first parity generating / checking circuit and a second parity generating / checking circuit of the input / output control device according to the first aspect of the present invention; and a function of generating parity by repeating odd parity, then even parity, and then even parity. It has a function of checking data by repeating odd parity, then even parity, and then even parity.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an example of a data processing system including an embodiment of the input / output control device of the first invention. The data processing system shown in FIG.
, Common bus 2, input / output control device 3, and input / output device 4
Includes and. The main storage device 1 and the input / output control device 3 are connected to the common bus 2. Further, the input / output device 4 is connected to the input / output control device 3.

The input / output control device 3 controls the input / output device 4, an input / output control circuit 11, a bus control circuit 12 for controlling the common bus 2, an input / output control circuit 11 and a buffer control circuit 12. Between the buffer circuit 13, the first parity generation / check circuit 14 for generating and checking the data parity of the input / output control circuit 11, and the generation and checking of the data parity of the buffer control circuit 12. And a second parity generation / check circuit 15 for performing.

Therefore, the data read from the input / output device 4 enters the input / output control circuit 11, and the first parity generation / check circuit 14 alternately generates odd parity and even parity to generate the respective data. Is sent to the buffer circuit 13. The data in the buffer circuit 13 is sent to the buffer control circuit 12 and is alternately checked by the second parity generation / check circuit 15 as odd parity and even parity, and then stored in the main storage device 1 via the common bus 2. Sent. When the buffer circuit 13 has data leaking or missing, even if the parity of each data is correct, the order of the odd parity and the even parity is out of order, so that the failure can be detected.

FIG. 2 is a block diagram showing an example of a data processing system including an embodiment of the input / output control device of the second invention. The data processing system of FIG. 2 has the same configuration as that of FIG. 1 and is different in that the buffer circuit 13A of the input / output control device 3A has a data width of 2 bytes.

Therefore, the data read from the input / output device 4 enters the input / output control circuit 11 and is repeated by the first parity generation / check circuit 14A for odd parity, then odd parity, and then even parity. Parity is generated, added to each data, and sent to the buffer circuit 13A. The data of the buffer circuit 13A is
It is sent to the buffer control circuit 12 and checked by the second parity generation / check circuit 15A as repetition of odd parity, then odd parity, and then even parity, and sent to the main storage device 1 via the common bus 2. To be Even if data of even bytes is leaked or lost in the buffer circuit 13, the order of odd parity, odd parity, and even parity is broken, and a failure can be detected. In this case, the buffer circuit 13A
If there is even-numbered bytes of data coming out or missing, the failure cannot be detected if the odd parity and the even parity are alternately added.

[0013]

As described above, since the input / output control device of the present invention can easily detect a failure such as a data leak or a loss, it has an effect of having high data integrity. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a data processing system including an embodiment of an input / output control device of the first invention.

FIG. 2 is a block diagram showing an example of a data processing system including an embodiment of the input / output control device of the second invention.

[Explanation of symbols]

1 main memory 2 common buses 3,3A I / O controller 4 I / O device 11 Input / output control circuit 12 Buffer control circuit 13,13A buffer circuit 14, 14A First parity generation / check circuit 15, 15A Second parity generation / check circuit

Claims (3)

[Claims] 1. A main storage device, a common bus, an input / output control device, and an input / output device, wherein the main storage device and the input / output control device are connected to the common bus, and the input / output device is the input / output control device. In a data processing system connected to a device, the input / output control device includes an input / output control circuit for connecting the input / output device to control the input / output device, and an input / output control circuit for connecting the common bus to the common bus. A bus control circuit for controlling, a buffer circuit provided between the input / output control circuit and the bus control circuit, and a parity generation and a parity check of data of the input / output control circuit connected to the input / output control circuit. A first parity generation / check circuit for performing, and a second parity generation for performing parity check and parity check of data of the bus control circuit connected to the bus control circuit. / Check circuit, the first
, And the second parity generation / check circuit have a function of alternately generating odd parity and even parity, and a function of alternately checking data as odd parity and even parity. I / O controller. 2. A function of the first parity generation / check circuit and the second parity generation / check circuit according to claim 1, for generating parity by repeating odd parity, then odd parity, and then even parity. 2. The input / output control device according to claim 1, further comprising a function of checking data by repeating odd parity, odd parity, and even parity. 3. The function of the first parity generation / check circuit and the second parity generation / check circuit according to claim 1 to generate parity by repeating odd parity, then even parity, and then even parity. The input / output control device according to claim 1, further comprising a function of checking data by repeating odd parity, even parity, and then even parity.