JPH05257822A - Data buffer - Google Patents

Abstract

PURPOSE:To detect address fault in writing and reading and fault in overwriting and overreading without increasing the number of bits of the storage circuit of an FIFO data buffer. CONSTITUTION:This data buffer has an EX-OR circuit 10 which EX-ORs the parity bit of write data with the parity bit of a write address register 1, a means which inputs the parity bit of the write data to the EX-OR circuit 10 and writes the write data and the output of the 1st EX-OR circuit 10 in a storage circuit 5, an EX-OR circuit 11 which EX-ORs the parity bit of the stored data with the parity bit of a read address register, and a means which adds the output of the EX-OR circuit 11 as a parity bit to the read storage data to generate read data; and the parity of the read data is checked. The fault of the data buffer can be detected by the conversion and reproduction of the input data by those EX-OR circuits 10 and 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is particularly applicable to first-in
It relates to a first-out (hereinafter FIFO) data buffer.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of an example of a conventional FIFO data buffer.

This data buffer is composed of a write address register 1 composed of 3 bits + parity bits, a +1 circuit 2 for adding 1 to the value of the write address register 1 including the parity bits, and 3 bits + parity bits. Read address register 3 and the value of the read address register 3 is incremented by 1 including the parity +1 circuit 4
And data is written in the word indicated by bits 1 and 2 of the write address register 1, and data is read from the word indicated by bits 1 and 2 of the read address register 3, and writing and writing in the memory circuit 5. Of the write address register 1 at the time of reading, reading from the storage circuit 5, and read address register 3 at the time of reading
And a write / read control circuit 6 for controlling the update of the data and a parity check circuit 7 for checking the odd parity of the read data and transmitting an error signal a if the parity is abnormal.
And a parity check circuit 8 that checks the odd parity of the write address register 1 (3 bits + parity bit) and sends out the error signal b if the parity is abnormal.
And a parity check circuit 9 for checking the odd parity of the read address register 3 (3 bits + parity bit) and transmitting an error signal c if the parity is abnormal.
Consists of.

The write / read control circuit 6 will be described in detail. As described above, the write / read control circuit 6 is a circuit that controls writing to the memory circuit 5, updating of the write address register 1 at the time of writing, reading from the memory circuit 5, and updating of the read address register 3 at the time of reading. However, the following two controls are also performed as a part of these controls. The first control monitors the difference between the values of the write address register 1 and the read address register 3, and when (value of write address register 1) − (value of read address register 3) = “100”, Since the storage circuit 5 is shown to be full of valid data, it is a control for suppressing writing to the storage circuit 5 and updating of the write address register 1 at the time of writing, and the second control is (write address Register 1 value)-(Read address register 3 value) = "00
When it is "0", it means that there is no valid data in the memory circuit 5, and therefore the control is for suppressing reading from the memory circuit 5 and updating of the read address register 3 at the time of reading.

Next, the operation of this data buffer will be described with reference to FIG.

Write data (4 bits +
Parity bits), bits 1 and 2 of write address register 1 (hereinafter referred to as write address) and bits 1 and 2 of read address register 3 (hereinafter referred to as read address) are supplied. The write data is written in the word indicated by the write address of the memory circuit 5 according to the instruction of the write / read control circuit 6, and the write address register 1 is updated at the same time. Further, according to an instruction from the write / read control circuit 6, data is read from the word indicated by the read address of the memory circuit 5, and the read address register 3 is updated at the same time. The read data is used as read data while the parity check circuit 7 is used.
The parity is checked by and if there is an error, an error signal a is transmitted (a failure is detected). Apart from these operations, the parity check circuit 8 or 9 checks the parity of the write address register 1 (3 bits + parity bit) and the read address register 3 (3 bits + parity bit), respectively. Or c is sent (a fault is detected).

[0007]

However, in the conventional fault detection circuit shown in FIG. 4 described above, when a fault occurs in the data itself, the fault is detected, but the write address (point in FIG. 4A) and Read address (Fig. 4
When a failure occurs at point B), the failure is not detected, and there is a drawback that data is written to an incorrect address or data is read from an incorrect address.

Further, although the write / read control circuit 6 has failed and it is shown that the storage circuit 5 is full of valid data, the write address to the storage circuit 5 and the write address at the time of writing are written. If the register 1 has been updated (overwrite failure), or even if it indicates that there is no valid data in the memory circuit 5, the read from the memory circuit 5 and the read address register at the time of reading When the update of 3 is performed (overread failure), there is also a drawback that the failure is not detected.

An object of the present invention is to provide a data buffer which detects a write address and a read address failure without increasing the number of bits of a memory circuit and detects an overwrite failure and an overread failure.

[0010]

In the data buffer of the present invention, a first bit of an exclusive OR of each bit of a part or all of write data to the storage circuit and a parity bit of the write address register is obtained. An exclusive OR circuit, means for inputting a predetermined bit of write data to be input to the first exclusive OR circuit to the first exclusive OR circuit, and first exclusive logic Means for storing the output of the sum circuit and the bit of the write data not input to the first exclusive OR circuit as the storage data in the storage circuit, and a part of the data read from the storage circuit Alternatively, a second exclusive OR circuit for exclusive ORing each bit of all and the parity bit of the read address register, and the read data from the storage circuit in advance. Means for inputting the bit to be input to the second exclusive OR circuit to the second exclusive OR circuit, and the output of the second exclusive OR circuit and the exclusive OR circuit. It has a unit for reading out the read data together with the read data that has not been read.

[0011]

When writing data to the memory circuit in the data buffer, a first exclusive OR (hereinafter referred to as EX-OR) is taken by the parity bit of the write address register and the parity bit of the write data, and the output is detected as a fault. A signal for input to the storage circuit which is not input to the first EX-OR circuit, and is stored.
When reading data from the storage circuit, the read data, a signal for fault detection by the second EX-OR circuit, the parity bit of the read address register, and EX-
Overwrite and overread faults are detected by reading the read data and the parity of the read data together with the ORed signal, reproducing the input data to the memory circuit, and checking the parity of the data. You can

Therefore, it is possible to detect the presence or absence of a failure in the read data and the parity of the read data by the parity check circuit.

[0013]

The present invention will be described in detail with reference to the drawings.

FIG. 1 shows a FIFO which is an embodiment of the present invention.
It is a block diagram which shows the structure of a data buffer.

This data buffer is composed of a write address register 1 composed of 3 bits + parity bits, a +1 circuit 2 for adding 1 to the value of the write address register 1 including the parity bits, and 3 bits + parity bits. Read address register 3 and the value of the read address register 3 is incremented by 1 including the parity +1 circuit 4
And write data to the word indicated by bits 1 and 2 of the write address register 1 and read data from the word indicated by bits 1 and 2 of the read address register 3 (4 bits + parity bit) × 4 word storage circuit 5 A write / read control circuit 6 for controlling writing to the memory circuit 5 and updating of the write address register 1 at the time of writing, reading from the memory circuit 5 and updating of the read address register 3 at the time of reading, and odd parity of read data. And a parity check circuit 7 that sends an error signal a if the parity is abnormal, and a parity check circuit 8 that checks the odd parity of the write address register and sends an error signal b if the parity is abnormal. Check the odd parity of the read address register and If there is an abnormality, the parity check circuit 9 which sends out the error signal c and the parity bit of the write data and the parity bit of the write address register 1 are exclusive ORed and the output is parity of the write data to the storage circuit 5. EX-OR circuit 10 as a bit
And the parity bit of the read data from the storage circuit 5, the parity bit of the read address register 3 and EX-
E which is ORed and whose output is the parity of the read data
It has an X-OR circuit 11. FIG. 1 shows an EX-OR circuit 1
It is the same as the conventional example of FIG. 4 except for 0 and the EX-OR circuit 11.

FIG. 2 is a diagram showing the relationship among the write address register 1, the write data and the storage data shown in FIG. 1 of the present embodiment.

FIG. 3 is a diagram showing the relationship among the read address register 3, the stored data and the read data shown in FIG. 1 of the present embodiment.

Next, the operation of the data buffer of the present invention will be described. Here, in the following description, in order to simplify the description, when a data value with a parity bit is shown, “data bit: parity bit” is displayed.
For example, "000: 1" indicates that the data bit is "000" and the parity bit is "1".

First, the operation in a normal state (no failure has occurred) will be described.

In FIG. 1, the write address register 1 is "0".
When the write data “1111: 1” is supplied and the write is instructed at the time of 00: 1 ”(the write address is“ 00: 1 ”), the write / read control circuit 6 controls the storage circuit 5 to operate. “0” is stored in the parity bit of word 0 and “1111” is stored in bits 0 to 3 of word 0 (see FIG. 2), and at the same time, the write address register 1 is incremented by “001: 0” (write address Becomes “01: 0”). Furthermore, the write data “101
When 0: 1 "is supplied and writing is instructed," 1 "is stored in the parity bit of word 1 and" 1010 "is stored in bits 0 to 3 of word 1 of the memory circuit 5 (see FIG. 2). ).

In this state, when read is instructed when the read address register 3 is "000: 1" (read address is "00: 1"), the memory circuit is controlled by the write / read control circuit 6. 5, "0" is read from the parity bit of word 0 and "1111" is read from bits 0 to 3 of word 0, and at the same time, the read address register 3 is incremented by "001: 0" (the read address is "01". : 0 ”). At this time, the read data is "1.
111: 1 "is output (see FIG. 3). The read data is simultaneously subjected to an odd parity check by the parity check circuit 7, but no abnormality (fault) is detected and no error signal a is output. Then, "1" is read from the parity bit of word 1 of the memory circuit 5 and "1010" is read from bits 0 to 3 of word 1, and at the same time, the read address register 3 is incremented by "01".
It becomes 0: 0. At this time, the read data is "101".
0: 1 "is output (see FIG. 3). The read data is simultaneously subjected to odd parity check by the parity check circuit 7, but no abnormality (fault) is detected and the error signal a is not output.

Next, a case where a failure occurs in the read address will be described.

In the above state, the read address "00: 1"
Should be supplied, but if bit 1 fails in the middle and "01: 1" is supplied, "1" is read from the parity bit of word 1 of the memory circuit 5, and bits 0 to 0 of word 1 are supplied.
“1010” is read out from 3, and read data “1010: 0” is output. At the same time, the read data is subjected to an odd parity check by the parity check circuit 7, but an abnormality (fault) is detected and an error signal a is output.

Next, the case where a write address failure occurs will be described.

In the above state, the write address "00: 1"
However, if "01: 1" is supplied as a write address and "1111: 1" is supplied as write data due to a failure in bit 1 in the middle, the memory circuit 5
“0” is stored in the parity bit of the word 1 of “1”, and “1111” is stored in the bits 0 to 3 of the word 1.

In this state, the read address "01: 0"
Is supplied, "0" is output from the parity bit of word 1 of the memory circuit 5, and "1" is input from bits 0 to 3 of word 1.
111 "is read out and the read data is" 1111:
0 "is output. The read data is simultaneously subjected to odd parity check by the parity check circuit 7, but an abnormality (fault) is detected and an error signal a is output.

Next, although the write / read control circuit 6 has failed and the memory circuit 5 shows that there is no valid data, the read from the memory circuit 5 and the read address register 3 at the time of reading are performed. The case where the update has been performed will be described.

The write address register 1 is "100:
0 and the read address register 3 is "100:
When the data is read out when the write address register 1 is "000: 1" when the data is read out when the data is "0" (the state where there is no valid data in the storage circuit 5). For example, "0" is read from the parity bit of word 0 and "1111" is read from bits 0 to 3 of word 0. At this time, the read data has the parity bit of read address register 3 of "0". Therefore, “1111: 0” is output, and the parity check circuit 7 simultaneously performs an odd number parity check on the read data, but an abnormality (fault) is detected and an error signal a is output.

Next, although a failure occurs in the write / read control circuit 6 and the storage circuit 5 is shown to be full of valid data, the write address to the storage circuit 5 and the write address at the time of writing are written. A case where the register 1 is updated will be described.

The write address register 1 is "100:
0 and the read address register 3 is "000:
1 "(memory circuit 5 is full of valid data)
Then, when the data is written, the parity bit of the write address register 1 is "0", so that if the write data is "1111: 1", the parity bit of the word 0 of the memory circuit 5 is "1". , Bit 0 of word 0
“1111” is written in 3. When the reading is instructed thereafter, “1” is read from the parity of word 0 of the memory circuit 5, and “1111” is read from bits 0 to 3 of word 0.
Is read. The read data at this time is "11" because the parity of the read address register 3 is "1".
11: 0 "is output. The read data is simultaneously subjected to an odd number parity check by the parity check circuit 7, but an abnormality (fault) is detected and an error signal a is output.

In the present embodiment, the write data and the read data of the memory circuit 1 are separate signal lines, but there is no problem even if they are made the same by using a three-state element. Further, in this embodiment, the EX-OR for write data is used.
The circuit 10 and the EX-OR circuit 11 for read data take the exclusive OR of only the parity bit of the data,
Moreover, although only one bit is exclusively ORed, the data bits may be other bits than the parity, and the parity of the address and the exclusive OR may be taken for a plurality of bits of data. There is no problem at all.

[0032]

As described above, the data buffer of the present invention does not increase the number of bits of the memory circuit, but not only when the data itself fails, but also when the write address and the read address fail. In addition, it is possible to detect a failure, and it is possible to prevent a data error caused by the occurrence of the failure.

Further, if the memory circuit is filled with valid data but writing has been performed to the memory circuit, or if the memory circuit has no valid data, the Even if the data has been read out, it is possible to detect a failure, and it is possible to prevent a data error due to the occurrence of a failure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO data buffer which is an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship among a write address register 1, write data, and stored data in FIG. 1 of the present embodiment.

FIG. 3 is a diagram showing a relationship among a read address register 3, storage data and read data in FIG. 1 of the present embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional FIFO data buffer.

[Explanation of symbols]

1 write address register (3 bits + parity bit) 2 + 1 circuit (with parity) 3 read address register (3 bits + parity bit) 4 + 1 circuit (with parity) 5 storage circuit (4 bits + parity bit) 6 write / read Control circuit 7 Parity check circuit (4 bits + parity bit) 8 Parity check circuit (3 bits + parity bit) 9 Parity check circuit (3 bits + parity bit) 10 EX-OR circuit (for write data) 11 EX-OR circuit (For read data)

Claims (1)

[Claims] 1. A storage circuit, a write address register for designating a write address to the storage circuit, and having a bit width and a parity bit larger than the bit width used for the write address by 1 bit or more, and the write address register are parity. First addition or subtraction including bits
1 from the bit width used to specify the read address from the arithmetic circuit and the memory circuit
It has a read address register having a bit width larger than the number of bits and a parity bit, a second arithmetic circuit for adding or subtracting the read address register including the parity bit, a write / read control circuit, and a circuit for checking the parity bit. In the data buffer, a first exclusive OR circuit that takes an exclusive OR of each bit of a part or all of the write data to the storage circuit and the parity bit of the write address register; A predetermined means for inputting a bit to be input to the first exclusive OR circuit to the first exclusive OR circuit, an output of the first exclusive OR circuit, and a first exclusive OR Means for storing in the storage circuit as storage data a sum of the bits of the write data not input to the circuit, A second exclusive OR circuit for obtaining the exclusive OR of each bit of a part or all of the data read from the storage circuit and the parity bit of the read address register; and the read data from the storage circuit. The bit to be input to the second exclusive OR circuit, which is determined in advance, is set to the second
Of the second exclusive OR circuit and the read data that has not been input to the exclusive OR circuit and is read as read data. Characteristic data buffer.