JPH07334431A - Fifo memory device and method for improving reliability - Google Patents

Abstract

PURPOSE:To detect the failure of an internal memory by an external circuit or the like without preparing a detecting means by including a diagnostic circuit for diagnosing the failure of the memory in an FIFO memory. CONSTITUTION:A diagnostic part 1a in a diagnostic circuit 20 is connected to a data memory body 6 through a write address bus 2, a write data bus 3, a write control signal 10, a read address bus 4, a read data bus 5 and a read control signal 13, and at the time of detecting abnormality by diagnosis, informs an external control part of a non-coincidence signal 7. Namely the diagnostic part 1a compares written data with read data, and when both the data are different from each other, informs the external control part of the signal 7. The external control part records the signal 7 and stops the operation of an FIFO memory device 21 when necessary. Thus, data are written/read out in/from all addresses in the body 6 and the non-coincidence of data is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out type (hereinafter referred to as F-type) used in information processing equipment.
(Referred to as IFO) memory.

[0002]

2. Description of the Related Art Conventionally, first-in first-out
There is an abnormality detection method such as providing a function of detecting garbled data when the data is read by adding parity to the data to be written in the memory. However, none has a function of detecting a failure of the internal memory of the FIFO. Therefore, in order to detect a failure, it is necessary to provide a detection mechanism outside the FIFO memory.

For example, Japanese Laid-Open Patent Publication No. 56-94591 (hereinafter referred to as a conventional example) discloses a FIFO memory as follows.
A structure including a FIFO buffer memory and a control circuit and a request receiving circuit provided outside the memory is shown. Here, the control circuit controls writing / reading of data to / from the FIFO buffer memory, the request receiving circuit receives a plurality of write requests, and during the failure diagnosis operation,
The 2-degree signal of the 4-word counter generated inside the control circuit is written as write data in the FIFO buffer memory.

[0004]

However, as shown in the above-mentioned conventional example, even if the failure is detected by the external circuit, the control function of the FIFO is built in the FIFO memory and the failure occurs. In this case, there is a problem that the operation of the FIFO is not guaranteed.

Therefore, the technical problem of the present invention is that the FIFO
The failure of the internal memory can be detected without a means for detecting it by an external circuit or the like. A FIFO memory reliability improving method and a FIFO memory device are provided.

A further technical object of the present invention is to provide a FIFO memory reliability improving method and a FIFO memory device which guarantee the subsequent operation even when a failure is detected in the internal memory of the FIFO.

[0007]

In the present invention, the FI
The FO memory is characterized in that a diagnostic circuit for diagnosing a memory failure and outputting a diagnostic result is built in.

Here, in the present invention, when a failure is detected in the internal memory, a write control section for writing and a read control section for reading are used without using the memory address where the failure is detected. And a first and second address holding unit for holding an address where an abnormality is detected by the diagnosis by the diagnosis circuit, wherein the write control unit sets the first address as a write address to an internal memory. It is preferable that writing is performed without using the address held in the address holding unit, and the read control unit performs reading without using the address held in the second address holding unit as the read address of the data memory. .

Further, in the present invention, the internal memory operates under the control of an external write signal, and operates under the control of an external read signal and a write control section for controlling writing to the data memory by a memory write control signal. And a read control unit for controlling reading from the data memory with a read control signal, and the diagnostic circuit is connected to the internal memory, and the diagnostic circuit is connected to the internal memory by a memory write control signal and a read control signal. Write and read all addresses,
It is preferable that the written data and the read data are compared with each other, and when they do not match, it is determined that there is an abnormality, and a non-coincidence signal indicating the abnormality is output as a failure diagnosis result of the memory.

Further, in the present invention, the diagnostic circuit performs writing and reading at all addresses of the internal memory, compares the written data with the read data, and when they do not match, A diagnostic unit that outputs a non-coincidence signal and outputs a holding signal that prohibits writing and reading with respect to an address of data that does not match, a first prohibited address whose writing is prohibited by the holding signal, and the holding signal. A first address holding unit and a second address holding unit that respectively hold the second prohibited address whose reading is prohibited by the first address holding unit, and the first address holding unit includes the address sent from the write control unit and the second address holding unit. Compare with the first prohibited address,
If they match, the write operation of the write controller is stopped, and the second address holding unit compares the address sent from the data memory with the second prohibited address. If they match, the read control is performed. It is preferable to stop the read operation of the unit.

Further, in the present invention, the first address holding unit outputs a write address match signal when the write address and the first prohibited address match, and the second address holding unit outputs the read address. And the second prohibited address match, the read address match signal is output, and the write control section
The read control unit includes an address counter for holding a write address, a memory control unit for generating the read control signal from the external write signal, and a counter control unit for counting up the address counter by the write address match signal. Includes an address counter that holds the read address, a memory control unit that generates the read control signal from the external read signal, and a counter control unit that counts up the address counter based on the read address match signal. It is preferable.

On the other hand, a method of improving reliability of a FIFO memory device according to the present invention is the method of improving reliability of a FIFO memory device having an internal memory, wherein a diagnostic section for diagnosing the internal memory is built in to improve the reliability of the internal memory. In addition to detecting the failure, the writing or reading is performed without using the memory address in which the failure is detected when the failure is detected in the internal memory.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a FIFO according to a first embodiment of the present invention.
It is a block diagram of an information processing apparatus including a memory device. As shown in FIG. 1, the information processing apparatus includes an external control unit 22 and an F
An IFO memory device 21 is provided. The FIFO memory device 21 includes a diagnostic circuit 20 and a data memory 23. The diagnostic circuit 20 outputs the write control signal and the read control signal to the data memory 23, and outputs the mismatch signal 7 to the external control unit 22. The data memory 23 is also connected via a data bus. The data memory 23 and the external control unit 22 are connected by the external write signal 9 and the external read signal 12, and the write data bus 3 and the read data bus 5 are connected.
Connected through. The external control unit 22 records the mismatch signal 7 from the diagnostic circuit 20 and stops the use of the FIFO memory device 21 as necessary.

FIG. 2 is a block diagram of the FIFO memory device 21 according to the first embodiment of FIG. Referring to FIGS. 1 and 2, a diagnostic circuit 20 and a data memory 23 are provided. The diagnostic circuit 20 includes a diagnostic unit 1a. Also,
The data memory 23 includes a data memory body 6 which is an internal memory, a write controller 8a, and a read controller 11a.
It has and. The diagnostic unit 1a uses the write address bus 2, the write data bus 3, the write control signal 10, and the read address bus 4, the read data bus 5, and the read control signal 13 to form the data memory main body 6
When the abnormality is detected by the diagnosis, the non-coincidence signal 7 is notified to the external control unit 22. Write controller 8a
Operates under the control of the external write signal 9, is connected to the write address bus 2 to the data memory body 6, and controls the write by the write control signal 10. Read control unit 11
a operates under the control of the external read signal 12, is connected to the read address bus 4 from the data memory body 6, and controls the read by the memory read control signal 13.

Next, the operation of the first embodiment of the present invention thus constructed will be described with reference to FIGS. First,
When the diagnostic unit 1a is turned on, it sends the write address to the write address bus 2 and the write data to the write data bus 3 to the data memory body 6, and further outputs the write control signal 10 to output the data memory body 6 to the data memory body 6.
Write to. Further, the same address as the written address is sent to the read address bus 4, the read control signal 13 is output, and the read data is received from the read data bus 5 from the data memory main body 6. The diagnosis unit 1a compares the written data with the read data and, if they do not match, notifies the external control unit 22 with a mismatch signal 7. The external control unit 22 records the mismatch signal 7 and stops the operation of the FIFO memory device 21 as necessary. Data inconsistencies are detected by writing and reading at all addresses in the data memory body 6.

FIG. 3 is a block diagram of the FIFO memory device 21 according to the second embodiment of the present invention shown in FIG.
The modification of an Example is shown. As shown in FIG. 3, in the second embodiment of the present invention, in addition to the configuration shown in FIG. 1, the write control unit 8b of the data memory 23 is added to the diagnostic circuit 20.
And a second address holding unit 15 connected to the read control unit 11b of the data memory 23. Here, the diagnosis unit 1b is configured to detect the first and second address holding units 1 when an abnormality is detected in the diagnosis.
A holding signal 16 for notifying the holding of an address is connected to 4, 15, and the first address holding unit 14 is connected to the write control unit 8b by the address match signal 17 and connected to the data memory body 6 by the write address bus 2. The second address holding unit 15 receives the address match signal 18 and the read control unit 1
1b, read address bus 4 and data memory body 6
It is connected to the.

FIGS. 4 and 5 show the write controller 8b of FIG.
The specific configuration of the read control unit 11b is shown. Figure 4
As shown in, the write control unit 8b counts up to the write address bus 2 by the counter control unit 81 which generates the count signal 114 from the input address coincidence signal 17 and the count signal 84 which is input from the count control unit 81. An address counter 82 for sending out the selected address and a memory control section 83 for outputting the write control signal 10 and the count signal 114 by the external write signal 9 are provided. Further, as shown in FIG. 5, the read control unit 11b has the same configuration as the write control unit 8b of FIG. 4, and has a counter control unit 81 that generates a count signal 114 from the input address coincidence signal 18 and a count control unit. By the count signal 114 input from the unit 81,
An address counter 112 that sends out the counted-up address to the read address bus 4 and a memory control unit 113 that outputs the read control signal 13 and the count signal 84 by the external read signal 12 are provided.

Next, the operation of the second embodiment of the present invention thus constructed will be described with reference to FIGS. 1 and 3 to 5. As in the case of the first embodiment, the diagnosis unit 1b makes a diagnosis, and the written data and the read data are compared. If they do not match, the external control unit 22 is notified with a mismatch signal 7. Hold signal 16 for the first and second
The address holding units 14 and 15 are notified. The first address holding unit 14 holds the address (first prohibited address) sent to the write address bus 2, while the second address holding unit 15 holds the address sent to the read address bus 4 (second (Prohibited address of) is retained. All addresses in the data memory body 6 are written to and read from to detect the mismatch of data, and the mismatched addresses are set to the first and second address holding units 14 and 1.
Hold at 5. Here, when the writing to the FIFO memory device 21 is requested by the external write signal 9, the write control unit 8b sends the write address held in the write address bus 2 from the address counter 82, and the memory control unit 83 Controls the memory write signal to write the data input from the write data bus 3 to the memory body 6. After performing this writing, the memory control unit 113 counts up the address counter 82 by the count signal 84. At this time, the first address holding unit 14 compares the address sent to the write address bus 2 with the held prohibited address, and when they match, the address match signal 17 is notified to the counter control unit 81 and the counter control is performed. The unit 81 repeats the operation of counting up the address counter 82 by the count signal 84 and counting up the address counter 82 which is not notified of the address match signal. As a result, the address that matches the prohibited address held in the first address holding unit 14, that is, the address in which an abnormality is detected by the diagnosis in the writing is determined by the address counter 82.
Controlled not to use.

On the other hand, in the read operation, when the read control unit 11b is requested to read from the FIFO memory device 21 by the external read signal 12, the address counter 112 sends out the read address held in the read address bus 4. Memory controller 1
Reference numeral 13 controls the read control signal 13 to read from the data memory body 6 and output it to the read data bus 5. After reading, the memory control unit 113
Address counter 112 by count signal 114
To count up. At this time, the second address holding unit 1
5 compares the address sent to the read address bus 4 with the held prohibited address, and when they match, notifies the read control unit 11b of the address match signal 18.
When the address match signal 18 is notified, the counter control unit 111 counts up the address counter 112 by the count signal 114, and repeats the operation of counting up the address counter 112 until the address match signal 18 is not notified. By controlling in this way, it is controlled so as not to use the address that has become abnormal in diagnosis, that is, the address counter 112 does not use the address that matches the prohibited address held in the second address holding unit 15. Write and read operations are guaranteed.

[0021]

As described above, according to the present invention, F
When there is a failure in the internal memory of the IFO, it is possible to detect an abnormality without having any external detection means.

Further, according to the present invention, even when the internal memory of the FIFO has a failure, the operation of the FIFO is guaranteed by detecting the address of the failure and operating without using the address.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus including a FIFO memory device according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram of a FIFO memory device according to a first embodiment of FIG.

FIG. 3 is a block diagram of a FIFO memory device according to a second exemplary embodiment of the present invention, showing a modification of the FIFO memory device of FIG.

FIG. 4 is a block diagram of a write controller of the FIFO memory device of FIG.

5 is a block diagram of a read control unit of the FIFO memory device of FIG.

[Explanation of symbols]

 1a, 1b Diagnostic unit 2 Write address bus 3 Write data bus 4 Read address bus 5 Read data bus 6 Data memory body 7 Mismatch signal 8a, 8b Write control unit 9 External write signal 10 Write control signal 11a, 11b Read control unit 12 External Read signal 13 Read control signal 14 First address holding unit 15 Second address holding unit 16 Holding signal 17,18 Address match signal 20 Diagnostic circuit 21 FIFO memory device 22 External control unit 81,111 Counter control unit 82,112 Address counter 83 , 113 Memory controller

Claims (7)

[Claims] 1. A FIFO memory device having an internal memory, wherein a diagnostic circuit for the internal memory is built in to output a failure diagnostic result of the memory. 2. The FIFO memory device according to claim 1, wherein when a failure is detected in the internal memory, a write control section that performs writing without using a memory address where a failure is detected and a read control that performs reading. And a FIFO
Memory device. 3. The FIFO memory device according to claim 1, further comprising first and second address holding units that hold an address in which an abnormality is detected by the diagnosis circuit.
The write control unit writes to the internal memory without using the address held in the first address holding unit as the write address, and the read control unit holds the second address as the read address of the data memory. A FIFO memory device characterized in that reading is performed without using an address held in a section. 4. The FIFO memory device according to claim 1, wherein the internal memory operates under the control of an external write signal, and a write control unit that controls writing to the internal memory by a write control signal, and an external read signal. And a read control unit that controls read from the internal memory by a read control signal.
The diagnostic circuit is connected to the internal memory, writes and reads all addresses of the internal memory by the write control signal and the read control signal, and compares the written data with the read data. When they do not match, it is judged to be abnormal, and a non-coincidence signal indicating that it is abnormal is output as a failure diagnosis result of the memory, and a FIFO memory device is provided. 5. The FIFO memory device according to claim 4, wherein the diagnostic circuit writes and reads at all addresses of the internal memory and compares the written data with the read data. When not done, the non-coincidence signal is output, and also a diagnostic unit that outputs a holding signal that prohibits writing and reading with respect to an address of the data that does not match, and a first inhibition that writing is prohibited by the holding signal. An address and a second forbidden address whose reading is prohibited by the holding signal; and a second address holding unit for holding the address and the first address holding unit for sending from the write control unit. The written address and the first prohibited address are compared, and if they match, the write operation of the write control unit is performed. The second address holding unit compares the address sent from the data memory with the second prohibited address, and stops the read operation of the read control unit if they match. FIFO memory device. 6. The FIFO memory device according to claim 5, wherein the first address holding unit outputs a write address match signal when the write address and the first prohibited address match, and holds the second address hold. If the read address and the second prohibited address match,
The write control unit outputs a read address match signal, the write control unit holds an address counter, a memory control unit generates the read control signal from the external write signal, and the address counter receives the write address match signal. A counter control unit that counts up the read address, the read control unit, an address counter that holds the read address, a memory control unit that generates the read control signal from the external read signal, and a read address match signal. A FIFO including a counter control unit that counts up the address counter.
Memory device. 7. A method of improving reliability of a FIFO memory device having an internal memory, wherein a failure of the internal memory is detected and a failure is detected in the internal memory by incorporating a diagnostic circuit for diagnosing the internal memory. A method for improving reliability of a FIFO memory device, wherein writing or reading is performed without using a memory address in which a failure is detected when detected.