JPH04312148A - Storage device - Google Patents

Abstract

PURPOSE:To process the clearing and diagnosing operations of a memory at a high speed in a subject memory range with a single instruction. CONSTITUTION:A comparator a 6 compares the contents of a start address register 3 with those of an end address register 4, and the writing operations are continuously carried out to a memory in all addresses including the address shown by the register 3 through the address shown by the register 4. Then the memory is cleared. At the same time, the contents of a write data register 9 are written in a RAM 10 in all addresses including the address of the register 3 through the address of the register 4 and then read out and stored in a read data register 11. Then a comparator b12 compares the contents of the register 9 with those of the register 11. Thus the memory is tested.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to storage devices, and more particularly to memory clearing and memory diagnosis.

0002

2. Description of the Related Art Conventionally, this type of storage device decodes commands from an external bus to read from or write to memory. When attempting to clear the memory of an address range in this storage device, the memory is cleared by writing data of ALL "0" to each address in response to a command from an external processor.

Furthermore, this type of storage device inputs commands, data, and addresses from an external bus, decodes the commands, and reads or writes them into the memory. When diagnosing this storage device, writing is performed using a command from an external processor, then reading is performed, and the external processor itself examines the state and performs the diagnosis.

0004

[Problems to be Solved by the Invention] As mentioned above, in conventional storage devices, one data write is performed for one address in the memory, so when attempting to clear a certain memory range of memory, In this case, it is necessary to execute a write instruction for all target addresses,
The disadvantage is that it takes a long time to clear the memory.

[0005] Furthermore, in conventional storage devices, one piece of data is read or written to one address in the memory, so when attempting to diagnose a certain memory range, all Since the read instruction must be executed after the write instruction is executed for the address, the memory diagnosis has the disadvantage that it takes a long time.

[0006] The first object of the invention is to compare the contents of a start address register and an end address register using a comparison circuit, and to compare the contents of a start address register and an end address register, and to compare the contents of a start address register and an end address register, and to compare the contents of a start address register and an end address register, and to compare the contents of a start address register and an end address register. By sequentially writing to memory for all addresses in the memory area and clearing the memory, the above disadvantages can be solved, and the memory clearing of the target memory range can be done in one go.
The purpose is to provide a storage device that can process instructions at high speed.

A second object of the invention is to write the contents of the write data register to the RAM for all addresses from the address indicated by the start address register to the address indicated by the end address register. After that, the above-mentioned drawbacks can be solved and the target memory can be The purpose of the present invention is to provide a storage device that can process diagnosis at high speed with one instruction.

[0008]

[Means for Solving the Problems] A storage device of a first invention has a start address register that stores a start address from an external bus, and an end address register that stores an end address from an external bus. and a comparison circuit that compares the contents of the start address register and end address register, and if the comparison results do not match, the value of the start address register is set to 1.
The memory access completion reporting flip-flop reports that the memory access has ended if the comparison result by the comparison circuit matches.

A storage device according to a second invention includes a write data register for storing data from an external bus, a read data register for storing data read from the memory, in addition to the storage device according to the first invention. Added a second comparison circuit that compares the contents of the write data register with the contents of the read data register, and a memory access control circuit that controls write instructions to the memory, controls read instructions, and controls switching between writing and reading. After storing the contents of the write data register in the memory under the control of the memory access control circuit, the contents are read from the memory again and the read data is stored.
If the comparison result in the second comparison circuit does not match, it is reported as a memory error, and the comparison circuit compares the contents of the start address register and the end address register, and the result matches. if,
The memory access completion report flip-flop is set and the memory access is completed.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

First, an embodiment of the first invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a storage device according to an embodiment of the first invention.

In FIG. 1, the storage device 30 according to the embodiment of the first invention includes a command register 1 that stores a command 101 from a bus 100, a decoder 2 that decodes the command output of the command register 1, bus 100
A start address that stores the start address 102 from
address register 3 and end address register 4 which stores end address 102 from bus 100.
, an adder circuit 5 that adds one value to the value of the start address register 3, a comparator circuit a6 that compares the contents of the start address register 3 and the end address register 4, and the result of the comparison by the comparator circuit a6. A memory function that reports that the memory access is finished if the
an access completion report F/F 7, a memory access control circuit 8 that controls write instructions to the RAM 10, controls read instructions, and controls switching between writing and reading; and a write data register 9 that stores data 103 from the bus 100.
and a RAM 10 that stores the output data of the write data register 9, and is connected to the processor 20.

Next, a normal write operation will be explained.

When command/address data from processor 20 is input via bus 100, it is stored in command register 1, start address register 3, and write data register 9, respectively.

The output of command register 1 is decoded by decoder 2 and sent to memory access control circuit 8.
is notified that it is a write command.

Memory access control circuit 8 includes RAM1
A write instruction is given to 0, and the data in the write data register 9 is written to the RAM 10 at the address indicated by the start address register 3.

When the write operation is completed, the memory access completion report F/F7 is set to end the memory access.

Next, the memory clear operation will be explained.

When a memory clear command is stored in the command register 1 from the processor 20 via the bus 100, the command is decoded by the decoder 2 and processing begins. Since the instruction specifies an address range, the address is input from the bus 100 twice, and is input into the start address register 3 and end address register 3, respectively.
Stored in register 4.

Further, the data 103 to be written to the memory is stored in the write data register 9 via the bus 100.

Since the command is a clear command, the memory access control circuit 8 issues a write instruction to the RAM 10. Since a write instruction has been issued to the RAM 10, the data in the write data register 9 is written to the address indicated by the start address register 3.

The contents of the start address register 3 are incremented by an adder circuit 5 and stored in the start address register 3 again.

The contents of the start address register 3 and the contents of the end address register 4 are compared by the comparison circuit a6, and if they do not match, a write instruction is issued again from the memory access control circuit 8, and the contents are written to the RAM 10. Data is written.

Furthermore, if the comparison results in a match, it means that all target addresses have been accessed, so the memory access control circuit 8 is instructed to terminate the write operation, and the memory access is terminated. Set report F/F7 and end memory access.

Next, an embodiment of the second invention will be described with reference to the drawings.

FIG. 2 is a block diagram of a storage device according to an embodiment of the second invention.

In FIG. 2, the storage device 30 according to the second embodiment of the present invention includes a command register 1 that stores a command 101 from a bus 100, a decoder 2 that decodes the command output of the command register 1, bus 100
A start address that stores the start address 102 from
address register 3 and end address register 4 which stores end address 102 from bus 100.
, an adder circuit 5 that adds one value to the value of the start address register 3, a comparator circuit a6 that compares the contents of the start address register 3 and the end address register 4, and the result of the comparison by the comparator circuit a6. A memory function that reports that the memory access is finished if the
an access completion report F/F 7, a memory access control circuit 8 that controls write instructions to the RAM 10, controls read instructions, and controls switching between writing and reading; and a write data register 9 that stores data 103 from the bus 100.
, a RAM 10 that stores the output data of the write data register 9, a read data register 11 that stores the read data from the RAM 10, and a comparison circuit b12 that compares the contents of the write data register 9 and the read data register 11. and is connected to the processor 20.

Next, a normal write operation will be explained.

When command/address data from processor 20 is input via bus 100, it is stored in command register 1, start address register 3, and write data register 9, respectively.

The output of command register 1 is decoded by decoder 2 and sent to memory access control circuit 8.
is notified that it is a write command.

The memory access control circuit 8 includes RAM1
A write instruction is given to 0, and the data in the write data register 9 is written to the RAM 10 at the address indicated by the start address register 3.

When the write operation is completed, the memory access completion report F/F7 is set to end the memory access.

Next, a normal read operation will be explained.

When a command address is input from the processor 20 via the bus 100, it is stored in the command register 1 and start address register 3, respectively.

The output of the command register 1 is decoded by the decoder 2 and transmitted to the memory access control circuit 8 as a read command.

The memory access control circuit 8 includes a RAM 10
The data corresponding to the address indicated by the start address register 3 is read from the RAM 10 and stored in the read register 11. When the contents of the read register 11 are output to the bus 100 and the read operation is completed, the memory access completion report F/F 7 is set.
Terminate memory access.

Next, a memory diagnostic operation for specifying a range will be explained.

When a memory diagnostic instruction is stored in command register 1 from processor 20 via bus 100, the instruction is decoded by decoder 2 and processing begins. Since the instruction specifies an address range, the address is input from the bus 100 twice, and the address is stored in the start address register 3 and end address register 4, respectively.

Further, diagnostic data 103 to be written to the memory is stored in the write data register 9 via the bus 100.

When the decoder 2 specifies that the instruction is a diagnostic instruction, the memory access control circuit 8 instructs the RAM 10 to write the data in the write data register 9 to the address indicated by the start address register 3. conduct. Subsequently, the memory access control circuit 8 switches the write instruction to a read instruction, reads out the data just written from the RAM 10, and stores it in the read data register 11.

Next, the contents of the write data register 9 and the read data register 11 are compared by a comparison circuit b12.

[0043] If the comparison results do not match, it is determined that a memory error has occurred, and this fact is reported to the request source.

The start address register 3 and comparison circuit b12 store a value in which the next address is incremented by 1 by the addition circuit 5, and write to, read from, and compare with the RAM 10 again. This is repeated until the values of start address register 3 and end address register 4 match.

[0045] If the contents of the start address register 3 and the contents of the end address register 4 are compared by the comparator circuit a6 and the results match, it means that the memory diagnosis for all target addresses has been completed. Therefore, the memory access completion report F/F7 is set and the memory diagnostic operation is ended.

[0046]

As explained above, the storage device of the present invention compares the contents of the start address register and the end address register with the comparison circuit, and calculates the end address from the address indicated by the start address register. By continuously writing to memory for all addresses up to the address indicated by the address register and clearing the memory, the effect is that memory clearing of the target memory range can be processed at high speed with one instruction. be.

Furthermore, after writing the contents of the write data register to the RAM for all addresses from the address indicated by the start address register to the address indicated by the end address register, the contents are read out and stored in the read data register. By performing a memory test by comparing the contents of the write data register and the read data register with a comparison circuit, there is an effect that diagnosis of the target memory can be processed at high speed with one instruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage device according to an embodiment of the first invention.

FIG. 2 is a block diagram of a storage device according to an embodiment of the second invention.

[Explanation of symbols]

1 Command register 2 Decoder 3 Start address register 4 End address register 5 Addition circuit 6 Comparison circuit a 7 Memory access completion report F/F 8
Memory access control circuit 9 Write data register 10 RAM 11 Read data register 12 Comparison circuit b 20 Processor 30 Storage device 100 Bus 101 Command 102 Address 103 Data

Claims (2)

[Claims] 1. A start address register that stores a start address from an external bus; an end address register that stores an end address from the external bus; a comparison circuit that compares the contents of the address register; an addition circuit that adds one value to the start address register and moves to the next operation if the comparison results do not match in the comparison circuit; 1. A storage device comprising a memory access completion reporting flip-flop that reports that the memory access has ended if the comparison results match. 2. The storage device according to claim 1, comprising: a write data register for storing data from an external bus; a read data register for storing data read from the memory; and a write data register for storing data read from the memory. A second comparison circuit that compares the contents of the read data register and a memory access control circuit that controls writing and reading instructions to the memory and switching between writing and reading are added. After the contents of the write data register are stored in the memory under the control of a control circuit, the contents are read from the memory again and stored in the read data register, and if the comparison result in the second comparison circuit does not match, , the contents of the start address register and the contents of the end address register are compared by the comparison circuit, and if the results match, the memory access completion report flip-flop is set, and the memory access is completed. A storage device characterized in that access is terminated.