JPH1083384A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer which controls the operation of an external extension interface in an external memory extending mode to output no signal to be noise to the external extension interface at the time of utilizing an internal memory and utilizing the external extension interface as an external extension I/O interface at the time of not using an external extension memory. SOLUTION: An identification signal expressing whether a decoded address indicates the internal memory or the external extension memory is outputted (step 46) and when an internal memory access signal is outputted, a signal from the external extension interface to outside is disconnected. In addition, the state of the external extension interface is switched to the state of the external extension memory interface or the state of an I/O interface according to the access of CPU.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer having a CPU, an internal memory, a system bus, and an external extension interface.

[0002]

2. Description of the Related Art In a computer system, an external extension interface is used to expand system resources in addition to a basic configuration and to provide flexibility. Devices connected to the external expansion interface include an external expansion memory and various I / O devices.

The operation of the microcomputer when the external expansion memory is connected to the external expansion interface in the external memory expansion mode will be described with reference to FIG. 10 while focusing on the external expansion interface.

In FIG. 10, reference numeral 101 denotes a CPU;
Is an internal memory, 103 is an external extension interface, 10
4 is an extension memory, and 105 is a system bus. The system bus 105 includes an address bus 105a and a data bus 10
5b, a control bus 105c. The control bus 105c further includes a memory / * I / O signal line 105c1, a read / *
It comprises a write signal line 105c2, an * address strobe signal line 105c3, a * ready signal line 105c4, a normal / * error signal line 105c5, and others. Here, a signal marked with * indicates negative logic. In the following explanation *
A signal with a sign indicates negative logic. C
The PU 101, the internal memory 102, and the external extension interface 103 are connected to a system bus 105, respectively.
03 is connected.

When the CPU 101 performs data input / output, a positive value ( (Memory cycle) / * Set a signal of a negative value (I / O cycle). When the positive state is selected, the bus starts a memory cycle. The external extended memory 104 sequentially transitions from the subsequent address reading process through the internal memory 102 allocated to the memory map space and the external extended interface 103 in the external extended mode. Where I
The I / O device assigned to the / O map space ignores the memory cycle and does not take in the address.

[0006]

In the conventional microcomputer, when the external expansion memory is mounted in the external memory expansion mode, a memory cycle issued even when the CPU accesses the internal memory 62 exclusively is used.
An address bus 6 is connected to the address lines and data lines of the external expansion memory via the external expansion interface in the external expansion mode.
5b, a signal is output to the data bus 65c. This signal was adversely affecting the operation of the system as noise. In particular, when the microcomputer is a portable terminal with wireless communication means, the effect is remarkable. Also, when the external memory expansion mode is set for connection to the external expansion memory, even if the external expansion memory is not used, the external expansion interface terminals cannot be used as external expansion I / O terminals.

SUMMARY OF THE INVENTION It is an object of the present invention to solve a problem that occurs when the CPU does not use the external expansion memory for the operation of the external expansion interface in the external memory expansion mode. In other words, when accessing the internal memory, control is performed so that no noise signal is output to the external extension interface and the external extension memory. When the external extension memory is not used, a microcomputer that can use the external extension interface as an external extension I / O interface is used. The purpose is to provide.

Even when the internal memory is accessed as described above, when testing the internal operation of the microcomputer, it is a simple method to monitor signals from the external extension interface. CPU to test internal operation
It is necessary to output a signal generated on the bus when accessing the internal memory through the external extension interface.

[0009]

In order to achieve the above object, a microcomputer according to the present invention comprises the above-mentioned CP.
Address decoding means for decoding an address designated by U; means for outputting an access memory identification signal indicating whether the decoded address indicates an internal memory or an external expansion memory; External signal output cut-off means for not outputting a signal from the external extension interface to the outside when the access indicates the access to the external extension interface, and external access from the external extension interface when the access memory identification signal indicates access to the external extension memory. And an external signal output permitting means for outputting a signal to the external device.

Next, in the microcomputer, when the access to the internal memory is indicated by the access memory identification signal, the external signal output cut-off means is controlled by the CPU which is output from the system bus. It is preferable that the bus cycle signal inverting means for inverting the signal level of the bus cycle signal indicating whether the bus cycle is a memory cycle or an I / O cycle among the commands and inputting the inverted signal to the external extension interface.

Further, in the microcomputer, when the access memory identification signal indicates access to the internal memory, the external extension interface interprets the signal level of the bus cycle signal in a reverse manner, and When the access memory identification signal indicates access to the external extension memory, it is preferable that the external extension interface has a logic for interpreting the signal level of the bus cycle signal as it is.

With this configuration, when the external extension memory is connected to the external extension interface, the CP
When U is accessing the internal memory, it is possible to control the external interface so that noisy signals are not output to the outside, and to solve the problem of the operation of the external expansion interface that occurs when the external memory expansion mode is set. Can be.

Further, the microcomputer according to the present invention comprises:
When performing an operation test inside the microcomputer, an internal test means for forcibly releasing the external signal output cutoff means and outputting an internal signal generated inside the microcomputer as an external signal from the external extension interface is provided.

With this configuration, when testing the internal operation of the microcomputer, a signal generated on the bus when the CPU accesses the internal memory is output to the outside via the external extension interface, and the signal is monitored from the external extension interface. It is possible to provide a simple internal operation test.

Further, the microcomputer of the present invention comprises:
When the CPU does not use the external expansion memory in the external memory expansion mode, the external expansion interface state switching means for switching the state of the external expansion interface between an external expansion memory interface state and an external expansion I / O interface state is provided. The state of the external extension interface used as the external extension memory interface is switched to the external extension I / O interface state by the external extension interface state switching means,
The external extension interface is also used as an external extension I / O interface.

Further, in the microcomputer, the controller of the external extension interface has two logics of an external extension memory control logic and an external extension I / O control logic, and the external extension interface state switching means is provided with the external extension memory control logic. It is preferable that the switching means is a means for selectively switching either the logic or the external extended I / O control logic.

With this configuration, when the CPU does not access the external expansion memory, the state of the external expansion interface in the external memory expansion mode is switched to the external expansion I / O interface state, and the external expansion interface is changed to the external expansion I / O interface. It can also be used as an / O interface, and can solve the problem of the operation of the external expansion interface that occurs when the external memory expansion mode is set.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a configuration diagram of a microcomputer according to a first embodiment of the present invention. In FIG. 1, 11 is a CPU, 12 is an internal memory, 13 is an external extension interface, 14 is an extension memory, and 15 is a system bus. The system bus 15 includes an address bus, a data bus, and a control bus. The control bus further includes a memory / * I
/ O signal line, read / * write signal line, * address strobe signal line, * ready signal line, normal / * error signal line, etc. The CPU 11, the internal memory 12, and the external extension interface 13 are connected to a system bus 15, respectively, and the external extension memory 14 is connected to the external extension interface 13.

FIG. 2 shows the external extension interface 1 of FIG.
3, a control controller 21 connected to a control bus, 22 an address decoder connected to an address bus, 23 an external expansion I / F controller for controlling an external expansion interface, The data input / output of the extension memory 14 is executed. The external extended I / F controller 23 is connected to an address bus via an address decoder 22 and to a control bus via a controller 21.

FIG. 3 shows signals representing the internal operation of the microcomputer. In FIG. 3, 31 is a bus clock supplied to the bus, 32 is an output signal of a memory / * I / O signal line which is a bus cycle signal, 33 is an output signal of a read / * write signal line, and 34 is The output signal of the address bus, 35 is the output signal of the * address strobe signal line, and 36 is the address decoder 22
An internal memory access / * external extended memory access signal, which is an access memory identification signal output for 1, indicates whether the decoded address points to the internal memory or the external extended memory. Reference numeral 37 denotes an output signal of the control controller 21 to the external expansion I / F controller 23, which corrects a memory / * I / O signal which is a bus cycle signal of a control command according to the result of the internal memory access / * external expansion memory access signal. Memory / * I / O secondary signal for inverting the value / negative value and outputting to the external extension interface. 38 is the output signal of the data bus, 39 is the output signal of the * ready signal line, 40 is normal / *
This is the output signal of the error signal line.

The operation of the microcomputer according to the present invention when the CPU 11 accesses the internal memory 12 and when it accesses the external extended memory 14 will now be described. First, the CPU 11 stores the internal memory 1
For example, FIG.
I will explain using.

In step 41, the CPU 11 determines whether the bus cycle to be issued is a memory cycle or not.
Memory / * I / O to declare whether it is O cycle
A signal 32 having a positive value (memory cycle) / * a negative value (I / O cycle) is set on the signal line. Here, since a memory cycle is issued, the memory / * I / O signal 32 is selected to have a positive output. This causes the bus to start a memory cycle. Internal memory 1 allocated to the memory map space
2 sequentially transitions from the next address fetch state onward. Here, the controller 21 stores the memory / * I / O
The positive output of the signal 32 is temporarily held and the external extension I / F
No signal value is given to the controller 23 yet.

Next, at step 42, the CPU 11 sets a signal of positive value (read) / * negative value (write) to the read / * write signal line. Here, since data is read, a positive value output is selected for the read / * write signal 33.
Here, similarly, the controller 21 temporarily holds the positive value output of the read / * write signal 33 and outputs the external expansion I / F.
No signal value is given to the controller 23 yet.

Next, at step 43, the CPU 11 outputs the address of the data to be read to the address bus.
Here, the address signal 3 is applied to the address line of the internal memory 12.
A positive / negative output corresponding to 4 appears. On the other hand, in the external extension interface 13, as the address signal 34, a positive / negative value output appears on the address fetch line of the address decoder 22.

Next, at step 44, the CPU 11 outputs a negative value as the * address strobe signal 35 to the * address strobe signal line to notify the peripheral device that the address signal 34 is being output to the address bus. The internal memory 12 and the address decoder 22 take in the address signal 34 in response to the negative output of the * address strobe signal 35. The fetched address signal 34 is temporarily held.

Next, at step 45, the address decoder 22 decodes the received address signal 34.

In step 46, the address decoder 22 stores the address space of the internal memory and the address space of the external expansion memory, and compares the decoding result with the stored address space. The internal memory access / * external extended memory access signal 3 indicates whether the decoded address points to the internal memory or the external extended memory.
6 is output. Here, since the address for accessing the internal memory is supplied, a positive value (internal memory access)
Output.

Next, at step 47, when the internal memory access / * external expansion memory access signal 36 is output to the controller 21 with a positive value, the temporarily stored memory / * I / O signal 32 is output. The output of the positive value is inverted to output a negative value, and the memory / * I / O secondary signal 37 is supplied to the external expansion I / F controller 23. As a result, the external expansion I / F controller 23 interprets the issued bus cycle as an I / O cycle, so ignores the subsequent cycles and does not take in addresses. Subsequent accesses to the internal memory continue the normal memory cycle.

Next, the operation when the CPU 11 accesses the external extension memory 14 will be described. The case where the CPU 11 executes, for example, data reading to the external extension memory 14 will be described with reference to each step in FIG.

Step 51 is the same as step 41 of FIG. 4. In order for the CPU 11 to declare whether the bus cycle to be issued is a memory cycle or an I / O cycle, a positive signal is applied to the memory / * I / O signal line. Value (memory cycle) / * Signal 32 of negative value (I / O cycle) is set. Since a memory cycle is issued here,
* Positive value output is selected for the I / O signal 32. This causes the bus to start a memory cycle. The internal memory 12 allocated to the memory map space transitions sequentially from the subsequent address fetch state. Here, the controller 21 temporarily holds the positive output of the memory / * I / O signal 32 as described above, and does not yet give the signal value to the external extended I / F controller 23.

Next, step 52 is the same as step 42 in FIG. 4, and the CPU 11 sets a signal of positive value (read) / * negative value (write) to the read / * write signal line. Here, since data is read, a positive value output is selected for the read / * write signal 33. As described above, the controller 21 temporarily holds the positive value output of the read / * write signal 33, and does not yet provide the signal value to the external extended I / F controller 23.

Next, step 53 is the same as step 43 in FIG. 4, and the CPU 11 outputs the address of the data to be read to the address bus. Here, a positive value / negative value output corresponding to the address signal 34 appears on the address line of the internal memory 12. On the other hand, in the external extension interface 13, the address signal 34 appears on the address fetch line of the address decoder 22.

Next, step 54 is the same as step 44 in FIG. 4. In order for the CPU 11 to notify the peripheral device that the address signal 34 is being output to the address bus 15a, the * address strobe signal line is connected to the * address strobe signal line. A negative value is output as 35. The internal memory 12 and the address decoder 22 take in the address signal 34 in response to the negative output of the * address strobe signal 35. As in the above, the fetched address signal 34 is temporarily held.

Next, step 55 is the same as step 45 in FIG. 4, and the address decoder 22 decodes the received address signal 34.

In step 56, the address decoder 22 stores the address space of the internal memory and the address space of the external extension memory, and compares the decoding result with the stored address space. And outputs an internal memory access / * external extended memory access signal 36 which is an access memory signal indicating whether the decoded address points to the internal memory or the external extended memory. Here, since an address for accessing the external extended memory is supplied, the output is a negative value (external extended memory access).

In step 57, when the internal memory access / * external extended memory access signal 36 is output to the controller 21 with a negative value, the positive value of the temporarily held memory / * I / O signal 32 is output. The output is not inverted and is output as a positive value as it is, and the memory / * I / O secondary signal 37 is supplied to the external expansion I / F controller 23. Thus, the external expansion I / F controller 23 interprets that the issued bus cycle is a memory cycle.

The address decoder 22 supplies the temporarily stored address signal 34 to an external memory controller. The external I / F controller 23 takes in the address signal 34, and the subsequent access to the external expansion memory continues in a normal memory cycle. (Embodiment 2) FIG. 6 shows a configuration diagram of a microcomputer according to a second embodiment of the present invention. 6, reference numeral 61 denotes a CPU, 62 denotes an internal memory, 63 denotes an external expansion interface, 64 denotes an expansion memory, 65 denotes a system bus, and 66 denotes an I / O device. The system bus 65 includes an address bus, a data bus, and a control bus. The control bus further includes a memory / * I / O signal line, a read / * write signal line, an * address strobe signal line, a * ready signal line, and a normal / * Consists of error signal lines and others. The CPU 61, the internal memory 62, and the external extension interface 63 are connected to a system bus 65, respectively.
And the I / O device are connected to the external extension interface 63.

FIG. 7 shows the external extension interface 6 of FIG.
3, a control controller 71 connected to the control bus 65c, an address decoder 72 connected to the address bus, an external expansion controller 73, and an external expansion memory control logic 74 inside. It has an external extension I / O control logic 75, the external extension memory control logic 74 controls the external extension interface, executes data input / output of the external extension memory 64, and the external extension I / O control logic 75 controls the external extension interface. Control and external extension I
The data input / output of the / O device 66 is executed. The external extension controller 73 is connected to an address bus via an address decoder 72 and to a control bus via a control controller 71.

First, the case of accessing the external extension memory 64, for example, the case of reading data will be described with reference to FIG.

In step 81, the CPU 61 determines whether the bus cycle to be issued is a memory cycle or not.
In order to declare whether the cycle is a cycle, a positive value (memory cycle) is applied to the memory / * I / O signal line which is a bus cycle signal.
/ * Set signal 32 of negative value (I / O cycle). Here, since a memory cycle is issued, the memory / * I /
As the O signal 32, a positive output is selected. This causes the bus to start a memory cycle.

Next, in step 82, the external expansion memory control logic 74 is selected in the external expansion interface controller 63. As a result, the external expansion interface controller 63 operates as an external expansion memory controller until the selection is changed thereafter. Next, in step 83, the CPU 61 causes the read / *
Set a signal of positive value (read) / * negative value (write) to the write signal line. Since the data is read here, read /
* A positive value output is selected for the write signal 33.

Next, at step 84, the CPU 61 outputs the address of the data to be read to the address bus.

Next, at step 85, the CPU 61 outputs a negative value as the * address strobe signal 35 to the * address strobe signal line in order to notify the external extension memory 64 that the address signal 34 has been output to the address bus. Triggered by the output of the negative value of the * address strobe signal 35, the external extension interface controller 63 takes in the address signal 34.

Next, in step 86, the external extension interface controller 63 decodes the fetched address signal 34 and shapes necessary data for output to the external extension memory 64.

In step 87, a process of reading data stored at the designated address is performed.

Next, referring to FIG. 9, when using the external extension interface as an external extension I / O interface,
For example, a case where data is read from the I / O device 66 will be described.

In step 91, the CPU 61 determines whether the bus cycle to be issued is a memory cycle or not.
In order to declare whether the cycle is an O cycle, a signal 32 of a positive value (memory cycle) / * a negative value (I / O cycle) is set on a memory / * I / O signal line which is a bus cycle signal. Here, since an I / O cycle is issued, the memory /
* A negative value output is selected for the I / O signal 32. This causes the bus to start an I / O cycle.

Next, at step 92, the I / O control logic 75 is selected in the external extension interface controller 63. This allows the external extension interface controller 63 to change the selection thereafter.
Operates as an I / O controller.
In step 3, the CPU 61 sets a signal of positive value (read) / * negative value (write) to the read / * write signal line. Since the data is read here, the read / * write signal 33
Is selected as a positive output.

Next, at step 94, the CPU 61 outputs the address of the data to be read to the address bus.

Next, at step 95, the CPU 61 outputs a negative value as the * address strobe signal 35 to the * address strobe signal line in order to notify the external extension controller that the address signal 34 has been output to the address bus. Triggered by the output of the negative value of the * address strobe signal 35, the external extension interface controller 63 takes in the address signal 34.

Next, at step 96, the external extension interface controller 63 decodes the received address signal 34. The external extension interface controller 63 divides the decoded address into upper bits and lower bits, and shapes the data. Originally, the effective address of the I / O map space is only the lower bits, and the upper bits are ignored.

In step 97, the shaped address data is output to the I / O device 66 via the external extension interface 63.

After the above steps, a process of reading data from the designated I / O device 66 is performed.

In order to prevent the I / O data from accessing the external memory, an external extension interface terminal corresponding to the upper bits of the address is required to generate a memory enable signal. External extension interface terminals corresponding to the other lower bits of the address can be used as external extension I / O terminals.

[0055]

As described above, according to the microcomputer of the present invention, the problem of the operation of the external expansion interface in the external memory expansion mode when the CPU does not use the external expansion memory can be solved. In other words, when the CPU accesses the internal memory, it is possible to provide a microcomputer which performs control so as not to output a noise signal to the external extension interface and the external extension memory, and is applicable to a portable terminal with wireless communication means. The effect of noise can be reduced.

When testing the internal operation of the microcomputer, a signal generated on the bus when accessing the internal memory of the CPU can be output to the outside through the external extension interface. Can be provided.

Further, it is possible to provide a microcomputer which can use the external expansion interface in the external memory expansion mode as an external expansion I / O interface, and to effectively use the external expansion interface even in a portable computer having a small housing. Yes, the number of external extension interfaces can be secured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an external extension interface according to the first embodiment of the present invention.

FIG. 3 is a timing chart of a transaction output signal of a system bus of the microcomputer according to the first embodiment of the present invention;

FIG. 4 is a flowchart of processing steps when accessing an internal memory of a microcomputer according to the first embodiment of the present invention;

FIG. 5 is a flowchart of processing steps when accessing an external extended memory of the microcomputer according to the first embodiment of the present invention;

FIG. 6 is a configuration diagram of a microcomputer according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of an external extension interface according to a second embodiment of the present invention;

FIG. 8 is a flowchart of processing steps when accessing an external extended memory of a microcomputer according to the second embodiment of the present invention.

FIG. 9 is a flowchart of processing steps when accessing an IO device of a microcomputer according to the second embodiment of the present invention.

FIG. 10 is a configuration diagram of a conventional microcomputer.

[Explanation of symbols]

11, 61 CPU 12, 62 Internal memory 13, 63 External extension interface 14, 64 External extension memory 15, 65 System bus 21, 71 Control controller 22, 72 Address decoder 23 External extension I / F controller 24 External extension interface terminal 31 Bus Clock signal 32 Memory / * I / O signal 33 Read / * Write signal 34 Address signal 35 * Address strobe signal 36 Internal memory access / * External extended memory access signal 37 Memory / * I / O secondary signal 38 Data signal 39 * Ready signal 40 Normal / * Error signal 65 System bus 66 I / O device 73 External expansion controller 74 External expansion memory control logic 75 I / O control logic

Claims (6)

[Claims] 1. A microcomputer provided with a CPU, an internal memory, a system bus, and an external extension interface, an address decoding means for decoding an address designated by the CPU, and an externally extended address indicating whether the decoded address points to the internal memory. Means for outputting an access memory identification signal indicating whether the memory is pointing to, and external signal output cutoff means for not outputting a signal from the external extension interface to the outside when the access memory identification signal indicates access to the internal memory; External signal output permitting means for outputting a signal from the external extension interface to the outside when the access memory identification signal indicates an access to the external extension memory; Connect extended memory In case it is, CPU
A microcomputer which does not output a signal from the external interface to the outside when the device is accessing an internal memory. 2. The control circuit according to claim 1, wherein said external signal output cut-off means is used to control a bus cycle of a control command output from the system bus by said CPU when said access memory identification signal indicates access to an internal memory. 2. The microcomputer according to claim 1, wherein the microcomputer is a bus cycle signal inverting means for inverting a signal level of a bus cycle signal indicating whether the cycle is a memory cycle or an I / O cycle and inputting the inverted signal to the external extension interface. 3. The external expansion interface, when the access memory identification signal indicates an access to an internal memory, interprets the signal level of the bus cycle signal in reverse, and the access memory identification signal is 2. The microcomputer according to claim 1, wherein the microcomputer is an external extension interface having logic for interpreting whether the signal level of the bus cycle signal is positive or negative when an access to the external extension memory is indicated. 4. When an operation test inside the microcomputer is performed, the external signal output cut-off means is forcibly released, and an internal signal generated inside the microcomputer is output as an external signal from the external extension interface. 2. The microcomputer according to claim 1, further comprising a test unit, wherein an internal operation can be monitored during an internal operation test of the microcomputer. 5. A microcomputer provided with a CPU, an internal memory, a system bus, an external expansion interface, and an external expansion memory, wherein the state of the external expansion interface is changed to an external expansion memory interface state and an external expansion I / O interface state. External extension interface state switching means for switching, when the CPU does not use the external extension memory in the external memory extension mode, switches the state of the external extension interface used as the external extension memory interface to the external extension interface state By means,
A microcomputer that switches to an external extended I / O interface state and can use the external extended interface as an external extended I / O interface. 6. A controller of the external extension interface has two logics of an external extension memory control logic and an external extension I / O control logic,
The externally extended interface state switching means includes an externally extended memory control logic or an externally extended I / O.
The microcomputer according to claim 5, wherein the microcomputer selectively switches one of the control logics.