JPH052494A - Interruption control system - Google Patents

Abstract

PURPOSE:To connect a circuit having an interruption response function to an extended slot without an interruption response signal. CONSTITUTION:An interruption requesting signal 18 of a circuit 15A having an interruption response function is inputted through an extended slot 14 to a personal computer main body 1 and the output of an address decoder 11A and the AND of an IO read-signal 7 are returned as an interruption response to the circuit 15A. In short, by reading a special address, the interruption response signal is inputted to the circuit 15A. By reading the special address at the beginning of the processing in the interruption routine, the circuit 15A is operated in the sequence of the interruption request, the interruption response and the inherent interruption processing. Then, when the constitution is not obtained, since there is not the means to input the interruption response signal to the circuit 15A, the processing of the interruption response cannot be performed, there is the possibility of the malfunction, and this can be evaded by the interruption control system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit expansion system for a personal computer or the like, and more particularly to an interrupt control system suitable for expanding a circuit having an interrupt function.

[0002]

2. Description of the Related Art Conventionally, an expansion slot has been prepared in a personal computer or the like, and when expanding a circuit requiring an interrupt, it is general to use the interrupt function on this expansion slot.

As an example, a method of expanding a communication circuit as shown in FIG. 2 will be described.

In FIG. 2, reference numeral 1 is a personal computer main body, and 2 is a C on the personal computer main body.
It is PU. A bus controller 13 receives the status 9 from the CPU 2. It also outputs an IO read signal of 7. Reference numeral 3 is an interrupt controller for controlling the interrupt, which outputs the interrupt request signal 6 to the CPU 2 and receives the interrupt response signal 17 from the bus controller 13. The interrupt request signal 6 is output by the interrupt request signal 18 from the communication circuit indicated by 15 on the expansion circuit 10 or the interrupt request signal 21 from the peripheral IC indicated by 20 on the personal computer main body 1. It

Reference numeral 14 denotes an expansion slot, which connects the personal computer main body 1 and the expansion circuit 10. 4 is an address bus, 5 is a data bus, and an expansion slot 1
It is also supplied to 4.

On the extension circuit 10, the address decoders of the communication circuits 15 and 11 for receiving the communication data 16 from the outside, and the read signal generating AND circuit 8 are mounted.

The operation will be described below.

When the communication data 16 is externally input to the communication circuit 15 on the expansion circuit 10, the communication circuit 15 sends the communication data 16 to the CPU 2 on the personal computer main body 1.
Personal computer main body 1 for readers to read
The interrupt request signal 18 is output to the upper interrupt controller 3.

The interrupt controller 3 compares which of the interrupt request 21 generated inside the personal computer main body 1 and the interrupt request signal 18 from the expansion circuit 10 has a higher priority and expands the interrupt request signal. As soon as the priority of the interrupt request signal 18 from the circuit 10 is higher, otherwise, after the interrupt response cycle of the interrupt request 21 generated inside the personal computer main body 1 is completed, The interrupt request signal 6 for performing the interrupt processing of the interrupt request signal 18 from the expansion circuit 10 is output to the CPU 2.

When the CPU 2 receives the interrupt request signal 6 output from the interrupt controller 3, the CPU 2 terminates the cycle that was being performed at the time of receiving the interrupt request signal 6 and becomes ready to accept the interrupt. A response cycle is executed, and at the same time, an interrupt response signal 17 indicating that this interrupt response cycle is being executed is output to the interrupt controller 3 via the bus controller 13.

The interrupt controller 3 receives the interrupt response signal 17
Is input, data for indicating that the interrupt request is output from the extension circuit 10, that is, the interrupt number is output to the CPU 2 in order to perform the interrupt processing of the interrupt request signal 18.

The CPU 2 reads the interrupt number, transfers control to an interrupt processing routine indicated by the read interrupt number, and executes an interrupt processing program such as data reading from the communication circuit 15 written therein. To do.

[0013]

In the above-mentioned prior art, no consideration is given to connecting an expansion circuit equipped with a circuit having a function of returning an interrupt number to an expansion slot.

That is, although it is possible to request an interrupt through the expansion slot, there is no means for knowing the execution of the interrupt response cycle to the interrupt request by the CPU on the personal computer body from the signal of the expansion slot. The circuit having the function of returning the interrupt number cannot output the interrupt number to the CPU.

When generating an interrupt, the extended circuit (1) issues an interrupt request (2) issues an interrupt number in an interrupt response cycle (3) reads data by an interrupt program indicated by the interrupt number, It is assumed that the interrupt process will be performed according to the procedure. However, in the case of the above-mentioned conventional example, (3) is executed by the interrupt processing program after (1), and it is impossible to execute the procedure (2) originally required for the extended circuit. Therefore, the circuit may malfunction.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a circuit for generating an interrupt response signal by using the signal of the conventional expansion slot.

[0017]

Means for Solving the Problems The above-mentioned object is to provide a CPU
, An address decoder, a read signal indicating that the CPU is in a read state, and a function for creating data associated with an interrupt factor, and a valid logical value is input to the interrupt response input terminal. Then, in the circuit including the interrupt control circuit having the function of outputting the data, the address decoder detects that the CPU has accessed the specific address, and the read signal indicates that the CPU is in the read state. In this case, it is achieved by providing means for inputting a valid logical value to the interrupt response input terminal of the interrupt control circuit.

[0018]

When the instruction to read the address assigned to the interrupt response signal of the circuit having the function of returning the interrupt number on the extended circuit is executed in the interrupt processing, the interrupt response signal is generated from this address and the read signal. As a result, the circuit having the function of returning the interrupt number on the extended circuit can know that the interrupt response cycle has come.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the device of the present invention, and 12 is an AND circuit for generating an interrupt response. The communication controller 15A is the communication circuit 15 to which an interrupt controller section is added, and the output of the AND circuit 12 for creating an interrupt response enters the interrupt controller section as an interrupt response signal 19. Further, 11A is an address decoder 11 with an interrupt response address decoder function added. The same parts as those in FIG. 2 are designated by the same reference numerals.

The operation will be described below.

Communication controller 15A on the extension circuit 10
Outputs an interrupt request signal 18 to the expansion slot 14 based on the interrupt request generated by the interrupt controller unit in the communication controller 15A.

When the interrupt controller 3 mounted on the main body 1 of the personal computer receives the interrupt request signal 18, and an interrupt request having a higher priority than the interrupt request signal 18 is waiting for interrupt processing. Waiting until the interrupt processing is completed, and if the interrupt request having the lower priority is waiting for the interrupt processing, the interrupt request signal 18 is accepted before the interrupt processing is performed.

After that, the process is the same as the conventional example until the control is transferred to the interrupt processing routine corresponding to the interrupt request signal 18. However, at this point, communication controller 1 is still
No interrupt response cycle is returned to 5A. The processing of the interrupt processing routine will be described below with reference to the flowchart of FIG.

In the interrupt processing routine, an instruction to read the contents of the address assigned for the interrupt response signal 19 of the communication controller 15A on the expansion circuit 10 is executed.

At this time, the CPU 2 outputs the address assigned for the interrupt response signal 19 of the communication controller 15A on the expansion circuit 10.

Address decoder 11A on the extension circuit 10
Detects that the address assigned for the interrupt response signal 19 of the communication controller 15A is input.

The output of this address decoder 11A and C
When the IO read signals 7 output from the PU 2 become active with each other, the interrupt response creating AND circuit 12 makes its output, that is, the interrupt response signal 19 active.

The communication controller 15A uses the interrupt response signal 1
Since 9 is returned, the interrupt number is output to the data bus 5.

In this way, the CPU 2 reads the interrupt number output to the data bus 5. That is, at this time, the interrupt response signal 19 can be returned to the communication controller 15A, and the output interrupt number can be fetched into the CPU 2 as data.

In the interrupt processing routine, the CPU 2 compares the data read in this way with the values on the interrupt processing branch table created for this data to confirm which interrupt processing is to be performed. Then, as in this example, if the interrupt is due to the completion of the communication data 16, the communication data 16 is read and the interrupt process is ended.

By doing so, as the general program processing for the CPU 2, and for the communication controller 15A, the originally expected (1) issue an interrupt request (2) interrupt response cycle (3) It becomes possible to carry out the processing by the procedure of reading the data by the interrupt program indicated by the interrupt number (3), and the malfunction does not occur.

In this embodiment, the case of adding a circuit to the expansion slot has been described, but the present invention is not limited to this. That is, it goes without saying that the present invention can be applied by configuring a circuit similar to that of this embodiment in the main body of the personal computer.

[0034]

According to the present invention, even in a system in which the interrupt response signal is not output on the expansion slot, by creating the interrupt response signal from the address and the read signal on the expansion slot, It is possible to add a circuit with an interrupt controller function without malfunctioning.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional configuration.

FIG. 3 is a flowchart of an interrupt processing routine according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Personal computer main body, 2 ... CPU on personal computer main body, 3 ... Interrupt controller, 4 ... Address bus, 5 ... Data bus, 6 ... Interrupt request signal from interrupt controller, 7 ... IO read signal, 7A ... read signal, 8 ... read signal creation AND circuit, 9 ... CPU status, 10 ... expansion circuit, 11 ... address decoder, 11A ... address decoder with address decoder function for interrupt response, 12 ... interrupt response Creation AND circuit, 13 ... Bus controller, 14 ... Expansion slot, 15 ... Communication circuit, 15A ... Communication controller, 16 ... Communication data, 17 ... Interrupt response signal to interrupt controller, 18 ... Break from expansion circuit Interrupt request signal, 19 ... interrupt response signal to interrupt controller section, 20 ... peripheral IC, 21 ... personal computer Interrupt request signal on Le computer.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Genko Horiguchi             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Image Information System Co., Ltd. (72) Inventor Jun Masuko             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Image Information System Co., Ltd. (72) Inventor ▲ Taka ▼ Tsutomu Ki             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Image Information System Co., Ltd. (72) Inventor Kazuhisa Nara             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi Image Information System Co., Ltd. (72) Inventor Masahiro Iwai             Hitachi, Ltd. 1 Horiyamashita, Hadano City, Kanagawa Prefecture             In computer electronics (72) Inventor Kazufumi Tomimatsu             Hitachi, Ltd. 1 Horiyamashita, Hadano City, Kanagawa Prefecture             Factory Kanagawa factory (72) Inventor Hitoshi Abe             Hitachi, Ltd. 1 Horiyamashita, Hadano City, Kanagawa Prefecture             Factory Kanagawa factory

Claims (3)

[Claims] 1. A CPU, an address decoder, a read signal indicating that the CPU is in a read state, and a function for creating data associated with an interrupt factor and effective for an interrupt response input terminal. When a logic value is input, the address decoder detects that the CPU has accessed a specific address in a circuit including an interrupt control circuit having a function of outputting the data, and a read signal indicates that the CPU has accessed the specific address.
Means for inputting a valid logical value to the interrupt response input terminal of the interrupt control circuit when the status indicates that the interrupt control circuit is in the read state. 2. An interrupt control circuit and means for inputting a valid logical value to the interrupt response input terminal are provided in the circuit expansion means of the computer device. Interrupt control method. 3. A means for allowing the CPU to read data output when a valid logical value is input to an interrupt response input terminal of the interrupt control circuit. The interrupt control method described in 1.