JPH01116702A - Sequence controller - Google Patents

Abstract

PURPOSE:To process application instruction at high speed by providing a fetching register to have the capacity of several words, and each selective circuit to select an address bus and a data bus. CONSTITUTION:The data of newest several words read by a bit CPU 1 are always stored in a fetching register 5. Consequently, a word CPU 2 to have received a processing request is not necessary to read anew instruction from a sequence program memory 3, and can process the application instruction such as reading the contents of a data memory 4 according to the contents of the fetching register 5. In such a case, the address of the data memory 4 is controlled by an address bus selective circuit 6, the contents of a data bus 17 of a word CPU are controlled by a data bus selective circuit 7, and without reading the contents of an operand, the word CPU 2 can read and write the data designated by the operand.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a sequence controller for controlling machine tools, robots, etc.

"Conventional technology" In the sequence controller, A that corresponds to the relay circuit diagram
Since bit operation instructions such as ND logic are often executed, bit CPL specializes in logical operations for each bit.
J (processing unit) and word C, which specializes in processing ordinary computer instructions such as numerical calculations for each 16-bit word.
Many of them are configured with a multi-CPU system including a PU (processing unit).

The conventional multi-CPU type device, as shown in Figure 6,
Address buses 21, 23 and data buses 22 . of sequence program memory 3 and data memory 4, respectively.
24, a bit CPU1 and a word CPU2 were connected in parallel.

a bit CPU 1 that executes basic instructions such as bit operations;
The word CPU 2, which executes applied instructions such as numerical calculations, is connected to the word CPU 2 by processing request signal lines 25 and 26. Basic control is performed by the bit CPUI, and when bit CPU 1 detects an application instruction, processing request 2 is sent to word CPU 2.
He rolled a 5 and activated Word CPU2. Therefore, the word CP U2 that has received the processing request 25 receives the address of the sequence program memory 3 where the application instruction to be executed is stored, such as bit cPU 1 j>z, and executes the application instruction again. It was necessary to read out the sequence program from the sequence program memory 3 and process it.

Therefore, there is a problem in that when an application instruction is interposed in a program instruction, the processing speed becomes extremely slow.

"Problems to be Solved by the Invention" The present invention has been made to solve the above problems, and while ensuring the processing speed of bit operations (basic instructions), which are the basic processing of sequence controllers, An object of the present invention is to provide a device that can speed up the processing of application instructions.

"Means for Solving Problems" This will be explained with reference to FIG. 1, which is an embodiment drawing. In order to achieve the above object, the present invention provides a multi-CPU type sequence controller that includes bits C and PU1 that mainly perform bit operations, and a word CPU 2 that performs numerical operations.
a fetch register 5 that constantly temporarily stores data on a data bus 12 connected to the data bus 12 by the number of words constituting at least one application instruction; A data bus selection circuit 7 selectively connects to the data bus 17 of the word CPU 2, the output of the fetch register 5, the address bus 14 from the CPU 1, or the address bus 16 from the word CPU 2. An address bus selection circuit 6 selects and connects the address bus 15 of the data memory 4 to the data bus selection circuit 7 and the address bus according to the data on the address bus 16 from the word CPU 2 and the processing request signal 18 from the bit CPU 2. A sequence controller is provided that includes an address decoder circuit 8 that outputs a selection signal to the selection circuit 6.

"Operation" According to the above configuration, the basic command is a dedicated PIP) CP.
The UI allows high-speed processing. On the other hand, fetch register 5
The latest few words of data read by bit CPtJ1 are always stored in bit CPLI.
At the time when 1 detects an applied instruction, several words of data (instructions) such as opcodes and operands constituting the applied instruction are all stored in the fetch register 5. Therefore, the word CPU 2 that receives the processing request does not need to read the instruction from the sequence program memory 3 again, and can process the applied instruction such as reading the contents of the data memory 4 according to the contents of the fetch register 5. It is possible to speed up processing. When processing the application instruction, the address of the data memory 4 is controlled by the address bus selection circuit 6, and the contents of the data bus 17 of word CPtJ are controlled by the data bus selection circuit 7. It becomes possible to read and write data specified by operands without reading the contents, further speeding up the processing of application instructions.

"Example" Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic composition of the embodiment, and FIGS. 2 and 3 are main part block diagrams showing the detailed structure.

This sequence controller includes two CPUs (Central Processing Units): a bit CPUI that executes basic instructions such as bit operations, and a word CPU 2 that executes applied instructions such as numerical calculations. The memory also includes a sequence program memory 3 in which a sequence program for machine control consisting of basic instructions and application instructions is stored;
Data memory 4 in which various data during control is stored
It is equipped with The sequence 10-gram memory 3 and the bit CPUI are directly connected by an address bus 11 and a data bus 12. Data memory 4 and bit CPU
The data bus 13 is directly connected to I, but the address buses 14 and 15 are connected via an address bus selection circuit 6.

A fetch register 5 is connected to the data bus 12 of the sequence program memory 3.

As shown in FIG. 2, the fetch register 5 has four registers 51, 5153, and 54, and has a capacity of 4 words. Data is always stored for the past four times. This 4
If the read data (instruction) is an application instruction, the content of the word is an operation code (51) indicating the type of instruction.
and three operands (52, 53, 54>) indicating a numerical value (constant) to be the object of the instruction or an address of the data memory 4 in which the numerical value is stored.

The output of the fetch register 5 is connected to an address bus selection circuit 6 and a data bus selection circuit 7.

As shown in FIG. 2, the data bus selection circuit 7 has word registers 54 connected to all word registers 51 of the fetch register 5, while the address bus selection circuit 6 has word registers 52 connected to all word registers 51 of the fetch register 5. .53 and 54L are not connected, because the address bus selection circuit 6 requires only three operand parts.

The address bus selection circuit 6 includes the fetch register 5
In addition to the output of the bit, the address bus 14 from the CPU
and an address bus 16 from the word CPU 2 are connected. The address bus selection circuit 6, as shown in FIG.
The output of the three word registers 52, 53, 54 of the fetch register 5 or the bit cpui or one of the address buses 14 and 16 of the word CPU 2 is selected according to the processing request signal REQ from the CPU 1, and the address bus to the data memory 4 is selected. It is possible to connect to 13. for example,
When the processing request signal REQ is not output from the bit CPU 1, the multiplexer 65 outputs the bit CPU
The address bus 14 from to the data memory 4 will be directly connected to the address bus 15 to the data memory 4.

The data bus selection circuit 7 includes the fetch register 5 mentioned above.
In addition to the output of , a data bus 13 from data memory 4 is connected. The data bus selection circuit 7 consists of five gate circuits 71, 72, 73, 74° 75, and receives selection signals C83, C84, CS5 . C
36, it is possible to select any one of the outputs of the four word registers 51-54 of the fetch register 5 or the data bus 13 from the data memory 4 and connect it to the data bus 17 of the word CPUI.

A processing request signal line 18 from the bit CPUI and an address bus 16 from the word CI) U1 are connected to the address decoder circuit 8. As shown in FIG. 3, the address decoder circuit 8 and the decoding circuit 81
It consists of AND gates 82 and 83, and when the signal REQ on the processing request line 18 from the bit CPU 1 is output, it decodes the data on the address bus 16 from the word CPU 2 and outputs the selection signals C8O to C36 for each layer. do. As described above, the data bus selection circuit 7 and the address bus selection circuit 6 are opened and closed by each selection signal C3O-C36.

Bit CPUI and word CPU2 are processing request signal line 1
8, and the processing request signal R is connected from the bit CPUUL.
By outputting EQ, processing by the word CPU 2 is started, and by returning a processing completion signal from the word CPU 2, processing by the bit CPUI is restarted.

FIG. 4 is a flowchart showing the processing at bit CPLJI.

When the bit CPUI process 100 is started, an instruction word is read from the sequence program memory 3 in step 101. Next, in step 102, the instruction word is decoded.Next, in step 103, the instruction word is AND,
It is determined whether the instruction is a basic instruction that performs bit operations such as OR logic, or an applied instruction that performs word-by-word parallel operations such as numerical calculations.

If it is a basic command, the process advances to step 104, executes the process of the command, ends the process, and returns to step 101 again. On the other hand, if it is an application command, the process advances to step 105. In step 105, the processing request signal REQ is sent to the word CPU 2.
Output. Then, in step 106, the word CPU2
The process waits until a process completion signal is returned from , and if the process completion signal is returned, the process is terminated and the process returns to step 101 .

FIG. 5 is a flowchart showing the processing by the word CPU 2.

When the processing request signals RF and Q are output from the bit CPUI, the processing 200 of the word CPU 2 is started. First, in step 201, an operation code is read from the fetch register 5. This is done by outputting a specific address to the address bus 16, which causes the address decoder circuit 8 to output a selection signal C86, and to the gate circuit of the data bus selection circuit 7. 71 and transfers the contents of the word register 51 in which the opcode part of the fetch register 5 is stored to the data bus 1.
7 to read out the operation code.

Next, in step 202, it is determined from the contents of the opcode whether the next operand is an indirect specification instruction that specifies the address of the data memory 4, or a direct specification instruction where the operand itself indicates a constant to be operated on. Discern.

If the instruction is an indirect specification, the process advances to step 203, reads the contents of the data memory 4 specified by the operand part, and
The word is stored in the internal register of CPU2. for example,
The application instructions this time are addition instructions (ADD, OPl, OF2,
0P3). This command ADD is 0■)1
This is an instruction to read and add the contents of the memory address specified by OP2 and the contents of the memory address specified by OP2, and store the result in the memory address specified by OF2. Opcode ADD of the addition instruction
The word CPU 2 decoded outputs a specific address to the address bus 16 in step 203, causes the address decoder circuit f88 to output a selection signal C82, and the gate circuit 61 of the address bus selection circuit 6 and the multiplexer 6
4.65, the first of fetch register 5
Contents of the word register 52 in which the operand part is stored O
Output PI to address bus 15 to data memory 4.

As a result, the data memory 4 outputs the data of the address OPI to the data bus 13, and the word CPU 2 reads the data via the data bus selection circuit 7. Similarly, the word CPU 2 outputs the data of the address OPI to the address bus 16. The contents of the data memory 4 whose memory address is the contents OP2 of the word register 53 of the fetch register 5 are read in step 205.
performs arithmetic processing (addition) and sends the result to the data bus 17.
Output to. At the same time, the gate circuit 63 of the address bus selection circuit 6 is opened by outputting a specific address to the address bus 16, and the contents of the operand OP3 stored in the word register 54 are output to the address bus 15 to the data memory 4. A memory address is specified and the calculation result is stored in the address (OP 3 ).

In this way, even if the application instruction is an instruction that indirectly specifies an operand, the word CPU2 is
P1. OP2. Processing can be performed by mechanically outputting a specific address and activating the address decoder circuit 8 without knowing OP3, thereby speeding up the processing of application instructions.

On the other hand, in step 201, if the instruction is a direct specification instruction in which the operand itself indicates a constant to be operated on, the process proceeds to step 204, outputs a specific address to the address bus 16, and stores the operand in the fetch register. 5 and performs arithmetic processing in step 205. When the arithmetic processing is completed, the process proceeds to step 206.
Returns the processing completion signal to the bit CPUI and returns the current word C.
Ending the processing of PU2 9. In response to the processing completion signal, the bit CPU changes from the standby state of step 106 to step 1.
01 and starts processing the next instruction.

As mentioned above, the word CPU 2 does not need to directly read the sequence program memory 3, and also reads a specific address from the address bus 16 according to the contents of the decoded opcode.
The contents of the operand or the contents of the data memory 4 designated by the operand can be mechanically accessed by simply outputting the output to the input command, thereby increasing the processing speed of application instructions.

"Effects of the Invention" As explained above, the present invention has the above configuration and includes a fetch register having a capacity of several words and each bus selection circuit for selecting an address bus and a data bus. The word CPU, which processes application instructions, can perform processing without having to read out the contents of the sequence program again.

A multi-CPU sequence controller including a bit CPU and a word CPU has the excellent effect of extremely speeding up the processing of application instructions.

[Brief explanation of the drawing]

1 to 5 show an embodiment of the present invention, FIG. 1 is a block diagram showing the basic configuration of the sequence controller of the embodiment, and FIGS. 2 and 3 are block diagrams showing the detailed configuration of the main parts. 4 and 5 are flowcharts showing processing in the bit CPU and word CPU, respectively.
The figure is a block diagram showing a conventional device. 111. Bit CPU, 26. , word CI) U
, 301. Sequence program memory, 410. data memory, 566, fetch register, 681
．． Address bus selection circuit, 7. ,,data bus selection circuit, 800. Address decoder circuit, 11,1
4゜15.16. ,,address bus, 12.13.1
7°, 6 data paths, 18. ,,processing request signal line. Figure 4 Figure 5

Claims (1)

[Claims] In a multi-CPU sequence controller that includes a bit CPU that mainly performs bit operations and a word CPU that performs numerical operations, data on a data bus that connects the sequence program memory and the bit CPU is provided. , a fetch register that constantly temporarily stores the number of words constituting at least one application instruction, and a data bus selection that selects either the output of the fetch register or the data bus from the data memory and connects it to the data bus of the word CPU. an address bus selection circuit that selects one of the output of the fetch register, the address bus from the bit CPU, or the address bus from the word CPU and connects it to the address bus of the data memory; Address bus data and bit C
A sequence controller comprising: an address decoder circuit that outputs a selection signal to the data bus selection circuit and the address bus selection circuit in accordance with a processing request signal from a PU.